Split out arm_atsam shift register logic (#14848)
This commit is contained in:
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@ -50,22 +50,18 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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/* This Shift Register expands available hardware output lines to control additional peripherals */
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/* This Shift Register expands available hardware output lines to control additional peripherals */
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/* It uses four lines from the MCU to provide 16 output lines */
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/* It uses four lines from the MCU to provide 16 output lines */
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/* Shift Register Clock configuration (MCU to ShiftRegister.RCLK) */
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/* Shift Register Clock configuration (MCU to ShiftRegister.RCLK) */
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#define SR_EXP_RCLK_PORT PB
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#define SR_EXP_RCLK_PIN B14
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#define SR_EXP_RCLK_PIN 14
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/* Shift Register Output Enable configuration (MCU to ShiftRegister.OE_N) */
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/* Shift Register Output Enable configuration (MCU to ShiftRegister.OE_N) */
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#define SR_EXP_OE_N_PORT PB
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#define SR_EXP_OE_PIN B15
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#define SR_EXP_OE_N_PIN 15
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/* SERCOM port to use for Shift Register SPI */
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/* SERCOM port to use for Shift Register SPI */
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/* DATAOUT and SCLK must be configured to use hardware pins of this port */
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/* DATAOUT and SCLK must be configured to use hardware pins of this port */
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#define SR_EXP_SERCOM SERCOM2
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#define SPI_SERCOM SERCOM2
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/* Shift Register SPI Data Out configuration (MCU.SERCOMx.PAD[0] to ShiftRegister.SER) */
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/* Shift Register SPI Data Out configuration (MCU.SERCOMx.PAD[0] to ShiftRegister.SER) */
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#define SR_EXP_DATAOUT_PORT PA
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#define SPI_DATAOUT_PIN A12
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#define SR_EXP_DATAOUT_PIN 12
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#define SPI_DATAOUT_MUX 2
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#define SR_EXP_DATAOUT_MUX 2
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/* Shift Register SPI Serial Clock configuration (MCU.SERCOMx.PAD[1] to ShiftRegister.SRCLK) */
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/* Shift Register SPI Serial Clock configuration (MCU.SERCOMx.PAD[1] to ShiftRegister.SRCLK) */
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#define SR_EXP_SCLK_PORT PA
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#define SPI_SCLK_PIN A13
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#define SR_EXP_SCLK_PIN 13
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#define SPI_SCLK_MUX 2
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#define SR_EXP_SCLK_MUX 2
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/* Debug LED (Small LED Located near MCU) */
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/* Debug LED (Small LED Located near MCU) */
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#define DEBUG_LED_ENABLE 1
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#define DEBUG_LED_ENABLE 1
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@ -49,22 +49,18 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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/* This Shift Register expands available hardware output lines to control additional peripherals */
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/* This Shift Register expands available hardware output lines to control additional peripherals */
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/* It uses four lines from the MCU to provide 16 output lines */
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/* It uses four lines from the MCU to provide 16 output lines */
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/* Shift Register Clock configuration (MCU to ShiftRegister.RCLK) */
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/* Shift Register Clock configuration (MCU to ShiftRegister.RCLK) */
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#define SR_EXP_RCLK_PORT PB
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#define SR_EXP_RCLK_PIN B14
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#define SR_EXP_RCLK_PIN 14
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/* Shift Register Output Enable configuration (MCU to ShiftRegister.OE_N) */
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/* Shift Register Output Enable configuration (MCU to ShiftRegister.OE_N) */
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#define SR_EXP_OE_N_PORT PB
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#define SR_EXP_OE_PIN B15
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#define SR_EXP_OE_N_PIN 15
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/* SERCOM port to use for Shift Register SPI */
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/* SERCOM port to use for Shift Register SPI */
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/* DATAOUT and SCLK must be configured to use hardware pins of this port */
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/* DATAOUT and SCLK must be configured to use hardware pins of this port */
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#define SR_EXP_SERCOM SERCOM2
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#define SPI_SERCOM SERCOM2
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/* Shift Register SPI Data Out configuration (MCU.SERCOMx.PAD[0] to ShiftRegister.SER) */
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/* Shift Register SPI Data Out configuration (MCU.SERCOMx.PAD[0] to ShiftRegister.SER) */
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#define SR_EXP_DATAOUT_PORT PA
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#define SPI_DATAOUT_PIN A12
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#define SR_EXP_DATAOUT_PIN 12
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#define SPI_DATAOUT_MUX 2
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#define SR_EXP_DATAOUT_MUX 2
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/* Shift Register SPI Serial Clock configuration (MCU.SERCOMx.PAD[1] to ShiftRegister.SRCLK) */
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/* Shift Register SPI Serial Clock configuration (MCU.SERCOMx.PAD[1] to ShiftRegister.SRCLK) */
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#define SR_EXP_SCLK_PORT PA
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#define SPI_SCLK_PIN A13
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#define SR_EXP_SCLK_PIN 13
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#define SPI_SCLK_MUX 2
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#define SR_EXP_SCLK_MUX 2
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/* Debug LED (Small LED Located near MCU) */
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/* Debug LED (Small LED Located near MCU) */
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#define DEBUG_LED_ENABLE 1
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#define DEBUG_LED_ENABLE 1
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@ -64,7 +64,13 @@ typedef uint8_t pin_t;
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PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
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PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
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} while (0)
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} while (0)
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#define writePin(pin, level) ((level) ? (writePinHigh(pin)) : (writePinLow(pin)))
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#define writePin(pin, level) \
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do { \
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if (level) \
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PORT->Group[SAMD_PORT(pin)].OUTSET.reg = SAMD_PIN_MASK(pin); \
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else \
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PORT->Group[SAMD_PORT(pin)].OUTCLR.reg = SAMD_PIN_MASK(pin); \
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} while (0)
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#define readPin(pin) ((PORT->Group[SAMD_PORT(pin)].IN.reg & SAMD_PIN_MASK(pin)) != 0)
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#define readPin(pin) ((PORT->Group[SAMD_PORT(pin)].IN.reg & SAMD_PIN_MASK(pin)) != 0)
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@ -9,7 +9,8 @@ ifeq ($(RGB_MATRIX_DRIVER),custom)
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SRC += $(ARM_ATSAM_DIR)/md_rgb_matrix.c
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SRC += $(ARM_ATSAM_DIR)/md_rgb_matrix.c
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endif
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endif
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SRC += $(ARM_ATSAM_DIR)/main_arm_atsam.c
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SRC += $(ARM_ATSAM_DIR)/main_arm_atsam.c
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SRC += $(ARM_ATSAM_DIR)/spi.c
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SRC += $(ARM_ATSAM_DIR)/shift_register.c
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SRC += $(ARM_ATSAM_DIR)/spi_master.c
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SRC += $(ARM_ATSAM_DIR)/startup.c
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SRC += $(ARM_ATSAM_DIR)/startup.c
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SRC += $(ARM_ATSAM_DIR)/usb/main_usb.c
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SRC += $(ARM_ATSAM_DIR)/usb/main_usb.c
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@ -27,7 +27,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include "wait.h"
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#include "wait.h"
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#include "adc.h"
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#include "adc.h"
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#include "i2c_master.h"
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#include "i2c_master.h"
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#include "spi.h"
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#include "shift_register.h"
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#include "./usb/usb2422.h"
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#include "./usb/usb2422.h"
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@ -0,0 +1,118 @@
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/*
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Copyright 2018 Massdrop Inc.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_atsam_protocol.h"
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#include "spi_master.h"
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#include "wait.h"
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#include "gpio.h"
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// #define SR_USE_BITBANG
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// Bodge for when spi_master is not available
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#ifdef SR_USE_BITBANG
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# define CLOCK_DELAY 10
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void shift_init_impl(void) {
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setPinOutput(SR_EXP_RCLK_PIN);
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setPinOutput(SPI_DATAOUT_PIN);
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setPinOutput(SPI_SCLK_PIN);
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}
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void shift_out_impl(const uint8_t *data, uint16_t length) {
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writePinLow(SR_EXP_RCLK_PIN);
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for (uint16_t i = 0; i < length; i++) {
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uint8_t val = data[i];
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// shift out lsb first
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for (uint8_t bit = 0; bit < 8; bit++) {
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writePin(SPI_DATAOUT_PIN, !!(val & (1 << bit)));
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writePin(SPI_SCLK_PIN, true);
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wait_us(CLOCK_DELAY);
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writePin(SPI_SCLK_PIN, false);
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wait_us(CLOCK_DELAY);
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}
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}
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writePinHigh(SR_EXP_RCLK_PIN);
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return SPI_STATUS_SUCCESS;
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}
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#else
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void shift_init_impl(void) { spi_init(); }
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void shift_out_impl(const uint8_t *data, uint16_t length) {
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spi_start(SR_EXP_RCLK_PIN, true, 0, 0);
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spi_transmit(data, length);
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spi_stop();
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}
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#endif
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// ***************************************************************
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void shift_out(const uint8_t *data, uint16_t length) { shift_out_impl(data, length); }
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void shift_enable(void) {
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setPinOutput(SR_EXP_OE_PIN);
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writePinLow(SR_EXP_OE_PIN);
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}
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void shift_disable(void) {
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setPinOutput(SR_EXP_OE_PIN);
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writePinHigh(SR_EXP_OE_PIN);
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}
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void shift_init(void) {
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shift_disable();
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shift_init_impl();
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}
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// ***************************************************************
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sr_exp_t sr_exp_data;
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void SR_EXP_WriteData(void) {
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uint8_t data[2] = {
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sr_exp_data.reg & 0xFF, // Shift in bits 7-0
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(sr_exp_data.reg >> 8) & 0xFF, // Shift in bits 15-8
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};
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shift_out(data, 2);
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}
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void SR_EXP_Init(void) {
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shift_init();
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sr_exp_data.reg = 0;
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sr_exp_data.bit.HUB_CONNECT = 0;
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sr_exp_data.bit.HUB_RESET_N = 0;
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sr_exp_data.bit.S_UP = 0;
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sr_exp_data.bit.E_UP_N = 1;
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sr_exp_data.bit.S_DN1 = 1;
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sr_exp_data.bit.E_DN1_N = 1;
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sr_exp_data.bit.E_VBUS_1 = 0;
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sr_exp_data.bit.E_VBUS_2 = 0;
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sr_exp_data.bit.SRC_1 = 1;
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sr_exp_data.bit.SRC_2 = 1;
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sr_exp_data.bit.IRST = 1;
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sr_exp_data.bit.SDB_N = 0;
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SR_EXP_WriteData();
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shift_enable();
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}
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@ -15,28 +15,9 @@ You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#ifndef _SPI_H_
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#pragma once
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#define _SPI_H_
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/* Macros for Shift Register control */
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#include <stdint.h>
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#define SR_EXP_RCLK_LO PORT->Group[SR_EXP_RCLK_PORT].OUTCLR.reg = (1 << SR_EXP_RCLK_PIN)
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#define SR_EXP_RCLK_HI PORT->Group[SR_EXP_RCLK_PORT].OUTSET.reg = (1 << SR_EXP_RCLK_PIN)
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#define SR_EXP_OE_N_ENA PORT->Group[SR_EXP_OE_N_PORT].OUTCLR.reg = (1 << SR_EXP_OE_N_PIN)
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#define SR_EXP_OE_N_DIS PORT->Group[SR_EXP_OE_N_PORT].OUTSET.reg = (1 << SR_EXP_OE_N_PIN)
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/* Determine bits to set for mux selection */
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#if SR_EXP_DATAOUT_PIN % 2 == 0
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# define SR_EXP_DATAOUT_MUX_SEL PMUXE
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#else
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# define SR_EXP_DATAOUT_MUX_SEL PMUXO
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#endif
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/* Determine bits to set for mux selection */
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#if SR_EXP_SCLK_PIN % 2 == 0
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# define SR_EXP_SCLK_MUX_SEL PMUXE
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#else
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# define SR_EXP_SCLK_MUX_SEL PMUXO
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#endif
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/* Data structure to define Shift Register output expander hardware */
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/* Data structure to define Shift Register output expander hardware */
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/* This structure gets shifted into registers LSB first */
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/* This structure gets shifted into registers LSB first */
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@ -66,5 +47,3 @@ extern sr_exp_t sr_exp_data;
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void SR_EXP_WriteData(void);
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void SR_EXP_WriteData(void);
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void SR_EXP_Init(void);
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void SR_EXP_Init(void);
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#endif //_SPI_H_
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@ -1,92 +0,0 @@
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/*
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Copyright 2018 Massdrop Inc.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_atsam_protocol.h"
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sr_exp_t sr_exp_data;
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void SR_EXP_WriteData(void) {
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SR_EXP_RCLK_LO;
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while (!(SR_EXP_SERCOM->SPI.INTFLAG.bit.DRE)) {
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DBGC(DC_SPI_WRITE_DRE);
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}
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SR_EXP_SERCOM->SPI.DATA.bit.DATA = sr_exp_data.reg & 0xFF; // Shift in bits 7-0
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while (!(SR_EXP_SERCOM->SPI.INTFLAG.bit.TXC)) {
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DBGC(DC_SPI_WRITE_TXC_1);
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}
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SR_EXP_SERCOM->SPI.DATA.bit.DATA = (sr_exp_data.reg >> 8) & 0xFF; // Shift in bits 15-8
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while (!(SR_EXP_SERCOM->SPI.INTFLAG.bit.TXC)) {
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DBGC(DC_SPI_WRITE_TXC_2);
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}
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SR_EXP_RCLK_HI;
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}
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void SR_EXP_Init(void) {
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DBGC(DC_SPI_INIT_BEGIN);
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CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
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// Set up MCU Shift Register pins
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PORT->Group[SR_EXP_RCLK_PORT].DIRSET.reg = (1 << SR_EXP_RCLK_PIN);
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PORT->Group[SR_EXP_OE_N_PORT].DIRSET.reg = (1 << SR_EXP_OE_N_PIN);
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// Set up MCU SPI pins
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PORT->Group[SR_EXP_DATAOUT_PORT].PMUX[SR_EXP_DATAOUT_PIN / 2].bit.SR_EXP_DATAOUT_MUX_SEL = SR_EXP_DATAOUT_MUX; // MUX select for sercom
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PORT->Group[SR_EXP_SCLK_PORT].PMUX[SR_EXP_SCLK_PIN / 2].bit.SR_EXP_SCLK_MUX_SEL = SR_EXP_SCLK_MUX; // MUX select for sercom
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PORT->Group[SR_EXP_DATAOUT_PORT].PINCFG[SR_EXP_DATAOUT_PIN].bit.PMUXEN = 1; // MUX Enable
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PORT->Group[SR_EXP_SCLK_PORT].PINCFG[SR_EXP_SCLK_PIN].bit.PMUXEN = 1; // MUX Enable
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// Initialize Shift Register
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SR_EXP_OE_N_DIS;
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SR_EXP_RCLK_HI;
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SR_EXP_SERCOM->SPI.CTRLA.bit.DORD = 1; // Data Order - LSB is transferred first
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SR_EXP_SERCOM->SPI.CTRLA.bit.CPOL = 1; // Clock Polarity - SCK high when idle. Leading edge of cycle is falling. Trailing rising.
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SR_EXP_SERCOM->SPI.CTRLA.bit.CPHA = 1; // Clock Phase - Leading Edge Falling, change, Trailing Edge - Rising, sample
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SR_EXP_SERCOM->SPI.CTRLA.bit.DIPO = 3; // Data In Pinout - SERCOM PAD[3] is used as data input (Configure away from DOPO. Not using input.)
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SR_EXP_SERCOM->SPI.CTRLA.bit.DOPO = 0; // Data Output PAD[0], Serial Clock PAD[1]
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SR_EXP_SERCOM->SPI.CTRLA.bit.MODE = 3; // Operating Mode - Master operation
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SR_EXP_SERCOM->SPI.CTRLA.bit.ENABLE = 1; // Enable - Peripheral is enabled or being enabled
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while (SR_EXP_SERCOM->SPI.SYNCBUSY.bit.ENABLE) {
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DBGC(DC_SPI_SYNC_ENABLING);
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}
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sr_exp_data.reg = 0;
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||||||
sr_exp_data.bit.HUB_CONNECT = 0;
|
|
||||||
sr_exp_data.bit.HUB_RESET_N = 0;
|
|
||||||
sr_exp_data.bit.S_UP = 0;
|
|
||||||
sr_exp_data.bit.E_UP_N = 1;
|
|
||||||
sr_exp_data.bit.S_DN1 = 1;
|
|
||||||
sr_exp_data.bit.E_DN1_N = 1;
|
|
||||||
sr_exp_data.bit.E_VBUS_1 = 0;
|
|
||||||
sr_exp_data.bit.E_VBUS_2 = 0;
|
|
||||||
sr_exp_data.bit.SRC_1 = 1;
|
|
||||||
sr_exp_data.bit.SRC_2 = 1;
|
|
||||||
sr_exp_data.bit.IRST = 1;
|
|
||||||
sr_exp_data.bit.SDB_N = 0;
|
|
||||||
SR_EXP_WriteData();
|
|
||||||
|
|
||||||
// Enable Shift Register output
|
|
||||||
SR_EXP_OE_N_ENA;
|
|
||||||
|
|
||||||
DBGC(DC_SPI_INIT_COMPLETE);
|
|
||||||
}
|
|
|
@ -0,0 +1,109 @@
|
||||||
|
/*
|
||||||
|
Copyright 2018 Massdrop Inc.
|
||||||
|
|
||||||
|
This program is free software: you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation, either version 2 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
This program is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "arm_atsam_protocol.h"
|
||||||
|
#include "spi_master.h"
|
||||||
|
#include "gpio.h"
|
||||||
|
|
||||||
|
/* Determine bits to set for mux selection */
|
||||||
|
#if SPI_DATAOUT_PIN % 2 == 0
|
||||||
|
# define SPI_DATAOUT_MUX_SEL PMUXE
|
||||||
|
#else
|
||||||
|
# define SPI_DATAOUT_MUX_SEL PMUXO
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Determine bits to set for mux selection */
|
||||||
|
#if SPI_SCLK_PIN % 2 == 0
|
||||||
|
# define SPI_SCLK_MUX_SEL PMUXE
|
||||||
|
#else
|
||||||
|
# define SPI_SCLK_MUX_SEL PMUXO
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static pin_t currentSelectPin = NO_PIN;
|
||||||
|
|
||||||
|
__attribute__((weak)) void spi_init(void) {
|
||||||
|
static bool is_initialised = false;
|
||||||
|
if (!is_initialised) {
|
||||||
|
is_initialised = true;
|
||||||
|
|
||||||
|
DBGC(DC_SPI_INIT_BEGIN);
|
||||||
|
|
||||||
|
CLK_set_spi_freq(CHAN_SERCOM_SPI, FREQ_SPI_DEFAULT);
|
||||||
|
|
||||||
|
// Set up MCU SPI pins
|
||||||
|
PORT->Group[SAMD_PORT(SPI_DATAOUT_PIN)].PMUX[SAMD_PIN(SPI_DATAOUT_PIN) / 2].bit.SPI_DATAOUT_MUX_SEL = SPI_DATAOUT_MUX; // MUX select for sercom
|
||||||
|
PORT->Group[SAMD_PORT(SPI_SCLK_PIN)].PMUX[SAMD_PIN(SPI_SCLK_PIN) / 2].bit.SPI_SCLK_MUX_SEL = SPI_SCLK_MUX; // MUX select for sercom
|
||||||
|
PORT->Group[SAMD_PORT(SPI_DATAOUT_PIN)].PINCFG[SAMD_PIN(SPI_DATAOUT_PIN)].bit.PMUXEN = 1; // MUX Enable
|
||||||
|
PORT->Group[SAMD_PORT(SPI_SCLK_PIN)].PINCFG[SAMD_PIN(SPI_SCLK_PIN)].bit.PMUXEN = 1; // MUX Enable
|
||||||
|
|
||||||
|
DBGC(DC_SPI_INIT_COMPLETE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
bool spi_start(pin_t csPin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
|
||||||
|
if (currentSelectPin != NO_PIN || csPin == NO_PIN) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
currentSelectPin = csPin;
|
||||||
|
setPinOutput(currentSelectPin);
|
||||||
|
writePinLow(currentSelectPin);
|
||||||
|
|
||||||
|
SPI_SERCOM->SPI.CTRLA.bit.DORD = lsbFirst; // Data Order - LSB is transferred first
|
||||||
|
SPI_SERCOM->SPI.CTRLA.bit.CPOL = 1; // Clock Polarity - SCK high when idle. Leading edge of cycle is falling. Trailing rising.
|
||||||
|
SPI_SERCOM->SPI.CTRLA.bit.CPHA = 1; // Clock Phase - Leading Edge Falling, change, Trailing Edge - Rising, sample
|
||||||
|
SPI_SERCOM->SPI.CTRLA.bit.DIPO = 3; // Data In Pinout - SERCOM PAD[3] is used as data input (Configure away from DOPO. Not using input.)
|
||||||
|
SPI_SERCOM->SPI.CTRLA.bit.DOPO = 0; // Data Output PAD[0], Serial Clock PAD[1]
|
||||||
|
SPI_SERCOM->SPI.CTRLA.bit.MODE = 3; // Operating Mode - Master operation
|
||||||
|
|
||||||
|
SPI_SERCOM->SPI.CTRLA.bit.ENABLE = 1; // Enable - Peripheral is enabled or being enabled
|
||||||
|
while (SPI_SERCOM->SPI.SYNCBUSY.bit.ENABLE) {
|
||||||
|
DBGC(DC_SPI_SYNC_ENABLING);
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
spi_status_t spi_transmit(const uint8_t *data, uint16_t length) {
|
||||||
|
while (!(SPI_SERCOM->SPI.INTFLAG.bit.DRE)) {
|
||||||
|
DBGC(DC_SPI_WRITE_DRE);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (uint16_t i = 0; i < length; i++) {
|
||||||
|
SPI_SERCOM->SPI.DATA.bit.DATA = data[i];
|
||||||
|
while (!(SPI_SERCOM->SPI.INTFLAG.bit.TXC)) {
|
||||||
|
DBGC(DC_SPI_WRITE_TXC_1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return SPI_STATUS_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_stop(void) {
|
||||||
|
if (currentSelectPin != NO_PIN) {
|
||||||
|
setPinOutput(currentSelectPin);
|
||||||
|
writePinHigh(currentSelectPin);
|
||||||
|
currentSelectPin = NO_PIN;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Not implemented yet....
|
||||||
|
|
||||||
|
spi_status_t spi_write(uint8_t data);
|
||||||
|
|
||||||
|
spi_status_t spi_read(void);
|
||||||
|
|
||||||
|
spi_status_t spi_receive(uint8_t *data, uint16_t length);
|
|
@ -0,0 +1,48 @@
|
||||||
|
/* Copyright 2021 QMK
|
||||||
|
*
|
||||||
|
* This program is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#include <stdbool.h>
|
||||||
|
|
||||||
|
typedef int16_t spi_status_t;
|
||||||
|
|
||||||
|
#define SPI_STATUS_SUCCESS (0)
|
||||||
|
#define SPI_STATUS_ERROR (-1)
|
||||||
|
#define SPI_STATUS_TIMEOUT (-2)
|
||||||
|
|
||||||
|
#define SPI_TIMEOUT_IMMEDIATE (0)
|
||||||
|
#define SPI_TIMEOUT_INFINITE (0xFFFF)
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
void spi_init(void);
|
||||||
|
|
||||||
|
bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor);
|
||||||
|
|
||||||
|
spi_status_t spi_write(uint8_t data);
|
||||||
|
|
||||||
|
spi_status_t spi_read(void);
|
||||||
|
|
||||||
|
spi_status_t spi_transmit(const uint8_t *data, uint16_t length);
|
||||||
|
|
||||||
|
spi_status_t spi_receive(uint8_t *data, uint16_t length);
|
||||||
|
|
||||||
|
void spi_stop(void);
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
Loading…
Reference in New Issue