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Massdrop keyboard support (#3780) 

* Massdrop SAMD51

Massdrop SAMD51 keyboards initial project upload

* Removing relocated files

Removing files that were relocated and not deleted from previous location

* LED queue fix and cleaning

Cleaned some white space or comments.
Fix for LED I2C command queue.
Cleaned up interrupts.
Added debug function for printing numbers to scope through m15 line.

* Factory programmed serial usage

Ability to use factory programmed serial in hub and keyboard usb descriptors

* USB serial number and bugfix

Added support for factory programmed serial and usage.
Incorporated bootloader's conditional compiling to align project closer.
Fixed issue when USB device attempted to send before enabled.
General white space and comment cleanup.

* Project cleanup

Cleaned up project in terms of white space, commented code, and unecessary files.
NKRO keyboard is now using correct setreport although KBD was fine to use.
Fixed broken linkage to __xprintf for serial debug statements.

* Fix for extra keys

Fixed possible USB hang on extra keys report set missing

* I2C cleanup

I2C cleanup and file renames necessary for master branch merge

* Boot tracing and clocks cleanup

Added optional boot debug trace mode through debug LED codes.
General clock code cleanup.

* Relocate ARM/Atmel headers

Moved ARM/Atmel header folder from drivers to lib and made necessary makefile changes.

* Pull request changes

Pull request changes

* Keymap and compile flag fix

Keymap fix for momentary layer.
Potential compile flag fix for Travis CI failure.

* va_list include fix

Fix for va_list compile failure

* Include file case fixes

Fixes for include files with incorrect case

* ctrl and alt67 keyboard readme

Added ctrl and alt67 keyboard readme files
This commit is contained in:
patrickmt 2018-08-29 15:07:52 -04:00 committed by Jack Humbert
parent a6c770432f
commit 30680c6eb3
194 changed files with 73324 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
build_keyboard.mk
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@ -144,6 +144,9 @@ endif
ifdef MCU_FAMILY
FIRMWARE_FORMAT?=bin
PLATFORM=CHIBIOS
else ifdef ARM_ATSAM
PLATFORM=ARM_ATSAM
FIRMWARE_FORMAT=bin
else
PLATFORM=AVR
FIRMWARE_FORMAT?=hex
@ -286,6 +289,11 @@ endif
include $(TMK_PATH)/avr.mk
endif
ifeq ($(PLATFORM),ARM_ATSAM)
include $(TMK_PATH)/arm_atsam.mk
include $(TMK_PATH)/protocol/arm_atsam.mk
endif
ifeq ($(PLATFORM),CHIBIOS)
include $(TMK_PATH)/protocol/chibios.mk
endif

24
keyboards/alt67/alt67.h Normal file
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@ -0,0 +1,24 @@
#pragma once
#include "quantum.h"
#include "config_led.h"
#include "matrix.h"
#include "i2c_master.h"
#include "led_matrix.h" //For led keycodes
#include "usb/udi_cdc.h"
#include "usb/usb2422.h"
#define LAYOUT( \
K01, K02, K03, K04, K05, K06, K07, K08, K09, K10, K11, K12, K13, K14, K15, \
K16, K17, K18, K19, K20, K21, K22, K23, K24, K25, K26, K27, K28, K29, K30, \
K31, K32, K33, K34, K35, K36, K37, K38, K39, K40, K41, K42, K43, K44, K45, \
K46, K47, K48, K49, K50, K51, K52, K53, K54, K55, K56, K57, K58, K59, K60, \
K61, K62, K63, K64, K65, K66, K67 \
) { \
{ K01, K02, K03, K04, K05, K06, K07, K08, K09, K10, K11, K12, K13, K14, K15, }, \
{ K16, K17, K18, K19, K20, K21, K22, K23, K24, K25, K26, K27, K28, K29, K30, }, \
{ K31, K32, K33, K34, K35, K36, K37, K38, K39, K40, K41, K42, KC_NO, K43, K44, }, \
{ K45, KC_NO, K46, K47, K48, K49, K50, K51, K52, K53, K54, K55, K56, K57, K58, }, \
{ K59, K60, K61, KC_NO, KC_NO, KC_NO, K62, KC_NO, KC_NO, KC_NO, K63, K64, K65, K66, K67, }, \
}

79
keyboards/alt67/config.h Normal file
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@ -0,0 +1,79 @@
/*
Copyright 2015 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "config_common.h"
/* USB Device descriptor parameter */
#define VENDOR_ID 0x04D8
#define PRODUCT_ID 0xEED3
#define DEVICE_VER 0x0101
#define MANUFACTURER "Massdrop Inc."
#define PRODUCT "ALT67 Keyboard"
#define SERIAL_NUM "Unavailable"
/* key matrix size */
#define MATRIX_ROWS 5
#define MATRIX_COLS 15
#define PA 0
#define PB 1
#define MATRIX_ROW_PORTS PA, PA, PA, PA, PA
#define MATRIX_ROW_PINS 0, 1, 2, 3, 4
#define MATRIX_COL_PORTS PB, PB, PB, PB, PB, PB, PB, PB, PB, PB, PA, PA, PA, PA, PA
#define MATRIX_COL_PINS 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 5, 6, 7, 10, 11
/* Print boot debug codes using debug LED when M28 and M30 shorted */
#define DEBUG_BOOT_TRACING
/* Debounce reduces chatter (unintended double-presses) - set 0 if debouncing is not needed */
#define DEBOUNCING_DELAY 5
/* Mechanical locking support. Use KC_LCAP, KC_LNUM or KC_LSCR instead in keymap */
//#define LOCKING_SUPPORT_ENABLE
/* Locking resynchronize hack */
//#define LOCKING_RESYNC_ENABLE
/* key combination for command */
#define IS_COMMAND() ( \
keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) \
)
/* Force boot in NKRO mode */
//#define FORCE_NKRO
/*
* Feature disable options
* These options are also useful to firmware size reduction.
*/
/* disable debug print */
//#define NO_DEBUG
/* disable print */
//#define NO_PRINT
/* disable action features */
//#define NO_ACTION_LAYER
//#define NO_ACTION_TAPPING
//#define NO_ACTION_ONESHOT
//#define NO_ACTION_MACRO
//#define NO_ACTION_FUNCTION

178
keyboards/alt67/config_led.h Normal file
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@ -0,0 +1,178 @@
/*
Copyright 2018 Massdrop Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _config_led_h_
#define _config_led_h_
//Define number of ISSI3733 drivers being used (1...16)
#define ISSI3733_DRIVER_COUNT 2
//Hardware address of each driver (Refer to ISSI3733 pdf "Table 1 Slave Address" and keyboard schematic)
#define ISSI3773_DRIVER_ADDRESSES { 0xA0, 0xBE }
//LED I2C bus speed
#define I2C_HZ 580000
//Count of LED bodies
#define ISSI3733_LED_COUNT 105
//Default Global Current Register value (Default brightness 0 - 255)
#define ISSI3733_GCR_DEFAULT 128
#define LED_GCR_MAX 165 //Max GCR value (0 - 255) WARNING: Raising this value may overload the LED drivers and USB bus
#define LED_GCR_STEP 10 //GCR increment/decrement value
//Automatic power rollback and recovery
#define V5_HIGH 2540 //5V high level (After low power detect, point at which LEDs are allowed to use more power )
#define V5_LOW 2480 //5V low level (LED power rolled back to stay above this limit)
#define V5_CAT 2200 //5V catastrophic level (Host USB port potential to shut down)
#define ANIMATION_SPEED_STEP 1
#define BREATHE_MIN_STEP 0
#define BREATHE_MAX_STEP 255
//LED Mapping - More practically generated from a spreadsheet program
//id: ID of the LED (Sync with PCB callouts)
//x: Physical X coordinate of LED (units do not matter)
//y: Physical Y coordinate of LED (units do not matter)
//drv: 1-Based index of ISSI3773_DRIVER_ADDRESSES
//cs: Matrix wiring CS col (1-16)
//swr: Matrix wiring SW Red row (1-12)
//swg: Matrix wiring SW Green row (1-12)
//swb: Matrix wiring SW Blue row (1-12)
//scan: Associated key scancode if any
//Note: Origin 0,0 may be located anywhere as the software will do the final layout
#define ISSI3733_LED_MAP { \
{ .id = 1, .x = 0, .y = 0, .adr = { .drv = 2, .cs = 2, .swr = 2, .swg = 1, .swb = 3 }, .scan = 0 }, \
{ .id = 2, .x = 0.75, .y = 0, .adr = { .drv = 2, .cs = 3, .swr = 5, .swg = 4, .swb = 6 }, .scan = 1 }, \
{ .id = 3, .x = 1.5, .y = 0, .adr = { .drv = 2, .cs = 4, .swr = 5, .swg = 4, .swb = 6 }, .scan = 2 }, \
{ .id = 4, .x = 2.25, .y = 0, .adr = { .drv = 2, .cs = 5, .swr = 5, .swg = 4, .swb = 6 }, .scan = 3 }, \
{ .id = 5, .x = 3, .y = 0, .adr = { .drv = 2, .cs = 6, .swr = 5, .swg = 4, .swb = 6 }, .scan = 4 }, \
{ .id = 6, .x = 3.75, .y = 0, .adr = { .drv = 2, .cs = 7, .swr = 5, .swg = 4, .swb = 6 }, .scan = 5 }, \
{ .id = 7, .x = 4.5, .y = 0, .adr = { .drv = 2, .cs = 8, .swr = 5, .swg = 4, .swb = 6 }, .scan = 6 }, \
{ .id = 8, .x = 5.25, .y = 0, .adr = { .drv = 2, .cs = 13, .swr = 2, .swg = 1, .swb = 3 }, .scan = 7 }, \
{ .id = 9, .x = 6, .y = 0, .adr = { .drv = 1, .cs = 1, .swr = 5, .swg = 4, .swb = 6 }, .scan = 8 }, \
{ .id = 10, .x = 6.75, .y = 0, .adr = { .drv = 1, .cs = 2, .swr = 5, .swg = 4, .swb = 6 }, .scan = 9 }, \
{ .id = 11, .x = 7.5, .y = 0, .adr = { .drv = 1, .cs = 3, .swr = 5, .swg = 4, .swb = 6 }, .scan = 10 }, \
{ .id = 12, .x = 8.25, .y = 0, .adr = { .drv = 1, .cs = 4, .swr = 5, .swg = 4, .swb = 6 }, .scan = 11 }, \
{ .id = 13, .x = 9, .y = 0, .adr = { .drv = 1, .cs = 5, .swr = 5, .swg = 4, .swb = 6 }, .scan = 12 }, \
{ .id = 14, .x = 10.125, .y = 0, .adr = { .drv = 1, .cs = 6, .swr = 5, .swg = 4, .swb = 6 }, .scan = 13 }, \
{ .id = 15, .x = 11.25, .y = 0, .adr = { .drv = 1, .cs = 7, .swr = 2, .swg = 1, .swb = 3 }, .scan = 14 }, \
{ .id = 16, .x = 0.188, .y = -0.75, .adr = { .drv = 2, .cs = 2, .swr = 5, .swg = 4, .swb = 6 }, .scan = 15 }, \
{ .id = 17, .x = 1.125, .y = -0.75, .adr = { .drv = 2, .cs = 3, .swr = 8, .swg = 7, .swb = 9 }, .scan = 16 }, \
{ .id = 18, .x = 1.875, .y = -0.75, .adr = { .drv = 2, .cs = 4, .swr = 8, .swg = 7, .swb = 9 }, .scan = 17 }, \
{ .id = 19, .x = 2.625, .y = -0.75, .adr = { .drv = 2, .cs = 5, .swr = 8, .swg = 7, .swb = 9 }, .scan = 18 }, \
{ .id = 20, .x = 3.375, .y = -0.75, .adr = { .drv = 2, .cs = 6, .swr = 8, .swg = 7, .swb = 9 }, .scan = 19 }, \
{ .id = 21, .x = 4.125, .y = -0.75, .adr = { .drv = 2, .cs = 7, .swr = 8, .swg = 7, .swb = 9 }, .scan = 20 }, \
{ .id = 22, .x = 4.875, .y = -0.75, .adr = { .drv = 2, .cs = 8, .swr = 8, .swg = 7, .swb = 9 }, .scan = 21 }, \
{ .id = 23, .x = 5.625, .y = -0.75, .adr = { .drv = 1, .cs = 1, .swr = 8, .swg = 7, .swb = 9 }, .scan = 22 }, \
{ .id = 24, .x = 6.375, .y = -0.75, .adr = { .drv = 1, .cs = 2, .swr = 8, .swg = 7, .swb = 9 }, .scan = 23 }, \
{ .id = 25, .x = 7.125, .y = -0.75, .adr = { .drv = 1, .cs = 3, .swr = 8, .swg = 7, .swb = 9 }, .scan = 24 }, \
{ .id = 26, .x = 7.875, .y = -0.75, .adr = { .drv = 1, .cs = 4, .swr = 8, .swg = 7, .swb = 9 }, .scan = 25 }, \
{ .id = 27, .x = 8.625, .y = -0.75, .adr = { .drv = 1, .cs = 5, .swr = 8, .swg = 7, .swb = 9 }, .scan = 26 }, \
{ .id = 28, .x = 9.375, .y = -0.75, .adr = { .drv = 1, .cs = 11, .swr = 11, .swg = 10, .swb = 12 }, .scan = 27 }, \
{ .id = 29, .x = 10.313, .y = -0.75, .adr = { .drv = 1, .cs = 6, .swr = 8, .swg = 7, .swb = 9 }, .scan = 28 }, \
{ .id = 30, .x = 11.25, .y = -0.75, .adr = { .drv = 1, .cs = 7, .swr = 5, .swg = 4, .swb = 6 }, .scan = 29 }, \
{ .id = 31, .x = 0.281, .y = -1.5, .adr = { .drv = 2, .cs = 2, .swr = 8, .swg = 7, .swb = 9 }, .scan = 30 }, \
{ .id = 32, .x = 1.313, .y = -1.5, .adr = { .drv = 2, .cs = 3, .swr = 11, .swg = 10, .swb = 12 }, .scan = 31 }, \
{ .id = 33, .x = 2.063, .y = -1.5, .adr = { .drv = 2, .cs = 4, .swr = 11, .swg = 10, .swb = 12 }, .scan = 32 }, \
{ .id = 34, .x = 2.813, .y = -1.5, .adr = { .drv = 2, .cs = 5, .swr = 11, .swg = 10, .swb = 12 }, .scan = 33 }, \
{ .id = 35, .x = 3.563, .y = -1.5, .adr = { .drv = 2, .cs = 6, .swr = 11, .swg = 10, .swb = 12 }, .scan = 34 }, \
{ .id = 36, .x = 4.313, .y = -1.5, .adr = { .drv = 2, .cs = 7, .swr = 11, .swg = 10, .swb = 12 }, .scan = 35 }, \
{ .id = 37, .x = 5.063, .y = -1.5, .adr = { .drv = 2, .cs = 8, .swr = 11, .swg = 10, .swb = 12 }, .scan = 36 }, \
{ .id = 38, .x = 5.813, .y = -1.5, .adr = { .drv = 1, .cs = 1, .swr = 11, .swg = 10, .swb = 12 }, .scan = 37 }, \
{ .id = 39, .x = 6.563, .y = -1.5, .adr = { .drv = 1, .cs = 2, .swr = 11, .swg = 10, .swb = 12 }, .scan = 38 }, \
{ .id = 40, .x = 7.313, .y = -1.5, .adr = { .drv = 1, .cs = 3, .swr = 11, .swg = 10, .swb = 12 }, .scan = 39 }, \
{ .id = 41, .x = 8.063, .y = -1.5, .adr = { .drv = 1, .cs = 4, .swr = 11, .swg = 10, .swb = 12 }, .scan = 40 }, \
{ .id = 42, .x = 8.813, .y = -1.5, .adr = { .drv = 1, .cs = 5, .swr = 11, .swg = 10, .swb = 12 }, .scan = 41 }, \
{ .id = 43, .x = 10.031, .y = -1.5, .adr = { .drv = 1, .cs = 6, .swr = 11, .swg = 10, .swb = 12 }, .scan = 43 }, \
{ .id = 44, .x = 11.25, .y = -1.5, .adr = { .drv = 1, .cs = 7, .swr = 8, .swg = 7, .swb = 9 }, .scan = 44 }, \
{ .id = 45, .x = 0.469, .y = -2.25, .adr = { .drv = 2, .cs = 2, .swr = 11, .swg = 10, .swb = 12 }, .scan = 45 }, \
{ .id = 46, .x = 1.688, .y = -2.25, .adr = { .drv = 2, .cs = 9, .swr = 5, .swg = 4, .swb = 6 }, .scan = 47 }, \
{ .id = 47, .x = 2.438, .y = -2.25, .adr = { .drv = 2, .cs = 9, .swr = 2, .swg = 1, .swb = 3 }, .scan = 48 }, \
{ .id = 48, .x = 3.188, .y = -2.25, .adr = { .drv = 2, .cs = 9, .swr = 11, .swg = 10, .swb = 12 }, .scan = 49 }, \
{ .id = 49, .x = 3.938, .y = -2.25, .adr = { .drv = 2, .cs = 9, .swr = 8, .swg = 7, .swb = 9 }, .scan = 50 }, \
{ .id = 50, .x = 4.688, .y = -2.25, .adr = { .drv = 2, .cs = 12, .swr = 11, .swg = 10, .swb = 12 }, .scan = 51 }, \
{ .id = 51, .x = 5.438, .y = -2.25, .adr = { .drv = 2, .cs = 13, .swr = 11, .swg = 10, .swb = 12 }, .scan = 52 }, \
{ .id = 52, .x = 6.188, .y = -2.25, .adr = { .drv = 1, .cs = 9, .swr = 11, .swg = 10, .swb = 12 }, .scan = 53 }, \
{ .id = 53, .x = 6.938, .y = -2.25, .adr = { .drv = 1, .cs = 10, .swr = 11, .swg = 10, .swb = 12 }, .scan = 54 }, \
{ .id = 54, .x = 7.688, .y = -2.25, .adr = { .drv = 1, .cs = 10, .swr = 8, .swg = 7, .swb = 9 }, .scan = 55 }, \
{ .id = 55, .x = 8.438, .y = -2.25, .adr = { .drv = 1, .cs = 11, .swr = 8, .swg = 7, .swb = 9 }, .scan = 56 }, \
{ .id = 56, .x = 9.469, .y = -2.25, .adr = { .drv = 1, .cs = 11, .swr = 2, .swg = 1, .swb = 3 }, .scan = 57 }, \
{ .id = 57, .x = 10.5, .y = -2.25, .adr = { .drv = 1, .cs = 11, .swr = 5, .swg = 4, .swb = 6 }, .scan = 58 }, \
{ .id = 58, .x = 11.25, .y = -2.25, .adr = { .drv = 1, .cs = 7, .swr = 11, .swg = 10, .swb = 12 }, .scan = 59 }, \
{ .id = 59, .x = 0.094, .y = -3, .adr = { .drv = 2, .cs = 10, .swr = 8, .swg = 7, .swb = 9 }, .scan = 60 }, \
{ .id = 60, .x = 1.031, .y = -3, .adr = { .drv = 2, .cs = 10, .swr = 5, .swg = 4, .swb = 6 }, .scan = 61 }, \
{ .id = 61, .x = 1.969, .y = -3, .adr = { .drv = 2, .cs = 10, .swr = 2, .swg = 1, .swb = 3 }, .scan = 62 }, \
{ .id = 62, .x = 4.781, .y = -3, .adr = { .drv = 2, .cs = 12, .swr = 8, .swg = 7, .swb = 9 }, .scan = 66 }, \
{ .id = 63, .x = 7.594, .y = -3, .adr = { .drv = 1, .cs = 10, .swr = 5, .swg = 4, .swb = 6 }, .scan = 70 }, \
{ .id = 64, .x = 8.531, .y = -3, .adr = { .drv = 1, .cs = 10, .swr = 2, .swg = 1, .swb = 3 }, .scan = 71 }, \
{ .id = 65, .x = 9.75, .y = -3, .adr = { .drv = 1, .cs = 12, .swr = 2, .swg = 1, .swb = 3 }, .scan = 72 }, \
{ .id = 66, .x = 10.5, .y = -3, .adr = { .drv = 1, .cs = 12, .swr = 8, .swg = 7, .swb = 9 }, .scan = 73 }, \
{ .id = 67, .x = 11.25, .y = -3, .adr = { .drv = 1, .cs = 12, .swr = 5, .swg = 4, .swb = 6 }, .scan = 74 }, \
{ .id = 68, .x = -0.338, .y = -3.338, .adr = { .drv = 2, .cs = 11, .swr = 11, .swg = 10, .swb = 12 }, .scan = 255 }, \
{ .id = 69, .x = 0.39, .y = -3.443, .adr = { .drv = 2, .cs = 11, .swr = 8, .swg = 7, .swb = 9 }, .scan = 255 }, \
{ .id = 70, .x = 1.263, .y = -3.443, .adr = { .drv = 2, .cs = 11, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
{ .id = 71, .x = 2.135, .y = -3.443, .adr = { .drv = 2, .cs = 11, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 72, .x = 3.008, .y = -3.443, .adr = { .drv = 2, .cs = 12, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 73, .x = 3.88, .y = -3.443, .adr = { .drv = 2, .cs = 12, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
{ .id = 74, .x = 4.753, .y = -3.443, .adr = { .drv = 2, .cs = 13, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
{ .id = 75, .x = 5.625, .y = -3.443, .adr = { .drv = 2, .cs = 13, .swr = 8, .swg = 7, .swb = 9 }, .scan = 255 }, \
{ .id = 76, .x = 6.497, .y = -3.443, .adr = { .drv = 1, .cs = 9, .swr = 8, .swg = 7, .swb = 9 }, .scan = 255 }, \
{ .id = 77, .x = 7.37, .y = -3.443, .adr = { .drv = 1, .cs = 9, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
{ .id = 78, .x = 8.242, .y = -3.443, .adr = { .drv = 1, .cs = 9, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 79, .x = 9.115, .y = -3.443, .adr = { .drv = 1, .cs = 13, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 80, .x = 9.987, .y = -3.443, .adr = { .drv = 1, .cs = 13, .swr = 8, .swg = 7, .swb = 9 }, .scan = 255 }, \
{ .id = 81, .x = 10.86, .y = -3.443, .adr = { .drv = 1, .cs = 13, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
{ .id = 82, .x = 11.588, .y = -3.338, .adr = { .drv = 1, .cs = 13, .swr = 11, .swg = 10, .swb = 12 }, .scan = 255 }, \
{ .id = 83, .x = 11.693, .y = -2.623, .adr = { .drv = 1, .cs = 12, .swr = 11, .swg = 10, .swb = 12 }, .scan = 255 }, \
{ .id = 84, .x = 11.693, .y = -1.873, .adr = { .drv = 1, .cs = 8, .swr = 11, .swg = 10, .swb = 12 }, .scan = 255 }, \
{ .id = 85, .x = 11.693, .y = -1.123, .adr = { .drv = 1, .cs = 8, .swr = 8, .swg = 7, .swb = 9 }, .scan = 255 }, \
{ .id = 86, .x = 11.693, .y = -0.373, .adr = { .drv = 1, .cs = 8, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
{ .id = 87, .x = 11.588, .y = 0.338, .adr = { .drv = 1, .cs = 8, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 88, .x = 9.908, .y = 0.443, .adr = { .drv = 1, .cs = 6, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 89, .x = 9.288, .y = 0.443, .adr = { .drv = 1, .cs = 5, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 90, .x = 8.625, .y = 0.443, .adr = { .drv = 1, .cs = 4, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 91, .x = 7.875, .y = 0.443, .adr = { .drv = 1, .cs = 3, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 92, .x = 7.125, .y = 0.443, .adr = { .drv = 1, .cs = 2, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 93, .x = 6.375, .y = 0.443, .adr = { .drv = 1, .cs = 1, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 94, .x = 5.625, .y = 0.443, .adr = { .drv = 1, .cs = 14, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 95, .x = 4.875, .y = 0.443, .adr = { .drv = 2, .cs = 8, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 96, .x = 4.125, .y = 0.443, .adr = { .drv = 2, .cs = 7, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 97, .x = 3.375, .y = 0.443, .adr = { .drv = 2, .cs = 6, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 98, .x = 2.625, .y = 0.443, .adr = { .drv = 2, .cs = 5, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 99, .x = 1.875, .y = 0.443, .adr = { .drv = 2, .cs = 4, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 100, .x = 1.125, .y = 0.443, .adr = { .drv = 2, .cs = 3, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 101, .x = -0.338, .y = 0.338, .adr = { .drv = 2, .cs = 1, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 102, .x = -0.443, .y = -0.373, .adr = { .drv = 2, .cs = 1, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
{ .id = 103, .x = -0.443, .y = -1.123, .adr = { .drv = 2, .cs = 1, .swr = 8, .swg = 7, .swb = 9 }, .scan = 255 }, \
{ .id = 104, .x = -0.443, .y = -1.873, .adr = { .drv = 2, .cs = 1, .swr = 11, .swg = 10, .swb = 12 }, .scan = 255 }, \
{ .id = 105, .x = -0.443, .y = -2.623, .adr = { .drv = 2, .cs = 10, .swr = 11, .swg = 10, .swb = 12 }, .scan = 255 }, \
};
#define USB_LED_INDICATOR_ENABLE //Comment out to disable indicator functionality
#ifdef USB_LED_INDICATOR_ENABLE //Scan codes refer to actual key matrix codes, not KC_* (255 to disable)
#define USB_LED_NUM_LOCK_SCANCODE 255
#define USB_LED_CAPS_LOCK_SCANCODE 30
#define USB_LED_SCROLL_LOCK_SCANCODE 255
#define USB_LED_COMPOSE_SCANCODE 255
#define USB_LED_KANA_SCANCODE 255
#endif //USB_LED_INDICATOR_ENABLE
#endif //_config_led_h_

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#include QMK_KEYBOARD_H
enum alt67_keycodes {
L_BRI = SAFE_RANGE, //LED Brightness Increase
L_BRD, //LED Brightness Decrease
L_PTN, //LED Pattern Select Next
L_PTP, //LED Pattern Select Previous
L_PSI, //LED Pattern Speed Increase
L_PSD, //LED Pattern Speed Decrease
L_T_MD, //LED Toggle Mode
L_T_ONF, //LED Toggle On / Off
L_ON, //LED On
L_OFF, //LED Off
L_T_BR, //LED Toggle Breath Effect
L_T_PTD, //LED Toggle Scrolling Pattern Direction
U_T_AUTO, //USB Extra Port Toggle Auto Detect / Always Active
U_T_AGCR, //USB Toggle Automatic GCR control
DBG_TOG, //DEBUG Toggle On / Off
DBG_MTRX, //DEBUG Toggle Matrix Prints
DBG_KBD, //DEBUG Toggle Keyboard Prints
DBG_MOU, //DEBUG Toggle Mouse Prints
};
#define TG_NKRO MAGIC_TOGGLE_NKRO //Toggle 6KRO / NKRO mode
keymap_config_t keymap_config;
const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[0] = LAYOUT(
KC_ESC, KC_1, KC_2, KC_3, KC_4, KC_5, KC_6, KC_7, KC_8, KC_9, KC_0, KC_MINS, KC_EQL, KC_BSPC, KC_DEL, \
KC_TAB, KC_Q, KC_W, KC_E, KC_R, KC_T, KC_Y, KC_U, KC_I, KC_O, KC_P, KC_LBRC, KC_RBRC, KC_BSLS, KC_HOME, \
KC_CAPS, KC_A, KC_S, KC_D, KC_F, KC_G, KC_H, KC_J, KC_K, KC_L, KC_SCLN, KC_QUOT, KC_ENT, KC_PGUP, \
KC_LSFT, KC_Z, KC_X, KC_C, KC_V, KC_B, KC_N, KC_M, KC_COMM, KC_DOT, KC_SLSH, KC_RSFT, KC_UP, KC_PGDN, \
KC_LCTL, KC_LGUI, KC_LALT, KC_SPC, KC_RALT, MO(1), KC_LEFT, KC_DOWN, KC_RGHT \
),
[1] = LAYOUT(
KC_TRNS, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_TRNS, KC_MUTE, \
L_T_BR, L_PSD, L_BRI, L_PSI, KC_TRNS, KC_TRNS, KC_TRNS, U_T_AUTO,U_T_AGCR,KC_TRNS, KC_PSCR, KC_SLCK, KC_PAUS, KC_TRNS, KC_TRNS, \
L_T_PTD, L_PTP, L_BRD, L_PTN, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_VOLU, \
KC_TRNS, L_T_MD, L_T_ONF, KC_TRNS, KC_TRNS, KC_TRNS, TG_NKRO, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_PGUP, KC_VOLD, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_HOME, KC_PGDN, KC_END \
),
/*
[X] = LAYOUT(
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS \
),
*/
};
const uint16_t PROGMEM fn_actions[] = {
};
// Runs just one time when the keyboard initializes.
void matrix_init_user(void) {
};
// Runs constantly in the background, in a loop.
void matrix_scan_user(void) {
};
#define MODS_SHIFT (keyboard_report->mods & MOD_BIT(KC_LSHIFT) || keyboard_report->mods & MOD_BIT(KC_RSHIFT))
#define MODS_CTRL (keyboard_report->mods & MOD_BIT(KC_LCTL) || keyboard_report->mods & MOD_BIT(KC_RCTRL))
#define MODS_ALT (keyboard_report->mods & MOD_BIT(KC_LALT) || keyboard_report->mods & MOD_BIT(KC_RALT))
bool process_record_user(uint16_t keycode, keyrecord_t *record) {
switch (keycode) {
case L_BRI:
if (record->event.pressed) {
if (LED_GCR_STEP > LED_GCR_MAX - gcr_desired) gcr_desired = LED_GCR_MAX;
else gcr_desired += LED_GCR_STEP;
if (led_animation_breathing) gcr_breathe = gcr_desired;
}
return false;
case L_BRD:
if (record->event.pressed) {
if (LED_GCR_STEP > gcr_desired) gcr_desired = 0;
else gcr_desired -= LED_GCR_STEP;
if (led_animation_breathing) gcr_breathe = gcr_desired;
}
return false;
case L_PTN:
if (record->event.pressed) {
if (led_animation_id == led_setups_count - 1) led_animation_id = 0;
else led_animation_id++;
}
return false;
case L_PTP:
if (record->event.pressed) {
if (led_animation_id == 0) led_animation_id = led_setups_count - 1;
else led_animation_id--;
}
return false;
case L_PSI:
if (record->event.pressed) {
led_animation_speed += ANIMATION_SPEED_STEP;
}
return false;
case L_PSD:
if (record->event.pressed) {
led_animation_speed -= ANIMATION_SPEED_STEP;
if (led_animation_speed < 0) led_animation_speed = 0;
}
return false;
case L_T_MD:
if (record->event.pressed) {
led_lighting_mode++;
if (led_lighting_mode > LED_MODE_MAX_INDEX) led_lighting_mode = LED_MODE_NORMAL;
}
return false;
case L_T_ONF:
if (record->event.pressed) {
led_enabled = !led_enabled;
I2C3733_Control_Set(led_enabled);
}
return false;
case L_ON:
if (record->event.pressed) {
led_enabled = 1;
I2C3733_Control_Set(led_enabled);
}
return false;
case L_OFF:
if (record->event.pressed) {
led_enabled = 0;
I2C3733_Control_Set(led_enabled);
}
return false;
case L_T_BR:
if (record->event.pressed) {
led_animation_breathing = !led_animation_breathing;
if (led_animation_breathing)
{
gcr_breathe = gcr_desired;
led_animation_breathe_cur = BREATHE_MIN_STEP;
breathe_dir = 1;
}
}
return false;
case L_T_PTD:
if (record->event.pressed) {
led_animation_direction = !led_animation_direction;
}
return false;
case U_T_AUTO:
if (record->event.pressed && MODS_SHIFT && MODS_CTRL) {
usb_extra_manual = !usb_extra_manual;
CDC_print("USB extra port manual mode ");
CDC_print(usb_extra_manual ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case U_T_AGCR:
if (record->event.pressed && MODS_SHIFT && MODS_CTRL) {
usb_gcr_auto = !usb_gcr_auto;
CDC_print("USB GCR auto mode ");
CDC_print(usb_gcr_auto ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case DBG_TOG:
if (record->event.pressed) {
debug_enable = !debug_enable;
CDC_print("Debug mode ");
CDC_print(debug_enable ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case DBG_MTRX:
if (record->event.pressed) {
debug_matrix = !debug_matrix;
CDC_print("Debug matrix ");
CDC_print(debug_matrix ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case DBG_KBD:
if (record->event.pressed) {
debug_keyboard = !debug_keyboard;
CDC_print("Debug keyboard ");
CDC_print(debug_keyboard ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case DBG_MOU:
if (record->event.pressed) {
debug_mouse = !debug_mouse;
CDC_print("Debug mouse ");
CDC_print(debug_mouse ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
default:
return true; //Process all other keycodes normally
}
}

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/*
Copyright 2018 Massdrop Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "alt67.h"
#include "led_matrix.h"
//Teal <-> Salmon
led_setup_t leds_teal_salmon[] = {
{ .hs = 0, .he = 33, .rs = 24, .re = 24, .gs = 215, .ge = 215, .bs = 204, .be = 204, .ef = EF_NONE },
{ .hs = 33, .he = 66, .rs = 24, .re = 255, .gs = 215, .ge = 114, .bs = 204, .be = 118, .ef = EF_NONE },
{ .hs = 66, .he = 100, .rs = 255, .re = 255, .gs = 114, .ge = 114, .bs = 118, .be = 118, .ef = EF_NONE },
{ .end = 1 },
};
//Yellow
led_setup_t leds_yellow[] = {
{ .hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_NONE },
{ .end = 1 },
};
//Off
led_setup_t leds_off[] = {
{ .hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_NONE },
{ .end = 1 },
};
//Red
led_setup_t leds_red[] = {
{ .hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_NONE },
{ .end = 1 },
};
//Green
led_setup_t leds_green[] = {
{ .hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_NONE },
{ .end = 1 },
};
//Blue
led_setup_t leds_blue[] = {
{ .hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_NONE },
{ .end = 1 },
};
//White
led_setup_t leds_white[] = {
{ .hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 255, .be = 255, .ef = EF_NONE },
{ .end = 1 },
};
//White with moving red stripe
led_setup_t leds_white_with_red_stripe[] = {
{ .hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 255, .be = 255, .ef = EF_NONE },
{ .hs = 0, .he = 15, .rs = 0, .re = 0, .gs = 0, .ge = 255, .bs = 0, .be = 255, .ef = EF_SCR_R | EF_SUBTRACT },
{ .hs = 15, .he = 30, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 0, .ef = EF_SCR_R | EF_SUBTRACT },
{ .end = 1 },
};
//Black with moving red stripe
led_setup_t leds_black_with_red_stripe[] = {
{ .hs = 0, .he = 15, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_SCR_R },
{ .hs = 15, .he = 30, .rs = 255, .re = 0, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_SCR_R },
{ .end = 1 },
};
//Rainbow no scrolling
led_setup_t leds_rainbow_ns[] = {
{ .hs = 0, .he = 16.67, .rs = 255, .re = 255, .gs = 0, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER },
{ .hs = 16.67, .he = 33.33, .rs = 255, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER },
{ .hs = 33.33, .he = 50, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 255, .ef = EF_OVER },
{ .hs = 50, .he = 66.67, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER },
{ .hs = 66.67, .he = 83.33, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER },
{ .hs = 83.33, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 0, .ef = EF_OVER },
{ .end = 1 },
};
//Rainbow scrolling
led_setup_t leds_rainbow_s[] = {
{ .hs = 0, .he = 16.67, .rs = 255, .re = 255, .gs = 0, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER | EF_SCR_R },
{ .hs = 16.67, .he = 33.33, .rs = 255, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER | EF_SCR_R },
{ .hs = 33.33, .he = 50, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 255, .ef = EF_OVER | EF_SCR_R },
{ .hs = 50, .he = 66.67, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER | EF_SCR_R },
{ .hs = 66.67, .he = 83.33, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER | EF_SCR_R },
{ .hs = 83.33, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 0, .ef = EF_OVER | EF_SCR_R },
{ .end = 1 },
};
//Add new LED animations here using one from above as example
//The last entry must be { .end = 1 }
//Add the new animation name to the list below following its format
void *led_setups[] = {
leds_rainbow_s,
leds_rainbow_ns,
leds_teal_salmon,
leds_yellow,
leds_red,
leds_green,
leds_blue,
leds_white,
leds_white_with_red_stripe,
leds_black_with_red_stripe,
leds_off
};
const uint8_t led_setups_count = sizeof(led_setups) / sizeof(led_setups[0]);

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/*
Copyright 2018 Massdrop Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "alt67.h"
#include "d51_util.h"
#include "debug.h"
#include "clks.h"
#include <string.h>
matrix_row_t mlatest[MATRIX_ROWS];
matrix_row_t mlast[MATRIX_ROWS];
matrix_row_t mdebounced[MATRIX_ROWS];
uint8_t row_ports[] = { MATRIX_ROW_PORTS };
uint8_t row_pins[] = { MATRIX_ROW_PINS };
uint8_t col_ports[] = { MATRIX_COL_PORTS };
uint8_t col_pins[] = { MATRIX_COL_PINS };
uint32_t row_masks[2]; //NOTE: If more than PA PB used in the future, adjust code to accomodate
__attribute__ ((weak))
void matrix_init_kb(void) {
matrix_init_user();
}
__attribute__ ((weak))
void matrix_scan_kb(void) {
matrix_scan_user();
}
__attribute__ ((weak))
void matrix_init_user(void) {
}
__attribute__ ((weak))
void matrix_scan_user(void) {
}
void matrix_init(void)
{
memset(mlatest, 0, MATRIX_ROWS * sizeof(matrix_row_t));
memset(mlast, 0, MATRIX_ROWS * sizeof(matrix_row_t));
memset(mdebounced, 0, MATRIX_ROWS * sizeof(matrix_row_t));
row_masks[PA] = 0;
row_masks[PB] = 0;
uint8_t row;
for (row = 0; row < MATRIX_ROWS; row++)
{
PORT->Group[row_ports[row]].DIRCLR.reg = 1 << row_pins[row]; //Input
PORT->Group[row_ports[row]].OUTCLR.reg = 1 << row_pins[row]; //Low
PORT->Group[row_ports[row]].PINCFG[row_pins[row]].bit.INEN = 1; //Input Enable,
PORT->Group[row_ports[row]].PINCFG[row_pins[row]].bit.PULLEN = 1; //Pull Enable
row_masks[row_ports[row]] |= 1 << row_pins[row]; //Add pin to proper row mask
}
uint8_t col;
for (col = 0; col < MATRIX_COLS; col++)
{
PORT->Group[col_ports[col]].DIRSET.reg = 1 << col_pins[col]; //Output
PORT->Group[col_ports[col]].OUTCLR.reg = 1 << col_pins[col]; //Low
}
matrix_init_quantum();
}
#define MATRIX_SCAN_DELAY 10 //Delay after setting a col to output (in us)
uint64_t mdebouncing = 0;
uint8_t matrix_scan(void)
{
uint8_t mchanged;
uint8_t row;
uint8_t col;
uint32_t scans[2]; //PA PB
if (CLK_get_ms() < mdebouncing) return 1; //mdebouncing == 0 when no debouncing active
//m15_off; //Profiling scans
memset(mlatest, 0, MATRIX_ROWS * sizeof(matrix_row_t)); //Zero the result buffer
for (col = 0; col < MATRIX_COLS; col++)
{
PORT->Group[col_ports[col]].OUTSET.reg = 1 << col_pins[col]; //Set col output
CLK_delay_us(MATRIX_SCAN_DELAY); //Delay for output
scans[PA] = PORT->Group[PA].IN.reg & row_masks[PA]; //Read PA row pins data
scans[PB] = PORT->Group[PB].IN.reg & row_masks[PB]; //Read PB row pins data
PORT->Group[col_ports[col]].OUTCLR.reg = 1 << col_pins[col]; //Clear col output
for (row = 0; row < MATRIX_ROWS; row++)
{
//Move scan bits from scans array into proper row bit locations
if (scans[row_ports[row]] & (1 << row_pins[row]))
mlatest[row] |= 1 << col;
}
}
mchanged = 0; //Default to no matrix change since last
for (row = 0; row < MATRIX_ROWS; row++)
{
if (mlast[row] != mlatest[row])
mchanged = 1;
mlast[row] = mlatest[row];
}
if (!mchanged)
{
for (row = 0; row < MATRIX_ROWS; row++)
mdebounced[row] = mlatest[row];
mdebouncing = 0;
}
else
{
//Begin or extend debounce on change
mdebouncing = CLK_get_ms() + DEBOUNCING_DELAY;
}
//m15_on; //Profiling scans
matrix_scan_quantum();
return 1;
}
matrix_row_t matrix_get_row(uint8_t row)
{
return mdebounced[row];
}
void matrix_print(void)
{
char buf[(MATRIX_COLS+8)*(MATRIX_ROWS+1)] = "R C";
char *pbuf = buf+3;
uint32_t cols;
uint32_t rows;
matrix_row_t row;
for (cols = 1; cols <= MATRIX_COLS; cols++)
{
*pbuf = (cols%10)+48;
pbuf++;
}
*pbuf = '\r'; pbuf++;
*pbuf = '\n'; pbuf++;
for (rows = 1; rows <= MATRIX_ROWS; rows++)
{
row = matrix_get_row(rows-1);
if (rows < 10) { *pbuf = rows+48; pbuf++; *pbuf = ' '; pbuf++; *pbuf = ' '; pbuf++; }
else { *pbuf = (rows/10)+48; pbuf++; *pbuf = (rows%10)+48; pbuf++; *pbuf = ' '; pbuf++; }
for (cols = 0; cols < MATRIX_COLS; cols++)
{
if (row & 1 << cols) *pbuf = 'X';
else *pbuf = '.';
pbuf++;
}
*pbuf = '\r'; pbuf++;
*pbuf = '\n'; pbuf++;
}
*pbuf = 0;
dprint(buf);
}

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/*
Copyright 2011 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef MATRIX_H
#define MATRIX_H
#include <stdint.h>
#include <stdbool.h>
#include "keyboard.h"
#if (MATRIX_COLS <= 8)
typedef uint8_t matrix_row_t;
#elif (MATRIX_COLS <= 16)
typedef uint16_t matrix_row_t;
#elif (MATRIX_COLS <= 32)
typedef uint32_t matrix_row_t;
#else
#error "MATRIX_COLS: invalid value"
#endif
#define MATRIX_IS_ON(row, col) (matrix_get_row(row) && (1<<col))
#ifdef __cplusplus
extern "C" {
#endif
/* number of matrix rows */
uint8_t matrix_rows(void);
/* number of matrix columns */
uint8_t matrix_cols(void);
/* should be called at early stage of startup before matrix_init.(optional) */
void matrix_setup(void);
/* intialize matrix for scaning. */
void matrix_init(void);
/* scan all key states on matrix */
uint8_t matrix_scan(void);
/* whether modified from previous scan. used after matrix_scan. */
bool matrix_is_modified(void) __attribute__ ((deprecated));
/* whether a switch is on */
bool matrix_is_on(uint8_t row, uint8_t col);
/* matrix state on row */
matrix_row_t matrix_get_row(uint8_t row);
/* print matrix for debug */
void matrix_print(void);
/* power control */
void matrix_power_up(void);
void matrix_power_down(void);
/* executes code for Quantum */
void matrix_init_quantum(void);
void matrix_scan_quantum(void);
void matrix_init_kb(void);
void matrix_scan_kb(void);
void matrix_init_user(void);
void matrix_scan_user(void);
#ifdef __cplusplus
}
#endif
#endif

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# ALT
![ALT](https://massdrop-s3.imgix.net/product-images/alt-keyboard/FP/WNxwR19gTua3nxiiQWP3_AI7B3311%20copy%20page.jpg?auto=format&fm=jpg&fit=max&w=700&h=467&dpr=1&q=80)
The Massdrop ALT is a 65% mechanical keyboard featuring dual USB-C connectors, an integrated Hi-Speed USB 2.0 hub, and fully customizable RGB backlighting and underlighting.
Keyboard Maintainer: [Massdrop](https://github.com/massdrop)
Hardware Supported: Massdrop, Inc. ALT67 PCBs utilizing Microchip's ATSAMD51J18A MCU and USB2422 2-Port USB 2.0 Hi-Speed Hub Controller, and ISSI's IS31FL3733 LED Drivers.
Hardware Availability: [Massdrop ALT Mechanical Keyboard](https://www.massdrop.com/buy/massdrop-alt-mechanical-keyboard)
Make example for this keyboard (after setting up your build environment):
make alt67:default
See the [build environment setup](https://docs.qmk.fm/#/getting_started_build_tools) and the [make instructions](https://docs.qmk.fm/#/getting_started_make_guide) for more information. Brand new to QMK? Start with our [Complete Newbs Guide](https://docs.qmk.fm/#/newbs).

32
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# project specific files
SRC = led_programs.c
SRC += matrix.c
#For platform and packs
ARM_ATSAM = SAMD51J18A
MCU = cortex-m4
CUSTOM_MATRIX = yes
# Build Options
# comment out to disable the options.
#
BOOTMAGIC_ENABLE = no # Virtual DIP switch configuration(+1000)
MOUSEKEY_ENABLE = no # Mouse keys(+4700)
EXTRAKEY_ENABLE = yes # Audio control and System control(+450)
CONSOLE_ENABLE = no # Console for debug(+400)
COMMAND_ENABLE = no # Commands for debug and configuration
# Do not enable SLEEP_LED_ENABLE. it uses the same timer as BACKLIGHT_ENABLE
SLEEP_LED_ENABLE = no # Breathing sleep LED during USB suspend
# if this doesn't work, see here: https://github.com/tmk/tmk_keyboard/wiki/FAQ#nkro-doesnt-work
NKRO_ENABLE = yes # USB Nkey Rollover
BACKLIGHT_ENABLE = no # Enable keyboard backlight functionality on B7 by default
RGBLIGHT_ENABLE = no # Enable keyboard RGB underglow
MIDI_ENABLE = no # MIDI support (+2400 to 4200, depending on config)
UNICODE_ENABLE = no # Unicode
BLUETOOTH_ENABLE = no # Enable Bluetooth with the Adafruit EZ-Key HID
AUDIO_ENABLE = no # Audio output on port C6
FAUXCLICKY_ENABLE = no # Use buzzer to emulate clicky switches
HD44780_ENABLE = no # Enable support for HD44780 based LCDs (+400)
VIRTSER_ENABLE = no # USB Serial Driver
RAW_ENABLE = no # Raw device

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/*
Copyright 2015 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
#include "config_common.h"
/* USB Device descriptor parameter */
#define VENDOR_ID 0x04D8
#define PRODUCT_ID 0xEED2
#define DEVICE_VER 0x0101
#define MANUFACTURER "Massdrop Inc."
#define PRODUCT "CTRL Keyboard"
#define SERIAL_NUM "Unavailable"
/* key matrix size */
#define MATRIX_ROWS 11
#define MATRIX_COLS 8
#define PA 0
#define PB 1
#define MATRIX_ROW_PORTS PB, PB, PB, PB, PB, PB, PA, PA, PB, PB, PB
#define MATRIX_ROW_PINS 4, 5, 6, 7, 8, 9, 10, 11, 10, 11, 12
#define MATRIX_COL_PORTS PA, PA, PA, PA, PA, PA, PA, PA
#define MATRIX_COL_PINS 0, 1, 2, 3, 4, 5, 6, 7
/* Print boot debug codes using debug LED when M28 and M30 shorted */
#define DEBUG_BOOT_TRACING
/* Debounce reduces chatter (unintended double-presses) - set 0 if debouncing is not needed */
#define DEBOUNCING_DELAY 5
/* Mechanical locking support. Use KC_LCAP, KC_LNUM or KC_LSCR instead in keymap */
//#define LOCKING_SUPPORT_ENABLE
/* Locking resynchronize hack */
//#define LOCKING_RESYNC_ENABLE
/* key combination for command */
#define IS_COMMAND() ( \
keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) \
)
/* Force boot in NKRO mode */
//#define FORCE_NKRO
/*
* Feature disable options
* These options are also useful to firmware size reduction.
*/
/* disable debug print */
//#define NO_DEBUG
/* disable print */
//#define NO_PRINT
/* disable action features */
//#define NO_ACTION_LAYER
//#define NO_ACTION_TAPPING
//#define NO_ACTION_ONESHOT
//#define NO_ACTION_MACRO
//#define NO_ACTION_FUNCTION

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/*
Copyright 2018 Massdrop Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _config_led_h_
#define _config_led_h_
//Define number of ISSI3733 drivers being used (1...16)
#define ISSI3733_DRIVER_COUNT 2
//Hardware address of each driver (Refer to ISSI3733 pdf "Table 1 Slave Address" and keyboard schematic)
#define ISSI3773_DRIVER_ADDRESSES { 0xA0, 0xBE }
//LED I2C bus speed
#define I2C_HZ 580000
//Count of LED bodies
#define ISSI3733_LED_COUNT 119
//Default Global Current Register value (Default brightness 0 - 255)
#define ISSI3733_GCR_DEFAULT 128
#define LED_GCR_MAX 165 //Max GCR value (0 - 255) WARNING: Raising this value may overload the LED drivers and USB bus
#define LED_GCR_STEP 10 //GCR increment/decrement value
//Automatic power rollback and recovery
#define V5_HIGH 2540 //5V high level (After low power detect, point at which LEDs are allowed to use more power )
#define V5_LOW 2480 //5V low level (LED power rolled back to stay above this limit)
#define V5_CAT 2200 //5V catastrophic level (Host USB port potential to shut down)
#define ANIMATION_SPEED_STEP 1
#define BREATHE_MIN_STEP 0
#define BREATHE_MAX_STEP 255
//LED Mapping - More practically generated from a spreadsheet program
//id: ID of the LED (Sync with PCB callouts)
//x: Physical X coordinate of LED (units do not matter)
//y: Physical Y coordinate of LED (units do not matter)
//drv: 1-Based index of ISSI3773_DRIVER_ADDRESSES
//cs: Matrix wiring CS col (1-16)
//swr: Matrix wiring SW Red row (1-12)
//swg: Matrix wiring SW Green row (1-12)
//swb: Matrix wiring SW Blue row (1-12)
//scan: Associated key scancode if any
//Note: Origin 0,0 may be located anywhere as the software will do the final layout
#define ISSI3733_LED_MAP { \
{ .id = 1, .x = 0, .y = 0, .adr = { .drv = 2, .cs = 2, .swr = 2, .swg = 1, .swb = 3 }, .scan = 0 }, \
{ .id = 2, .x = 1.5, .y = 0, .adr = { .drv = 2, .cs = 3, .swr = 5, .swg = 4, .swb = 6 }, .scan = 1 }, \
{ .id = 3, .x = 2.25, .y = 0, .adr = { .drv = 2, .cs = 4, .swr = 5, .swg = 4, .swb = 6 }, .scan = 2 }, \
{ .id = 4, .x = 3, .y = 0, .adr = { .drv = 2, .cs = 5, .swr = 5, .swg = 4, .swb = 6 }, .scan = 3 }, \
{ .id = 5, .x = 3.75, .y = 0, .adr = { .drv = 2, .cs = 6, .swr = 2, .swg = 1, .swb = 3 }, .scan = 4 }, \
{ .id = 6, .x = 4.875, .y = 0, .adr = { .drv = 2, .cs = 7, .swr = 5, .swg = 4, .swb = 6 }, .scan = 5 }, \
{ .id = 7, .x = 5.625, .y = 0, .adr = { .drv = 2, .cs = 8, .swr = 5, .swg = 4, .swb = 6 }, .scan = 6 }, \
{ .id = 8, .x = 6.375, .y = 0, .adr = { .drv = 1, .cs = 1, .swr = 5, .swg = 4, .swb = 6 }, .scan = 7 }, \
{ .id = 9, .x = 7.125, .y = 0, .adr = { .drv = 1, .cs = 2, .swr = 5, .swg = 4, .swb = 6 }, .scan = 90 }, \
{ .id = 10, .x = 8.25, .y = 0, .adr = { .drv = 1, .cs = 3, .swr = 5, .swg = 4, .swb = 6 }, .scan = 91 }, \
{ .id = 11, .x = 9, .y = 0, .adr = { .drv = 1, .cs = 4, .swr = 5, .swg = 4, .swb = 6 }, .scan = 92 }, \
{ .id = 12, .x = 9.75, .y = 0, .adr = { .drv = 1, .cs = 5, .swr = 5, .swg = 4, .swb = 6 }, .scan = 93 }, \
{ .id = 13, .x = 10.5, .y = 0, .adr = { .drv = 1, .cs = 6, .swr = 5, .swg = 4, .swb = 6 }, .scan = 94 }, \
{ .id = 14, .x = 11.625, .y = 0, .adr = { .drv = 1, .cs = 7, .swr = 5, .swg = 4, .swb = 6 }, .scan = 95 }, \
{ .id = 15, .x = 12.375, .y = 0, .adr = { .drv = 1, .cs = 8, .swr = 5, .swg = 4, .swb = 6 }, .scan = 96 }, \
{ .id = 16, .x = 13.125, .y = 0, .adr = { .drv = 1, .cs = 9, .swr = 5, .swg = 4, .swb = 6 }, .scan = 97 }, \
{ .id = 17, .x = 0, .y = -1.125, .adr = { .drv = 2, .cs = 1, .swr = 8, .swg = 7, .swb = 9 }, .scan = 15 }, \
{ .id = 18, .x = 0.75, .y = -1.125, .adr = { .drv = 2, .cs = 2, .swr = 8, .swg = 7, .swb = 9 }, .scan = 16 }, \
{ .id = 19, .x = 1.5, .y = -1.125, .adr = { .drv = 2, .cs = 3, .swr = 8, .swg = 7, .swb = 9 }, .scan = 17 }, \
{ .id = 20, .x = 2.25, .y = -1.125, .adr = { .drv = 2, .cs = 4, .swr = 8, .swg = 7, .swb = 9 }, .scan = 18 }, \
{ .id = 21, .x = 3, .y = -1.125, .adr = { .drv = 2, .cs = 5, .swr = 8, .swg = 7, .swb = 9 }, .scan = 19 }, \
{ .id = 22, .x = 3.75, .y = -1.125, .adr = { .drv = 2, .cs = 6, .swr = 8, .swg = 7, .swb = 9 }, .scan = 20 }, \
{ .id = 23, .x = 4.5, .y = -1.125, .adr = { .drv = 2, .cs = 7, .swr = 8, .swg = 7, .swb = 9 }, .scan = 21 }, \
{ .id = 24, .x = 5.25, .y = -1.125, .adr = { .drv = 2, .cs = 8, .swr = 8, .swg = 7, .swb = 9 }, .scan = 22 }, \
{ .id = 25, .x = 6, .y = -1.125, .adr = { .drv = 1, .cs = 1, .swr = 8, .swg = 7, .swb = 9 }, .scan = 105 }, \
{ .id = 26, .x = 6.75, .y = -1.125, .adr = { .drv = 1, .cs = 2, .swr = 8, .swg = 7, .swb = 9 }, .scan = 106 }, \
{ .id = 27, .x = 7.5, .y = -1.125, .adr = { .drv = 1, .cs = 3, .swr = 8, .swg = 7, .swb = 9 }, .scan = 107 }, \
{ .id = 28, .x = 8.25, .y = -1.125, .adr = { .drv = 1, .cs = 4, .swr = 8, .swg = 7, .swb = 9 }, .scan = 108 }, \
{ .id = 29, .x = 9, .y = -1.125, .adr = { .drv = 1, .cs = 5, .swr = 8, .swg = 7, .swb = 9 }, .scan = 109 }, \
{ .id = 30, .x = 10.125, .y = -1.125, .adr = { .drv = 1, .cs = 6, .swr = 8, .swg = 7, .swb = 9 }, .scan = 110 }, \
{ .id = 31, .x = 11.625, .y = -1.125, .adr = { .drv = 1, .cs = 7, .swr = 8, .swg = 7, .swb = 9 }, .scan = 111 }, \
{ .id = 32, .x = 12.375, .y = -1.125, .adr = { .drv = 1, .cs = 8, .swr = 8, .swg = 7, .swb = 9 }, .scan = 112 }, \
{ .id = 33, .x = 13.125, .y = -1.125, .adr = { .drv = 1, .cs = 9, .swr = 8, .swg = 7, .swb = 9 }, .scan = 142 }, \
{ .id = 34, .x = 0.188, .y = -1.875, .adr = { .drv = 2, .cs = 1, .swr = 11, .swg = 10, .swb = 12 }, .scan = 30 }, \
{ .id = 35, .x = 1.125, .y = -1.875, .adr = { .drv = 2, .cs = 2, .swr = 11, .swg = 10, .swb = 12 }, .scan = 31 }, \
{ .id = 36, .x = 1.875, .y = -1.875, .adr = { .drv = 2, .cs = 3, .swr = 11, .swg = 10, .swb = 12 }, .scan = 32 }, \
{ .id = 37, .x = 2.625, .y = -1.875, .adr = { .drv = 2, .cs = 4, .swr = 11, .swg = 10, .swb = 12 }, .scan = 33 }, \
{ .id = 38, .x = 3.375, .y = -1.875, .adr = { .drv = 2, .cs = 5, .swr = 11, .swg = 10, .swb = 12 }, .scan = 34 }, \
{ .id = 39, .x = 4.125, .y = -1.875, .adr = { .drv = 2, .cs = 6, .swr = 11, .swg = 10, .swb = 12 }, .scan = 35 }, \
{ .id = 40, .x = 4.875, .y = -1.875, .adr = { .drv = 2, .cs = 7, .swr = 11, .swg = 10, .swb = 12 }, .scan = 36 }, \
{ .id = 41, .x = 5.625, .y = -1.875, .adr = { .drv = 2, .cs = 8, .swr = 11, .swg = 10, .swb = 12 }, .scan = 37 }, \
{ .id = 42, .x = 6.375, .y = -1.875, .adr = { .drv = 1, .cs = 1, .swr = 11, .swg = 10, .swb = 12 }, .scan = 120 }, \
{ .id = 43, .x = 7.125, .y = -1.875, .adr = { .drv = 1, .cs = 2, .swr = 11, .swg = 10, .swb = 12 }, .scan = 121 }, \
{ .id = 44, .x = 7.875, .y = -1.875, .adr = { .drv = 1, .cs = 3, .swr = 11, .swg = 10, .swb = 12 }, .scan = 122 }, \
{ .id = 45, .x = 8.625, .y = -1.875, .adr = { .drv = 1, .cs = 4, .swr = 11, .swg = 10, .swb = 12 }, .scan = 123 }, \
{ .id = 46, .x = 9.375, .y = -1.875, .adr = { .drv = 1, .cs = 5, .swr = 11, .swg = 10, .swb = 12 }, .scan = 124 }, \
{ .id = 47, .x = 10.312, .y = -1.875, .adr = { .drv = 1, .cs = 6, .swr = 11, .swg = 10, .swb = 12 }, .scan = 125 }, \
{ .id = 48, .x = 11.625, .y = -1.875, .adr = { .drv = 1, .cs = 7, .swr = 11, .swg = 10, .swb = 12 }, .scan = 126 }, \
{ .id = 49, .x = 12.375, .y = -1.875, .adr = { .drv = 1, .cs = 8, .swr = 11, .swg = 10, .swb = 12 }, .scan = 127 }, \
{ .id = 50, .x = 13.125, .y = -1.875, .adr = { .drv = 1, .cs = 9, .swr = 11, .swg = 10, .swb = 12 }, .scan = 141 }, \
{ .id = 51, .x = 0.281, .y = -2.625, .adr = { .drv = 2, .cs = 1, .swr = 5, .swg = 4, .swb = 6 }, .scan = 45 }, \
{ .id = 52, .x = 1.313, .y = -2.625, .adr = { .drv = 2, .cs = 2, .swr = 5, .swg = 4, .swb = 6 }, .scan = 46 }, \
{ .id = 53, .x = 2.063, .y = -2.625, .adr = { .drv = 2, .cs = 13, .swr = 11, .swg = 10, .swb = 12 }, .scan = 47 }, \
{ .id = 54, .x = 2.812, .y = -2.625, .adr = { .drv = 2, .cs = 12, .swr = 11, .swg = 10, .swb = 12 }, .scan = 48 }, \
{ .id = 55, .x = 3.562, .y = -2.625, .adr = { .drv = 2, .cs = 11, .swr = 11, .swg = 10, .swb = 12 }, .scan = 49 }, \
{ .id = 56, .x = 4.312, .y = -2.625, .adr = { .drv = 2, .cs = 6, .swr = 5, .swg = 4, .swb = 6 }, .scan = 50 }, \
{ .id = 57, .x = 5.062, .y = -2.625, .adr = { .drv = 2, .cs = 10, .swr = 11, .swg = 10, .swb = 12 }, .scan = 51 }, \
{ .id = 58, .x = 5.812, .y = -2.625, .adr = { .drv = 2, .cs = 9, .swr = 11, .swg = 10, .swb = 12 }, .scan = 52 }, \
{ .id = 59, .x = 6.562, .y = -2.625, .adr = { .drv = 1, .cs = 16, .swr = 11, .swg = 10, .swb = 12 }, .scan = 135 }, \
{ .id = 60, .x = 7.312, .y = -2.625, .adr = { .drv = 1, .cs = 15, .swr = 11, .swg = 10, .swb = 12 }, .scan = 136 }, \
{ .id = 61, .x = 8.062, .y = -2.625, .adr = { .drv = 1, .cs = 14, .swr = 11, .swg = 10, .swb = 12 }, .scan = 137 }, \
{ .id = 62, .x = 8.812, .y = -2.625, .adr = { .drv = 1, .cs = 13, .swr = 11, .swg = 10, .swb = 12 }, .scan = 138 }, \
{ .id = 63, .x = 10.031, .y = -2.625, .adr = { .drv = 1, .cs = 12, .swr = 11, .swg = 10, .swb = 12 }, .scan = 139 }, \
{ .id = 64, .x = 0.469, .y = -3.375, .adr = { .drv = 2, .cs = 14, .swr = 5, .swg = 4, .swb = 6 }, .scan = 60 }, \
{ .id = 65, .x = 1.688, .y = -3.375, .adr = { .drv = 2, .cs = 13, .swr = 5, .swg = 4, .swb = 6 }, .scan = 61 }, \
{ .id = 66, .x = 2.438, .y = -3.375, .adr = { .drv = 2, .cs = 12, .swr = 8, .swg = 7, .swb = 9 }, .scan = 62 }, \
{ .id = 67, .x = 3.188, .y = -3.375, .adr = { .drv = 2, .cs = 12, .swr = 5, .swg = 4, .swb = 6 }, .scan = 63 }, \
{ .id = 68, .x = 3.938, .y = -3.375, .adr = { .drv = 2, .cs = 11, .swr = 5, .swg = 4, .swb = 6 }, .scan = 64 }, \
{ .id = 69, .x = 4.688, .y = -3.375, .adr = { .drv = 2, .cs = 10, .swr = 5, .swg = 4, .swb = 6 }, .scan = 65 }, \
{ .id = 70, .x = 5.438, .y = -3.375, .adr = { .drv = 2, .cs = 9, .swr = 5, .swg = 4, .swb = 6 }, .scan = 66 }, \
{ .id = 71, .x = 6.188, .y = -3.375, .adr = { .drv = 2, .cs = 9, .swr = 8, .swg = 7, .swb = 9 }, .scan = 67 }, \
{ .id = 72, .x = 6.938, .y = -3.375, .adr = { .drv = 1, .cs = 16, .swr = 8, .swg = 7, .swb = 9 }, .scan = 150 }, \
{ .id = 73, .x = 7.688, .y = -3.375, .adr = { .drv = 1, .cs = 15, .swr = 8, .swg = 7, .swb = 9 }, .scan = 151 }, \
{ .id = 74, .x = 8.438, .y = -3.375, .adr = { .drv = 1, .cs = 14, .swr = 8, .swg = 7, .swb = 9 }, .scan = 152 }, \
{ .id = 75, .x = 9.844, .y = -3.375, .adr = { .drv = 1, .cs = 13, .swr = 8, .swg = 7, .swb = 9 }, .scan = 153 }, \
{ .id = 76, .x = 12.375, .y = -3.375, .adr = { .drv = 1, .cs = 11, .swr = 8, .swg = 7, .swb = 9 }, .scan = 140 }, \
{ .id = 77, .x = 0.094, .y = -4.125, .adr = { .drv = 2, .cs = 14, .swr = 11, .swg = 10, .swb = 12 }, .scan = 75 }, \
{ .id = 78, .x = 1.031, .y = -4.125, .adr = { .drv = 2, .cs = 14, .swr = 8, .swg = 7, .swb = 9 }, .scan = 76 }, \
{ .id = 79, .x = 1.969, .y = -4.125, .adr = { .drv = 2, .cs = 13, .swr = 8, .swg = 7, .swb = 9 }, .scan = 77 }, \
{ .id = 80, .x = 4.781, .y = -4.125, .adr = { .drv = 2, .cs = 10, .swr = 8, .swg = 7, .swb = 9 }, .scan = 78 }, \
{ .id = 81, .x = 7.594, .y = -4.125, .adr = { .drv = 1, .cs = 16, .swr = 5, .swg = 4, .swb = 6 }, .scan = 79 }, \
{ .id = 82, .x = 8.531, .y = -4.125, .adr = { .drv = 1, .cs = 15, .swr = 5, .swg = 4, .swb = 6 }, .scan = 80 }, \
{ .id = 83, .x = 9.469, .y = -4.125, .adr = { .drv = 1, .cs = 14, .swr = 5, .swg = 4, .swb = 6 }, .scan = 81 }, \
{ .id = 84, .x = 10.406, .y = -4.125, .adr = { .drv = 1, .cs = 13, .swr = 5, .swg = 4, .swb = 6 }, .scan = 82 }, \
{ .id = 85, .x = 11.625, .y = -4.125, .adr = { .drv = 1, .cs = 12, .swr = 8, .swg = 7, .swb = 9 }, .scan = 154 }, \
{ .id = 86, .x = 12.375, .y = -4.125, .adr = { .drv = 1, .cs = 12, .swr = 5, .swg = 4, .swb = 6 }, .scan = 155 }, \
{ .id = 87, .x = 13.125, .y = -4.125, .adr = { .drv = 1, .cs = 11, .swr = 5, .swg = 4, .swb = 6 }, .scan = 156 }, \
{ .id = 88, .x = 13.433, .y = -4.43, .adr = { .drv = 1, .cs = 11, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 89, .x = 12.285, .y = -4.535, .adr = { .drv = 1, .cs = 12, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 90, .x = 11.14, .y = -4.535, .adr = { .drv = 1, .cs = 13, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 91, .x = 9.995, .y = -4.535, .adr = { .drv = 1, .cs = 14, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 92, .x = 8.85, .y = -4.535, .adr = { .drv = 1, .cs = 15, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 93, .x = 7.705, .y = -4.535, .adr = { .drv = 1, .cs = 16, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 94, .x = 6.56, .y = -4.535, .adr = { .drv = 2, .cs = 9, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 95, .x = 5.415, .y = -4.535, .adr = { .drv = 2, .cs = 10, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 96, .x = 4.27, .y = -4.535, .adr = { .drv = 2, .cs = 11, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 97, .x = 3.125, .y = -4.535, .adr = { .drv = 2, .cs = 12, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 98, .x = 1.98, .y = -4.535, .adr = { .drv = 2, .cs = 13, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 99, .x = 0.835, .y = -4.535, .adr = { .drv = 2, .cs = 14, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 100, .x = -0.307, .y = -4.43, .adr = { .drv = 2, .cs = 15, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 101, .x = -0.41, .y = -3.245, .adr = { .drv = 2, .cs = 15, .swr = 11, .swg = 10, .swb = 12 }, .scan = 255 }, \
{ .id = 102, .x = -0.41, .y = -2.06, .adr = { .drv = 2, .cs = 15, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
{ .id = 103, .x = -0.41, .y = -0.875, .adr = { .drv = 2, .cs = 15, .swr = 8, .swg = 7, .swb = 9 }, .scan = 255 }, \
{ .id = 104, .x = -0.308, .y = 0.31, .adr = { .drv = 2, .cs = 1, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 105, .x = 0.835, .y = 0.415, .adr = { .drv = 2, .cs = 3, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 106, .x = 1.98, .y = 0.415, .adr = { .drv = 2, .cs = 4, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 107, .x = 3.125, .y = 0.415, .adr = { .drv = 2, .cs = 5, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 108, .x = 4.27, .y = 0.415, .adr = { .drv = 2, .cs = 7, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 109, .x = 5.415, .y = 0.415, .adr = { .drv = 2, .cs = 8, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 110, .x = 6.56, .y = 0.415, .adr = { .drv = 1, .cs = 1, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 111, .x = 7.705, .y = 0.415, .adr = { .drv = 1, .cs = 2, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 112, .x = 8.85, .y = 0.415, .adr = { .drv = 1, .cs = 3, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 113, .x = 9.995, .y = 0.415, .adr = { .drv = 1, .cs = 5, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 114, .x = 11.14, .y = 0.415, .adr = { .drv = 1, .cs = 6, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 115, .x = 12.285, .y = 0.415, .adr = { .drv = 1, .cs = 8, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 116, .x = 13.432, .y = 0.31, .adr = { .drv = 1, .cs = 10, .swr = 2, .swg = 1, .swb = 3 }, .scan = 255 }, \
{ .id = 117, .x = 13.535, .y = -0.875, .adr = { .drv = 1, .cs = 10, .swr = 8, .swg = 7, .swb = 9 }, .scan = 255 }, \
{ .id = 118, .x = 13.535, .y = -2.06, .adr = { .drv = 1, .cs = 10, .swr = 11, .swg = 10, .swb = 12 }, .scan = 255 }, \
{ .id = 119, .x = 13.535, .y = -3.245, .adr = { .drv = 1, .cs = 10, .swr = 5, .swg = 4, .swb = 6 }, .scan = 255 }, \
};
#define USB_LED_INDICATOR_ENABLE //Comment out to disable indicator functionality
#ifdef USB_LED_INDICATOR_ENABLE //Scan codes refer to actual key matrix codes, not KC_* (255 to disable)
#define USB_LED_NUM_LOCK_SCANCODE 255
#define USB_LED_CAPS_LOCK_SCANCODE 45
#define USB_LED_SCROLL_LOCK_SCANCODE 96
#define USB_LED_COMPOSE_SCANCODE 255
#define USB_LED_KANA_SCANCODE 255
#endif //USB_LED_INDICATOR_ENABLE
#endif //_config_led_h_

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#pragma once
#include "quantum.h"
#include "config_led.h"
#include "matrix.h"
#include "i2c_master.h"
#include "led_matrix.h" //For led keycodes
#include "usb/udi_cdc.h"
#include "usb/usb2422.h"
#define LAYOUT( \
K01, K02, K03, K04, K05, K06, K07, K08, K09, K10, K11, K12, K13, K14, K15, \
K16, K17, K18, K19, K20, K21, K22, K23, K24, K25, K26, K27, K28, K29, K30, \
K31, K32, K33, K34, K35, K36, K37, K38, K39, K40, K41, K42, K43, K44, K45, \
K46, K47, K48, K49, K50, K51, K52, K53, K54, K55, K56, K57, K58, K59, K60, \
K61, K62, K63, K64, K65, K66, K67, K68, K69, K70, K71, K72, K73, K74, K75, \
K76, K77, K78, K79, K80, K81, K82, K83, K84, K85, K86, K87 \
\
) { \
{ K01, K02, K03, K04, K05, K06, K07, K08 }, \
{ K17, K18, K19, K20, K21, K22, K23, K24 }, \
{ K34, K35, K36, K37, K38, K39, K40, K41 }, \
{ K51, K52, K53, K54, K55, K56, K57, K58 }, \
{ K64, K65, K66, K67, K68, K69, K70, K71 }, \
{ K77, K78, K79, K80, K81, K82, K83, K84 }, \
{ K09, K10, K11, K12, K13, K14, K15, K16 }, \
{ K25, K26, K27, K28, K29, K30, K31, K32 }, \
{ K42, K43, K44, K45, K46, K47, K48, K49 }, \
{ K59, K60, K61, K62, K63, K76, K50, K33 }, \
{ K72, K73, K74, K75, K85, K86, K87, }, \
}

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#include QMK_KEYBOARD_H
enum alt67_keycodes {
L_BRI = SAFE_RANGE, //LED Brightness Increase
L_BRD, //LED Brightness Decrease
L_PTN, //LED Pattern Select Next
L_PTP, //LED Pattern Select Previous
L_PSI, //LED Pattern Speed Increase
L_PSD, //LED Pattern Speed Decrease
L_T_MD, //LED Toggle Mode
L_T_ONF, //LED Toggle On / Off
L_ON, //LED On
L_OFF, //LED Off
L_T_BR, //LED Toggle Breath Effect
L_T_PTD, //LED Toggle Scrolling Pattern Direction
U_T_AUTO, //USB Extra Port Toggle Auto Detect / Always Active
U_T_AGCR, //USB Toggle Automatic GCR control
DBG_TOG, //DEBUG Toggle On / Off
DBG_MTRX, //DEBUG Toggle Matrix Prints
DBG_KBD, //DEBUG Toggle Keyboard Prints
DBG_MOU, //DEBUG Toggle Mouse Prints
};
#define TG_NKRO MAGIC_TOGGLE_NKRO //Toggle 6KRO / NKRO mode
keymap_config_t keymap_config;
const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
[0] = LAYOUT(
KC_ESC, KC_F1, KC_F2, KC_F3, KC_F4, KC_F5, KC_F6, KC_F7, KC_F8, KC_F9, KC_F10, KC_F11, KC_F12, KC_PSCR, KC_SLCK, KC_PAUS, \
KC_GRV, KC_1, KC_2, KC_3, KC_4, KC_5, KC_6, KC_7, KC_8, KC_9, KC_0, KC_MINS, KC_EQL, KC_BSPC, KC_INS, KC_HOME, KC_PGUP, \
KC_TAB, KC_Q, KC_W, KC_E, KC_R, KC_T, KC_Y, KC_U, KC_I, KC_O, KC_P, KC_LBRC, KC_RBRC, KC_BSLS, KC_DEL, KC_END, KC_PGDN, \
KC_CAPS, KC_A, KC_S, KC_D, KC_F, KC_G, KC_H, KC_J, KC_K, KC_L, KC_SCLN, KC_QUOT, KC_ENT, \
KC_LSFT, KC_Z, KC_X, KC_C, KC_V, KC_B, KC_N, KC_M, KC_COMM, KC_DOT, KC_SLSH, KC_RSFT, KC_UP, \
KC_LCTL, KC_LGUI, KC_LALT, KC_SPC, KC_RALT, MO(1), KC_APP, KC_RCTL, KC_LEFT, KC_DOWN, KC_RGHT \
),
[1] = LAYOUT(
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_MUTE, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_MPLY, KC_MSTP, KC_VOLU, \
L_T_BR, L_PSD, L_BRI, L_PSI, KC_TRNS, KC_TRNS, KC_TRNS, U_T_AUTO,U_T_AGCR,KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_MPRV, KC_MNXT, KC_VOLD, \
L_T_PTD, L_PTP, L_BRD, L_PTN, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, L_T_MD, L_T_ONF, KC_TRNS, KC_TRNS, KC_TRNS, TG_NKRO, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS \
),
/*
[X] = LAYOUT(
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, TG_NKRO, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, \
KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS, KC_TRNS \
),
*/
};
const uint16_t PROGMEM fn_actions[] = {
};
// Runs just one time when the keyboard initializes.
void matrix_init_user(void) {
};
// Runs constantly in the background, in a loop.
void matrix_scan_user(void) {
};
#define MODS_SHIFT (keyboard_report->mods & MOD_BIT(KC_LSHIFT) || keyboard_report->mods & MOD_BIT(KC_RSHIFT))
#define MODS_CTRL (keyboard_report->mods & MOD_BIT(KC_LCTL) || keyboard_report->mods & MOD_BIT(KC_RCTRL))
#define MODS_ALT (keyboard_report->mods & MOD_BIT(KC_LALT) || keyboard_report->mods & MOD_BIT(KC_RALT))
bool process_record_user(uint16_t keycode, keyrecord_t *record) {
switch (keycode) {
case L_BRI:
if (record->event.pressed) {
if (LED_GCR_STEP > LED_GCR_MAX - gcr_desired) gcr_desired = LED_GCR_MAX;
else gcr_desired += LED_GCR_STEP;
if (led_animation_breathing) gcr_breathe = gcr_desired;
}
return false;
case L_BRD:
if (record->event.pressed) {
if (LED_GCR_STEP > gcr_desired) gcr_desired = 0;
else gcr_desired -= LED_GCR_STEP;
if (led_animation_breathing) gcr_breathe = gcr_desired;
}
return false;
case L_PTN:
if (record->event.pressed) {
if (led_animation_id == led_setups_count - 1) led_animation_id = 0;
else led_animation_id++;
}
return false;
case L_PTP:
if (record->event.pressed) {
if (led_animation_id == 0) led_animation_id = led_setups_count - 1;
else led_animation_id--;
}
return false;
case L_PSI:
if (record->event.pressed) {
led_animation_speed += ANIMATION_SPEED_STEP;
}
return false;
case L_PSD:
if (record->event.pressed) {
led_animation_speed -= ANIMATION_SPEED_STEP;
if (led_animation_speed < 0) led_animation_speed = 0;
}
return false;
case L_T_MD:
if (record->event.pressed) {
led_lighting_mode++;
if (led_lighting_mode > LED_MODE_MAX_INDEX) led_lighting_mode = LED_MODE_NORMAL;
}
return false;
case L_T_ONF:
if (record->event.pressed) {
led_enabled = !led_enabled;
I2C3733_Control_Set(led_enabled);
}
return false;
case L_ON:
if (record->event.pressed) {
led_enabled = 1;
I2C3733_Control_Set(led_enabled);
}
return false;
case L_OFF:
if (record->event.pressed) {
led_enabled = 0;
I2C3733_Control_Set(led_enabled);
}
return false;
case L_T_BR:
if (record->event.pressed) {
led_animation_breathing = !led_animation_breathing;
if (led_animation_breathing)
{
gcr_breathe = gcr_desired;
led_animation_breathe_cur = BREATHE_MIN_STEP;
breathe_dir = 1;
}
}
return false;
case L_T_PTD:
if (record->event.pressed) {
led_animation_direction = !led_animation_direction;
}
return false;
case U_T_AUTO:
if (record->event.pressed && MODS_SHIFT && MODS_CTRL) {
usb_extra_manual = !usb_extra_manual;
CDC_print("USB extra port manual mode ");
CDC_print(usb_extra_manual ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case U_T_AGCR:
if (record->event.pressed && MODS_SHIFT && MODS_CTRL) {
usb_gcr_auto = !usb_gcr_auto;
CDC_print("USB GCR auto mode ");
CDC_print(usb_gcr_auto ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case DBG_TOG:
if (record->event.pressed) {
debug_enable = !debug_enable;
CDC_print("Debug mode ");
CDC_print(debug_enable ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case DBG_MTRX:
if (record->event.pressed) {
debug_matrix = !debug_matrix;
CDC_print("Debug matrix ");
CDC_print(debug_matrix ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case DBG_KBD:
if (record->event.pressed) {
debug_keyboard = !debug_keyboard;
CDC_print("Debug keyboard ");
CDC_print(debug_keyboard ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
case DBG_MOU:
if (record->event.pressed) {
debug_mouse = !debug_mouse;
CDC_print("Debug mouse ");
CDC_print(debug_mouse ? "enabled" : "disabled");
CDC_print("\r\n");
}
return false;
default:
return true; //Process all other keycodes normally
}
}

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/*
Copyright 2018 Massdrop Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "ctrl.h"
#include "led_matrix.h"
//Teal <-> Salmon
led_setup_t leds_teal_salmon[] = {
{ .hs = 0, .he = 33, .rs = 24, .re = 24, .gs = 215, .ge = 215, .bs = 204, .be = 204, .ef = EF_NONE },
{ .hs = 33, .he = 66, .rs = 24, .re = 255, .gs = 215, .ge = 114, .bs = 204, .be = 118, .ef = EF_NONE },
{ .hs = 66, .he = 100, .rs = 255, .re = 255, .gs = 114, .ge = 114, .bs = 118, .be = 118, .ef = EF_NONE },
{ .end = 1 },
};
//Yellow
led_setup_t leds_yellow[] = {
{ .hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_NONE },
{ .end = 1 },
};
//Off
led_setup_t leds_off[] = {
{ .hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_NONE },
{ .end = 1 },
};
//Red
led_setup_t leds_red[] = {
{ .hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_NONE },
{ .end = 1 },
};
//Green
led_setup_t leds_green[] = {
{ .hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_NONE },
{ .end = 1 },
};
//Blue
led_setup_t leds_blue[] = {
{ .hs = 0, .he = 100, .rs = 0, .re = 0, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_NONE },
{ .end = 1 },
};
//White
led_setup_t leds_white[] = {
{ .hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 255, .be = 255, .ef = EF_NONE },
{ .end = 1 },
};
//White with moving red stripe
led_setup_t leds_white_with_red_stripe[] = {
{ .hs = 0, .he = 100, .rs = 255, .re = 255, .gs = 255, .ge = 255, .bs = 255, .be = 255, .ef = EF_NONE },
{ .hs = 0, .he = 15, .rs = 0, .re = 0, .gs = 0, .ge = 255, .bs = 0, .be = 255, .ef = EF_SCR_R | EF_SUBTRACT },
{ .hs = 15, .he = 30, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 0, .ef = EF_SCR_R | EF_SUBTRACT },
{ .end = 1 },
};
//Black with moving red stripe
led_setup_t leds_black_with_red_stripe[] = {
{ .hs = 0, .he = 15, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_SCR_R },
{ .hs = 15, .he = 30, .rs = 255, .re = 0, .gs = 0, .ge = 0, .bs = 0, .be = 0, .ef = EF_SCR_R },
{ .end = 1 },
};
//Rainbow no scrolling
led_setup_t leds_rainbow_ns[] = {
{ .hs = 0, .he = 16.67, .rs = 255, .re = 255, .gs = 0, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER },
{ .hs = 16.67, .he = 33.33, .rs = 255, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER },
{ .hs = 33.33, .he = 50, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 255, .ef = EF_OVER },
{ .hs = 50, .he = 66.67, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER },
{ .hs = 66.67, .he = 83.33, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER },
{ .hs = 83.33, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 0, .ef = EF_OVER },
{ .end = 1 },
};
//Rainbow scrolling
led_setup_t leds_rainbow_s[] = {
{ .hs = 0, .he = 16.67, .rs = 255, .re = 255, .gs = 0, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER | EF_SCR_R },
{ .hs = 16.67, .he = 33.33, .rs = 255, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 0, .ef = EF_OVER | EF_SCR_R },
{ .hs = 33.33, .he = 50, .rs = 0, .re = 0, .gs = 255, .ge = 255, .bs = 0, .be = 255, .ef = EF_OVER | EF_SCR_R },
{ .hs = 50, .he = 66.67, .rs = 0, .re = 0, .gs = 255, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER | EF_SCR_R },
{ .hs = 66.67, .he = 83.33, .rs = 0, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 255, .ef = EF_OVER | EF_SCR_R },
{ .hs = 83.33, .he = 100, .rs = 255, .re = 255, .gs = 0, .ge = 0, .bs = 255, .be = 0, .ef = EF_OVER | EF_SCR_R },
{ .end = 1 },
};
//Add new LED animations here using one from above as example
//The last entry must be { .end = 1 }
//Add the new animation name to the list below following its format
void *led_setups[] = {
leds_rainbow_s,
leds_rainbow_ns,
leds_teal_salmon,
leds_yellow,
leds_red,
leds_green,
leds_blue,
leds_white,
leds_white_with_red_stripe,
leds_black_with_red_stripe,
leds_off
};
const uint8_t led_setups_count = sizeof(led_setups) / sizeof(led_setups[0]);

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/*
Copyright 2018 Massdrop Inc.
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "ctrl.h"
#include "d51_util.h"
#include "debug.h"
#include "clks.h"
#include <string.h>
matrix_row_t mlatest[MATRIX_ROWS];
matrix_row_t mlast[MATRIX_ROWS];
matrix_row_t mdebounced[MATRIX_ROWS];
uint8_t row_ports[] = { MATRIX_ROW_PORTS };
uint8_t row_pins[] = { MATRIX_ROW_PINS };
uint8_t col_ports[] = { MATRIX_COL_PORTS };
uint8_t col_pins[] = { MATRIX_COL_PINS };
uint32_t row_masks[2]; //NOTE: If more than PA PB used in the future, adjust code to accomodate
__attribute__ ((weak))
void matrix_init_kb(void) {
matrix_init_user();
}
__attribute__ ((weak))
void matrix_scan_kb(void) {
matrix_scan_user();
}
__attribute__ ((weak))
void matrix_init_user(void) {
}
__attribute__ ((weak))
void matrix_scan_user(void) {
}
void matrix_init(void)
{
memset(mlatest, 0, MATRIX_ROWS * sizeof(matrix_row_t));
memset(mlast, 0, MATRIX_ROWS * sizeof(matrix_row_t));
memset(mdebounced, 0, MATRIX_ROWS * sizeof(matrix_row_t));
row_masks[PA] = 0;
row_masks[PB] = 0;
uint8_t row;
for (row = 0; row < MATRIX_ROWS; row++)
{
PORT->Group[row_ports[row]].DIRCLR.reg = 1 << row_pins[row]; //Input
PORT->Group[row_ports[row]].OUTCLR.reg = 1 << row_pins[row]; //Low
PORT->Group[row_ports[row]].PINCFG[row_pins[row]].bit.INEN = 1; //Input Enable,
PORT->Group[row_ports[row]].PINCFG[row_pins[row]].bit.PULLEN = 1; //Pull Enable
row_masks[row_ports[row]] |= 1 << row_pins[row]; //Add pin to proper row mask
}
uint8_t col;
for (col = 0; col < MATRIX_COLS; col++)
{
PORT->Group[col_ports[col]].DIRSET.reg = 1 << col_pins[col]; //Output
PORT->Group[col_ports[col]].OUTCLR.reg = 1 << col_pins[col]; //Low
}
matrix_init_quantum();
}
#define MATRIX_SCAN_DELAY 10 //Delay after setting a col to output (in us)
uint64_t mdebouncing = 0;
uint8_t matrix_scan(void)
{
uint8_t mchanged;
uint8_t row;
uint8_t col;
uint32_t scans[2]; //PA PB
if (CLK_get_ms() < mdebouncing) return 1; //mdebouncing == 0 when no debouncing active
//m15_off; //Profiling scans
memset(mlatest, 0, MATRIX_ROWS * sizeof(matrix_row_t)); //Zero the result buffer
for (col = 0; col < MATRIX_COLS; col++)
{
PORT->Group[col_ports[col]].OUTSET.reg = 1 << col_pins[col]; //Set col output
CLK_delay_us(MATRIX_SCAN_DELAY); //Delay for output
scans[PA] = PORT->Group[PA].IN.reg & row_masks[PA]; //Read PA row pins data
scans[PB] = PORT->Group[PB].IN.reg & row_masks[PB]; //Read PB row pins data
PORT->Group[col_ports[col]].OUTCLR.reg = 1 << col_pins[col]; //Clear col output
for (row = 0; row < MATRIX_ROWS; row++)
{
//Move scan bits from scans array into proper row bit locations
if (scans[row_ports[row]] & (1 << row_pins[row]))
mlatest[row] |= 1 << col;
}
}
mchanged = 0; //Default to no matrix change since last
for (row = 0; row < MATRIX_ROWS; row++)
{
if (mlast[row] != mlatest[row])
mchanged = 1;
mlast[row] = mlatest[row];
}
if (!mchanged)
{
for (row = 0; row < MATRIX_ROWS; row++)
mdebounced[row] = mlatest[row];
mdebouncing = 0;
}
else
{
//Begin or extend debounce on change
mdebouncing = CLK_get_ms() + DEBOUNCING_DELAY;
}
//m15_on; //Profiling scans
matrix_scan_quantum();
return 1;
}
matrix_row_t matrix_get_row(uint8_t row)
{
return mdebounced[row];
}
void matrix_print(void)
{
char buf[(MATRIX_COLS+8)*(MATRIX_ROWS+1)] = "R C";
char *pbuf = buf+3;
uint32_t cols;
uint32_t rows;
matrix_row_t row;
for (cols = 1; cols <= MATRIX_COLS; cols++)
{
*pbuf = (cols%10)+48;
pbuf++;
}
*pbuf = '\r'; pbuf++;
*pbuf = '\n'; pbuf++;
for (rows = 1; rows <= MATRIX_ROWS; rows++)
{
row = matrix_get_row(rows-1);
if (rows < 10) { *pbuf = rows+48; pbuf++; *pbuf = ' '; pbuf++; *pbuf = ' '; pbuf++; }
else { *pbuf = (rows/10)+48; pbuf++; *pbuf = (rows%10)+48; pbuf++; *pbuf = ' '; pbuf++; }
for (cols = 0; cols < MATRIX_COLS; cols++)
{
if (row & 1 << cols) *pbuf = 'X';
else *pbuf = '.';
pbuf++;
}
*pbuf = '\r'; pbuf++;
*pbuf = '\n'; pbuf++;
}
*pbuf = 0;
dprint(buf);
}

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/*
Copyright 2011 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef MATRIX_H
#define MATRIX_H
#include <stdint.h>
#include <stdbool.h>
#include "keyboard.h"
#if (MATRIX_COLS <= 8)
typedef uint8_t matrix_row_t;
#elif (MATRIX_COLS <= 16)
typedef uint16_t matrix_row_t;
#elif (MATRIX_COLS <= 32)
typedef uint32_t matrix_row_t;
#else
#error "MATRIX_COLS: invalid value"
#endif
#define MATRIX_IS_ON(row, col) (matrix_get_row(row) && (1<<col))
#ifdef __cplusplus
extern "C" {
#endif
/* number of matrix rows */
uint8_t matrix_rows(void);
/* number of matrix columns */
uint8_t matrix_cols(void);
/* should be called at early stage of startup before matrix_init.(optional) */
void matrix_setup(void);
/* intialize matrix for scaning. */
void matrix_init(void);
/* scan all key states on matrix */
uint8_t matrix_scan(void);
/* whether modified from previous scan. used after matrix_scan. */
bool matrix_is_modified(void) __attribute__ ((deprecated));
/* whether a switch is on */
bool matrix_is_on(uint8_t row, uint8_t col);
/* matrix state on row */
matrix_row_t matrix_get_row(uint8_t row);
/* print matrix for debug */
void matrix_print(void);
/* power control */
void matrix_power_up(void);
void matrix_power_down(void);
/* executes code for Quantum */
void matrix_init_quantum(void);
void matrix_scan_quantum(void);
void matrix_init_kb(void);
void matrix_scan_kb(void);
void matrix_init_user(void);
void matrix_scan_user(void);
#ifdef __cplusplus
}
#endif
#endif

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# CTRL
![CTRL](https://massdrop-s3.imgix.net/product-images/massdrop-ntkl-mechanical-keyboard/FP/W6zvr0cTR4KVDY5z8rwp_AI7B6588%20copy%20page.jpg?auto=format&fm=jpg&fit=max&w=700&h=467&dpr=1&q=80)
The Massdrop CTRL is a TKL mechanical keyboard featuring dual USB-C connectors, an integrated Hi-Speed USB 2.0 hub, and fully customizable RGB backlighting and underlighting.
Keyboard Maintainer: [Massdrop](https://github.com/massdrop)
Hardware Supported: Massdrop, Inc. CTRL PCBs utilizing Microchip's ATSAMD51J18A MCU and USB2422 2-Port USB 2.0 Hi-Speed Hub Controller, and ISSI's IS31FL3733 LED Drivers.
Hardware Availability: [Massdrop CTRL Mechanical Keyboard](https://www.massdrop.com/buy/massdrop-ctrl-mechanical-keyboard)
Make example for this keyboard (after setting up your build environment):
make ctrl:default
See the [build environment setup](https://docs.qmk.fm/#/getting_started_build_tools) and the [make instructions](https://docs.qmk.fm/#/getting_started_make_guide) for more information. Brand new to QMK? Start with our [Complete Newbs Guide](https://docs.qmk.fm/#/newbs).

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# project specific files
SRC = led_programs.c
SRC += matrix.c
#For platform and packs
ARM_ATSAM = SAMD51J18A
MCU = cortex-m4
CUSTOM_MATRIX = yes
# Build Options
# comment out to disable the options.
#
BOOTMAGIC_ENABLE = no # Virtual DIP switch configuration(+1000)
MOUSEKEY_ENABLE = no # Mouse keys(+4700)
EXTRAKEY_ENABLE = yes # Audio control and System control(+450)
CONSOLE_ENABLE = no # Console for debug(+400)
COMMAND_ENABLE = no # Commands for debug and configuration
# Do not enable SLEEP_LED_ENABLE. it uses the same timer as BACKLIGHT_ENABLE
SLEEP_LED_ENABLE = no # Breathing sleep LED during USB suspend
# if this doesn't work, see here: https://github.com/tmk/tmk_keyboard/wiki/FAQ#nkro-doesnt-work
NKRO_ENABLE = yes # USB Nkey Rollover
BACKLIGHT_ENABLE = no # Enable keyboard backlight functionality on B7 by default
RGBLIGHT_ENABLE = no # Enable keyboard RGB underglow
MIDI_ENABLE = no # MIDI support (+2400 to 4200, depending on config)
UNICODE_ENABLE = no # Unicode
BLUETOOTH_ENABLE = no # Enable Bluetooth with the Adafruit EZ-Key HID
AUDIO_ENABLE = no # Audio output on port C6
FAUXCLICKY_ENABLE = no # Use buzzer to emulate clicky switches
HD44780_ENABLE = no # Enable support for HD44780 based LCDs (+400)
VIRTSER_ENABLE = no # USB Serial Driver
RAW_ENABLE = no # Raw device

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.1
* @date 30. January 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#include <cmsis_iar.h>
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
__packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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unless required by applicable law (such as deliberate and grossly
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has been advised of the possibility of such damages.
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on Your own behalf and on Your sole responsibility, not on behalf
of any other Contributor, and only if You agree to indemnify,
defend, and hold each Contributor harmless for any liability
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Licensed under the Apache License, Version 2.0 (the "License");
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168
lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/gcc/gcc/samd51j18a_flash.ld Normal file
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/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51J18A
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
//rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
rom (rx) : ORIGIN = 0x00004000, LENGTH = 0x0003C000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
_srom = ORIGIN(rom);
_lrom = LENGTH(rom);
_erom = ORIGIN(rom) + LENGTH(rom);
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

65
lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component-version.h Normal file
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@ -0,0 +1,65 @@
/**
* \file
*
* \brief Component version header file
*
* Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _COMPONENT_VERSION_H_INCLUDED
#define _COMPONENT_VERSION_H_INCLUDED
#define COMPONENT_VERSION_MAJOR 1
#define COMPONENT_VERSION_MINOR 0
//
// The COMPONENT_VERSION define is composed of the major and the minor version number.
//
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION
// is at least 8 digits long.
//
#define COMPONENT_VERSION 00010000
//
// The build number does not refer to the component, but to the build number
// of the device pack that provides the component.
//
#define BUILD_NUMBER 70
//
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
//
#define COMPONENT_VERSION_STRING "1.0"
//
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
//
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
//
// "%Y-%m-%d %H:%M:%S"
//
//
#define COMPONENT_DATE_STRING "2017-08-09 09:59:41"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */

598
lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/ac.h Normal file
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@ -0,0 +1,598 @@
/**
* \file
*
* \brief Component description for AC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_AC_COMPONENT_
#define _SAMD51_AC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR AC */
/* ========================================================================== */
/** \addtogroup SAMD51_AC Analog Comparators */
/*@{*/
#define AC_U2501
#define REV_AC 0x100
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos)
#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos)
#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos)
#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos)
#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos)
#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos)
#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos)
#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos)
#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos)
#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos)
#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos)
#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos)
#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos)
#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos)
#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos)
#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos)
#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos)
#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos)
#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos)
#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos)
#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos)
#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
__I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
__I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
__I uint8_t WIN:1; /*!< bit: 4 Window x */
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos)
#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos)
#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos)
#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos)
#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos)
#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */
/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */
#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos)
#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos)
#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos)
#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */
/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */
#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos)
#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos)
#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos)
#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */
/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */
#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */
#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */
#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */
/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */
#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */
/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */
#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos)
#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */
uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */
uint32_t :1; /*!< bit: 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */
uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */
uint32_t :2; /*!< bit: 22..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :1; /*!< bit: 27 Reserved */
uint32_t OUT:2; /*!< bit: 28..29 Output */
uint32_t :2; /*!< bit: 30..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */
#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */
#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */
#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */
#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */
#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */
#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */
#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */
#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */
#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos)
#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */
#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */
#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */
#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos)
#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos)
#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos)
#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */
#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */
#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */
uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */
uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */
uint32_t :27; /*!< bit: 5..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :3; /*!< bit: 0.. 2 Reserved */
uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */
uint32_t :27; /*!< bit: 5..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} AC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos)
#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */
/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */
uint16_t :14; /*!< bit: 2..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} AC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */
#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */
#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */
#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos)
#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */
__IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */
RoReg8 Reserved1[0x1];
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */
RoReg8 Reserved2[0x2];
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
RoReg8 Reserved3[0x8];
__I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
__IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_AC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for ADC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_ADC_COMPONENT_
#define _SAMD51_ADC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR ADC */
/* ========================================================================== */
/** \addtogroup SAMD51_ADC Analog Digital Converter */
/*@{*/
#define ADC_U2500
#define REV_ADC 0x100
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t :1; /*!< bit: 2 Reserved */
uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */
uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
uint16_t :4; /*!< bit: 11..14 Reserved */
uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */
#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */
#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos)
#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos)
#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos)
#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */
#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */
#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */
#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */
#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */
#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */
#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */
#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */
#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */
#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */
#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */
#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */
#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos)
#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */
#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos)
#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */
/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */
#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */
#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */
#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */
/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */
#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint16_t :2; /*!< bit: 5.. 6 Reserved */
uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */
uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint16_t :2; /*!< bit: 13..14 Reserved */
uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */
#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */
#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */
#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */
#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */
#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos)
#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */
#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */
#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos)
#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */
/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */
uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */
uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */
#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */
#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)
#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */
#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)
#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */
#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos)
#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */
#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */
#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */
#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */
#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */
#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */
#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */
#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */
#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */
#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos)
#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */
#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos)
#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */
/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */
#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */
#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */
#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */
#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */
#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */
#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */
/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */
#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */
#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */
#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */
#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */
#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */
#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */
#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */
#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */
#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */
#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */
#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */
#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */
#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :1; /*!< bit: 6 Reserved */
uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */
/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */
/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */
/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */
#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */
/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
uint8_t START:1; /*!< bit: 1 Start ADC Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */
#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */
#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos)
#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */
/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */
/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */
/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */
/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */
#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */
#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */
#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos)
#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */
#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos)
#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */
/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */
uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */
uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */
uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */
uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */
uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */
uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */
uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */
uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */
uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */
uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */
#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */
#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos)
#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */
#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos)
#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */
#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */
#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */
#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */
#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */
#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */
#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */
#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */
/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_DSEQDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */
#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */
#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */
#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos)
#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */
/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
uint32_t CTRLB:1; /*!< bit: 1 Control B */
uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
uint32_t :22; /*!< bit: 9..30 Reserved */
uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_DSEQCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */
#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */
#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */
#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos)
#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */
#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos)
#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */
#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos)
#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */
#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos)
#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */
#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos)
#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */
#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos)
#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */
#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos)
#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */
#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos)
#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */
#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos)
#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */
#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos)
#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */
/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */
uint32_t CTRLB:1; /*!< bit: 1 Control B */
uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */
uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */
uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */
uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */
uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */
uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */
uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */
uint32_t :22; /*!< bit: 9..30 Reserved */
uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_DSEQSTAT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */
#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */
#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */
#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos)
#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */
#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos)
#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */
#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos)
#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */
#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos)
#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */
#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos)
#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */
#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos)
#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */
#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos)
#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */
#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos)
#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */
#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos)
#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */
#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos)
#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */
/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */
#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */
#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */
/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_RESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */
#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */
#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */
#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos)
#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */
/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */
#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */
#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */
#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */
#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos)
#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */
#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */
RoReg8 Reserved1[0x1];
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */
RoReg8 Reserved2[0x17];
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */
__I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */
__O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */
__IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */
__I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */
RoReg8 Reserved3[0x2];
__I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */
RoReg8 Reserved4[0x2];
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_ADC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for AES
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_AES_COMPONENT_
#define _SAMD51_AES_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR AES */
/* ========================================================================== */
/** \addtogroup SAMD51_AES Advanced Encryption Standard */
/*@{*/
#define AES_U2238
#define REV_AES 0x220
/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
uint32_t :1; /*!< bit: 15 Reserved */
uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AES_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
uint8_t NEWMSG:1; /*!< bit: 1 New message */
uint8_t EOM:1; /*!< bit: 2 End of message */
uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
__I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_DATABUFPTR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_KEYWORD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_INDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_INTVECTV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_HASHKEY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_GHASH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_CIPLEN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_RANDSEED_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
/** \brief AES hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
__IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
__IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
__IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
RoReg8 Reserved1[0x2];
__O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
RoReg8 Reserved2[0xC];
__IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
__O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
RoReg8 Reserved3[0x10];
__IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
__IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
RoReg8 Reserved4[0x4];
__IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
__IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
} Aes;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_AES_COMPONENT_ */

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/**
* \file
*
* \brief Component description for CCL
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_CCL_COMPONENT_
#define _SAMD51_CCL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR CCL */
/* ========================================================================== */
/** \addtogroup SAMD51_CCL Configurable Custom Logic */
/*@{*/
#define CCL_U2225
#define REV_CCL 0x110
/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} CCL_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */
#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} CCL_SEQCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
uint32_t :2; /*!< bit: 2.. 3 Reserved */
uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
uint32_t :1; /*!< bit: 6 Reserved */
uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */
uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */
uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CCL_LUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
/** \brief CCL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
RoReg8 Reserved1[0x3];
__IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
RoReg8 Reserved2[0x2];
__IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
} Ccl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_CCL_COMPONENT_ */

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/**
* \file
*
* \brief Component description for CMCC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_CMCC_COMPONENT_
#define _SAMD51_CMCC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR CMCC */
/* ========================================================================== */
/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */
/*@{*/
#define CMCC_U2015
#define REV_CMCC 0x600
/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */
uint32_t :2; /*!< bit: 2.. 3 Reserved */
uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */
uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */
uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */
uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */
uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */
uint32_t :18; /*!< bit: 14..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_TYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */
#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */
#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */
#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */
#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */
#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */
#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */
#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */
#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */
#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */
uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */
uint32_t :1; /*!< bit: 3 Reserved */
uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_CFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */
#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */
#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */
#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */
#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */
#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */
#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_SR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */
#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */
#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */
uint32_t :28; /*!< bit: 4..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_LCKWAY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */
#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_MAINT0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :4; /*!< bit: 0.. 3 Reserved */
uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */
uint32_t :16; /*!< bit: 12..27 Reserved */
uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_MAINT1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */
#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */
#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_MCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */
#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */
#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */
#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_MEN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_MCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CMCC_MSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */
#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
/** \brief CMCC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */
__IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
__O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
__I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */
__IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
RoReg8 Reserved1[0xC];
__O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
__O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
__IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
__IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
__O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
__I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */
} Cmcc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_CMCC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for DAC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_DAC_COMPONENT_
#define _SAMD51_DAC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR DAC */
/* ========================================================================== */
/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */
/*@{*/
#define DAC_U2502
#define REV_DAC 0x100
/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */
#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */
#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */
/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */
uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */
#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */
#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */
#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */
#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */
#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */
#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */
#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */
#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */
/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */
uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */
uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */
uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */
uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */
uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */
uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */
uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */
uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */
uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */
uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */
#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */
#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */
#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */
#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */
#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */
#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */
#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */
#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */
#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */
#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */
#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */
#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */
#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */
/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */
#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */
#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */
#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */
#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */
#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */
#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */
#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */
#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */
#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */
#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */
#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */
#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */
/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */
uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */
uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */
uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */
uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */
uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */
uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */
uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */
uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */
uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */
uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */
#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */
#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */
#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */
#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */
#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */
#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */
#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */
#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */
#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */
#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */
#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */
#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */
/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */
__I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */
__I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */
__I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */
__I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */
__I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */
__I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */
__I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */
__I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */
__I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */
__I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */
#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */
#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */
#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */
#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */
#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */
#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */
#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */
#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */
#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */
#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */
#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */
#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */
/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */
uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */
uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */
uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */
uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DAC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */
#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */
#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */
#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos)
#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */
#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos)
#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */
#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos)
#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */
#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos)
#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */
#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos)
#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */
#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos)
#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */
/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */
uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */
uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */
uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */
uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */
uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */
uint32_t :26; /*!< bit: 6..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DAC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */
#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */
#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */
#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */
#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */
#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */
#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */
#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */
#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */
/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */
uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */
uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */
uint16_t :1; /*!< bit: 4 Reserved */
uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */
uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */
uint16_t :1; /*!< bit: 12 Reserved */
uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DACCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */
#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */
#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */
#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */
#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */
#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */
#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */
#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */
#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos)
#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos)
#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos)
#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */
#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */
#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */
#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */
#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */
#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */
/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */
#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */
#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */
#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATABUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */
#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */
#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */
#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */
#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */
#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */
/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */
#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */
#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */
#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */
/** \brief DAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
RoReg8 Reserved1[0x1];
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */
__I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
__IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */
__O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */
__O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
__IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */
RoReg8 Reserved2[0x3];
__I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */
} Dac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_DAC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for EIC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_EIC_COMPONENT_
#define _SAMD51_EIC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR EIC */
/* ========================================================================== */
/** \addtogroup SAMD51_EIC External Interrupt Controller */
/*@{*/
#define EIC_U2254
#define REV_EIC 0x300
/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control A */
#define EIC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EIC_CTRLA reset_value) Control A */
#define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */
#define EIC_CTRLA_SWRST (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
#define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */
#define EIC_CTRLA_ENABLE (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
#define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */
#define EIC_CTRLA_CKSEL (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
#define EIC_CTRLA_MASK _U_(0x13) /**< \brief (EIC_CTRLA) MASK Register */
/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense Configuration */
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
uint8_t NMIASYNCH:1; /*!< bit: 4 Asynchronous Edge Detection Mode */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
#define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration */
#define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
#define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< \brief (EIC_NMICTRL) No detection */
#define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1) /**< \brief (EIC_NMICTRL) Rising-edge detection */
#define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2) /**< \brief (EIC_NMICTRL) Falling-edge detection */
#define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3) /**< \brief (EIC_NMICTRL) Both-edges detection */
#define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4) /**< \brief (EIC_NMICTRL) High-level detection */
#define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5) /**< \brief (EIC_NMICTRL) Low-level detection */
#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
#define EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
#define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) Asynchronous Edge Detection Mode */
#define EIC_NMICTRL_NMIASYNCH (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
#define EIC_NMICTRL_MASK _U_(0x1F) /**< \brief (EIC_NMICTRL) MASK Register */
/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
uint16_t :15; /*!< bit: 1..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
#define EIC_NMIFLAG_RESETVALUE _U_(0x0000) /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
#define EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
#define EIC_NMIFLAG_MASK _U_(0x0001) /**< \brief (EIC_NMIFLAG) MASK Register */
/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy Status */
uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy Status */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Synchronization Busy */
#define EIC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Synchronization Busy */
#define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software Reset Synchronization Busy Status */
#define EIC_SYNCBUSY_SWRST (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
#define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable Synchronization Busy Status */
#define EIC_SYNCBUSY_ENABLE (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
#define EIC_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */
#define EIC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
#define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
#define EIC_EVCTRL_MASK _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
#define EIC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Enable */
#define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
#define EIC_INTENCLR_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
#define EIC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Enable */
#define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
#define EIC_INTENSET_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt */
__I uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
#define EIC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt */
#define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
#define EIC_INTFLAG_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ASYNCH:16; /*!< bit: 0..15 Asynchronous Edge Detection Mode */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_ASYNCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_ASYNCH offset) External Interrupt Asynchronous Mode */
#define EIC_ASYNCH_RESETVALUE _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) External Interrupt Asynchronous Mode */
#define EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_ASYNCH) Asynchronous Edge Detection Mode */
#define EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
#define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
#define EIC_ASYNCH_MASK _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */
uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */
uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */
uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */
uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */
uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */
uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */
uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */
uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) External Interrupt Sense Configuration */
#define EIC_CONFIG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) External Interrupt Sense Configuration */
#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
#define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
#define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */
#define EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
#define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
#define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */
#define EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
#define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
#define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */
#define EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
#define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
#define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */
#define EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
#define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
#define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */
#define EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
#define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
#define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */
#define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
#define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
#define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */
#define EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
#define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
#define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */
#define EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
#define EIC_CONFIG_MASK _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
/* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DEBOUNCEN:16; /*!< bit: 0..15 Debouncer Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_DEBOUNCEN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_DEBOUNCEN_OFFSET 0x30 /**< \brief (EIC_DEBOUNCEN offset) Debouncer Enable */
#define EIC_DEBOUNCEN_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DEBOUNCEN reset_value) Debouncer Enable */
#define EIC_DEBOUNCEN_DEBOUNCEN_Pos 0 /**< \brief (EIC_DEBOUNCEN) Debouncer Enable */
#define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)
#define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
#define EIC_DEBOUNCEN_MASK _U_(0x0000FFFF) /**< \brief (EIC_DEBOUNCEN) MASK Register */
/* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PRESCALER0:3; /*!< bit: 0.. 2 Debouncer Prescaler */
uint32_t STATES0:1; /*!< bit: 3 Debouncer number of states */
uint32_t PRESCALER1:3; /*!< bit: 4.. 6 Debouncer Prescaler */
uint32_t STATES1:1; /*!< bit: 7 Debouncer number of states */
uint32_t :8; /*!< bit: 8..15 Reserved */
uint32_t TICKON:1; /*!< bit: 16 Pin Sampler frequency selection */
uint32_t :15; /*!< bit: 17..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_DPRESCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_DPRESCALER_OFFSET 0x34 /**< \brief (EIC_DPRESCALER offset) Debouncer Prescaler */
#define EIC_DPRESCALER_RESETVALUE _U_(0x00000000) /**< \brief (EIC_DPRESCALER reset_value) Debouncer Prescaler */
#define EIC_DPRESCALER_PRESCALER0_Pos 0 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
#define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)
#define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
#define EIC_DPRESCALER_STATES0_Pos 3 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
#define EIC_DPRESCALER_STATES0 (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)
#define EIC_DPRESCALER_PRESCALER1_Pos 4 /**< \brief (EIC_DPRESCALER) Debouncer Prescaler */
#define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)
#define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
#define EIC_DPRESCALER_STATES1_Pos 7 /**< \brief (EIC_DPRESCALER) Debouncer number of states */
#define EIC_DPRESCALER_STATES1 (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)
#define EIC_DPRESCALER_TICKON_Pos 16 /**< \brief (EIC_DPRESCALER) Pin Sampler frequency selection */
#define EIC_DPRESCALER_TICKON (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)
#define EIC_DPRESCALER_MASK _U_(0x000100FF) /**< \brief (EIC_DPRESCALER) MASK Register */
/* -------- EIC_PINSTATE : (EIC Offset: 0x38) (R/ 32) Pin State -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PINSTATE:16; /*!< bit: 0..15 Pin State */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_PINSTATE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_PINSTATE_OFFSET 0x38 /**< \brief (EIC_PINSTATE offset) Pin State */
#define EIC_PINSTATE_RESETVALUE _U_(0x00000000) /**< \brief (EIC_PINSTATE reset_value) Pin State */
#define EIC_PINSTATE_PINSTATE_Pos 0 /**< \brief (EIC_PINSTATE) Pin State */
#define EIC_PINSTATE_PINSTATE_Msk (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)
#define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
#define EIC_PINSTATE_MASK _U_(0x0000FFFF) /**< \brief (EIC_PINSTATE) MASK Register */
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */
__I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */
RoReg8 Reserved1[0xC];
__IO EIC_DEBOUNCEN_Type DEBOUNCEN; /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */
__IO EIC_DPRESCALER_Type DPRESCALER; /**< \brief Offset: 0x34 (R/W 32) Debouncer Prescaler */
__I EIC_PINSTATE_Type PINSTATE; /**< \brief Offset: 0x38 (R/ 32) Pin State */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_EIC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for EVSYS
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_EVSYS_COMPONENT_
#define _SAMD51_EVSYS_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR EVSYS */
/* ========================================================================== */
/** \addtogroup SAMD51_EVSYS Event System Interface */
/*@{*/
#define EVSYS_U2504
#define REV_EVSYS 0x100
/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x000) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CTRLA_OFFSET 0x000 /**< \brief (EVSYS_CTRLA offset) Control */
#define EVSYS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CTRLA reset_value) Control */
#define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */
#define EVSYS_CTRLA_SWRST (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
#define EVSYS_CTRLA_MASK _U_(0x01) /**< \brief (EVSYS_CTRLA) MASK Register */
/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x004) ( /W 32) Software Event -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */
uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */
uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */
uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */
uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */
uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */
uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */
uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */
uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */
uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */
uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */
uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */
uint32_t CHANNEL12:1; /*!< bit: 12 Channel 12 Software Selection */
uint32_t CHANNEL13:1; /*!< bit: 13 Channel 13 Software Selection */
uint32_t CHANNEL14:1; /*!< bit: 14 Channel 14 Software Selection */
uint32_t CHANNEL15:1; /*!< bit: 15 Channel 15 Software Selection */
uint32_t CHANNEL16:1; /*!< bit: 16 Channel 16 Software Selection */
uint32_t CHANNEL17:1; /*!< bit: 17 Channel 17 Software Selection */
uint32_t CHANNEL18:1; /*!< bit: 18 Channel 18 Software Selection */
uint32_t CHANNEL19:1; /*!< bit: 19 Channel 19 Software Selection */
uint32_t CHANNEL20:1; /*!< bit: 20 Channel 20 Software Selection */
uint32_t CHANNEL21:1; /*!< bit: 21 Channel 21 Software Selection */
uint32_t CHANNEL22:1; /*!< bit: 22 Channel 22 Software Selection */
uint32_t CHANNEL23:1; /*!< bit: 23 Channel 23 Software Selection */
uint32_t CHANNEL24:1; /*!< bit: 24 Channel 24 Software Selection */
uint32_t CHANNEL25:1; /*!< bit: 25 Channel 25 Software Selection */
uint32_t CHANNEL26:1; /*!< bit: 26 Channel 26 Software Selection */
uint32_t CHANNEL27:1; /*!< bit: 27 Channel 27 Software Selection */
uint32_t CHANNEL28:1; /*!< bit: 28 Channel 28 Software Selection */
uint32_t CHANNEL29:1; /*!< bit: 29 Channel 29 Software Selection */
uint32_t CHANNEL30:1; /*!< bit: 30 Channel 30 Software Selection */
uint32_t CHANNEL31:1; /*!< bit: 31 Channel 31 Software Selection */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHANNEL:32; /*!< bit: 0..31 Channel x Software Selection */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_SWEVT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_SWEVT_OFFSET 0x004 /**< \brief (EVSYS_SWEVT offset) Software Event */
#define EVSYS_SWEVT_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
#define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
#define EVSYS_SWEVT_CHANNEL0 (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
#define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
#define EVSYS_SWEVT_CHANNEL1 (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
#define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
#define EVSYS_SWEVT_CHANNEL2 (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
#define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
#define EVSYS_SWEVT_CHANNEL3 (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
#define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
#define EVSYS_SWEVT_CHANNEL4 (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
#define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
#define EVSYS_SWEVT_CHANNEL5 (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
#define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
#define EVSYS_SWEVT_CHANNEL6 (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
#define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
#define EVSYS_SWEVT_CHANNEL7 (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
#define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
#define EVSYS_SWEVT_CHANNEL8 (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
#define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
#define EVSYS_SWEVT_CHANNEL9 (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
#define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
#define EVSYS_SWEVT_CHANNEL10 (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
#define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
#define EVSYS_SWEVT_CHANNEL11 (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
#define EVSYS_SWEVT_CHANNEL12_Pos 12 /**< \brief (EVSYS_SWEVT) Channel 12 Software Selection */
#define EVSYS_SWEVT_CHANNEL12 (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
#define EVSYS_SWEVT_CHANNEL13_Pos 13 /**< \brief (EVSYS_SWEVT) Channel 13 Software Selection */
#define EVSYS_SWEVT_CHANNEL13 (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
#define EVSYS_SWEVT_CHANNEL14_Pos 14 /**< \brief (EVSYS_SWEVT) Channel 14 Software Selection */
#define EVSYS_SWEVT_CHANNEL14 (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
#define EVSYS_SWEVT_CHANNEL15_Pos 15 /**< \brief (EVSYS_SWEVT) Channel 15 Software Selection */
#define EVSYS_SWEVT_CHANNEL15 (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
#define EVSYS_SWEVT_CHANNEL16_Pos 16 /**< \brief (EVSYS_SWEVT) Channel 16 Software Selection */
#define EVSYS_SWEVT_CHANNEL16 (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
#define EVSYS_SWEVT_CHANNEL17_Pos 17 /**< \brief (EVSYS_SWEVT) Channel 17 Software Selection */
#define EVSYS_SWEVT_CHANNEL17 (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
#define EVSYS_SWEVT_CHANNEL18_Pos 18 /**< \brief (EVSYS_SWEVT) Channel 18 Software Selection */
#define EVSYS_SWEVT_CHANNEL18 (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
#define EVSYS_SWEVT_CHANNEL19_Pos 19 /**< \brief (EVSYS_SWEVT) Channel 19 Software Selection */
#define EVSYS_SWEVT_CHANNEL19 (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
#define EVSYS_SWEVT_CHANNEL20_Pos 20 /**< \brief (EVSYS_SWEVT) Channel 20 Software Selection */
#define EVSYS_SWEVT_CHANNEL20 (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
#define EVSYS_SWEVT_CHANNEL21_Pos 21 /**< \brief (EVSYS_SWEVT) Channel 21 Software Selection */
#define EVSYS_SWEVT_CHANNEL21 (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
#define EVSYS_SWEVT_CHANNEL22_Pos 22 /**< \brief (EVSYS_SWEVT) Channel 22 Software Selection */
#define EVSYS_SWEVT_CHANNEL22 (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
#define EVSYS_SWEVT_CHANNEL23_Pos 23 /**< \brief (EVSYS_SWEVT) Channel 23 Software Selection */
#define EVSYS_SWEVT_CHANNEL23 (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
#define EVSYS_SWEVT_CHANNEL24_Pos 24 /**< \brief (EVSYS_SWEVT) Channel 24 Software Selection */
#define EVSYS_SWEVT_CHANNEL24 (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
#define EVSYS_SWEVT_CHANNEL25_Pos 25 /**< \brief (EVSYS_SWEVT) Channel 25 Software Selection */
#define EVSYS_SWEVT_CHANNEL25 (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
#define EVSYS_SWEVT_CHANNEL26_Pos 26 /**< \brief (EVSYS_SWEVT) Channel 26 Software Selection */
#define EVSYS_SWEVT_CHANNEL26 (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
#define EVSYS_SWEVT_CHANNEL27_Pos 27 /**< \brief (EVSYS_SWEVT) Channel 27 Software Selection */
#define EVSYS_SWEVT_CHANNEL27 (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
#define EVSYS_SWEVT_CHANNEL28_Pos 28 /**< \brief (EVSYS_SWEVT) Channel 28 Software Selection */
#define EVSYS_SWEVT_CHANNEL28 (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
#define EVSYS_SWEVT_CHANNEL29_Pos 29 /**< \brief (EVSYS_SWEVT) Channel 29 Software Selection */
#define EVSYS_SWEVT_CHANNEL29 (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
#define EVSYS_SWEVT_CHANNEL30_Pos 30 /**< \brief (EVSYS_SWEVT) Channel 30 Software Selection */
#define EVSYS_SWEVT_CHANNEL30 (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
#define EVSYS_SWEVT_CHANNEL31_Pos 31 /**< \brief (EVSYS_SWEVT) Channel 31 Software Selection */
#define EVSYS_SWEVT_CHANNEL31 (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
#define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
#define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
#define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
#define EVSYS_SWEVT_MASK _U_(0xFFFFFFFF) /**< \brief (EVSYS_SWEVT) MASK Register */
/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x008) (R/W 8) Priority Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PRI:4; /*!< bit: 0.. 3 Channel Priority Number */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t RREN:1; /*!< bit: 7 Round-Robin Scheduling Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_PRICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_PRICTRL_OFFSET 0x008 /**< \brief (EVSYS_PRICTRL offset) Priority Control */
#define EVSYS_PRICTRL_RESETVALUE _U_(0x00) /**< \brief (EVSYS_PRICTRL reset_value) Priority Control */
#define EVSYS_PRICTRL_PRI_Pos 0 /**< \brief (EVSYS_PRICTRL) Channel Priority Number */
#define EVSYS_PRICTRL_PRI_Msk (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
#define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
#define EVSYS_PRICTRL_RREN_Pos 7 /**< \brief (EVSYS_PRICTRL) Round-Robin Scheduling Enable */
#define EVSYS_PRICTRL_RREN (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
#define EVSYS_PRICTRL_MASK _U_(0x8F) /**< \brief (EVSYS_PRICTRL) MASK Register */
/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x010) (R/W 16) Channel Pending Interrupt -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t OVR:1; /*!< bit: 8 Channel Overrun */
uint16_t EVD:1; /*!< bit: 9 Channel Event Detected */
uint16_t :4; /*!< bit: 10..13 Reserved */
uint16_t READY:1; /*!< bit: 14 Ready */
uint16_t BUSY:1; /*!< bit: 15 Busy */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} EVSYS_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTPEND_OFFSET 0x010 /**< \brief (EVSYS_INTPEND offset) Channel Pending Interrupt */
#define EVSYS_INTPEND_RESETVALUE _U_(0x4000) /**< \brief (EVSYS_INTPEND reset_value) Channel Pending Interrupt */
#define EVSYS_INTPEND_ID_Pos 0 /**< \brief (EVSYS_INTPEND) Channel ID */
#define EVSYS_INTPEND_ID_Msk (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
#define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
#define EVSYS_INTPEND_OVR_Pos 8 /**< \brief (EVSYS_INTPEND) Channel Overrun */
#define EVSYS_INTPEND_OVR (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
#define EVSYS_INTPEND_EVD_Pos 9 /**< \brief (EVSYS_INTPEND) Channel Event Detected */
#define EVSYS_INTPEND_EVD (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
#define EVSYS_INTPEND_READY_Pos 14 /**< \brief (EVSYS_INTPEND) Ready */
#define EVSYS_INTPEND_READY (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
#define EVSYS_INTPEND_BUSY_Pos 15 /**< \brief (EVSYS_INTPEND) Busy */
#define EVSYS_INTPEND_BUSY (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
#define EVSYS_INTPEND_MASK _U_(0xC30F) /**< \brief (EVSYS_INTPEND) MASK Register */
/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x014) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTSTATUS_OFFSET 0x014 /**< \brief (EVSYS_INTSTATUS offset) Interrupt Status */
#define EVSYS_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTSTATUS reset_value) Interrupt Status */
#define EVSYS_INTSTATUS_CHINT0_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel 0 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT0 (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
#define EVSYS_INTSTATUS_CHINT1_Pos 1 /**< \brief (EVSYS_INTSTATUS) Channel 1 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT1 (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
#define EVSYS_INTSTATUS_CHINT2_Pos 2 /**< \brief (EVSYS_INTSTATUS) Channel 2 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT2 (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
#define EVSYS_INTSTATUS_CHINT3_Pos 3 /**< \brief (EVSYS_INTSTATUS) Channel 3 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT3 (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
#define EVSYS_INTSTATUS_CHINT4_Pos 4 /**< \brief (EVSYS_INTSTATUS) Channel 4 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT4 (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
#define EVSYS_INTSTATUS_CHINT5_Pos 5 /**< \brief (EVSYS_INTSTATUS) Channel 5 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT5 (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
#define EVSYS_INTSTATUS_CHINT6_Pos 6 /**< \brief (EVSYS_INTSTATUS) Channel 6 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT6 (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
#define EVSYS_INTSTATUS_CHINT7_Pos 7 /**< \brief (EVSYS_INTSTATUS) Channel 7 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT7 (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
#define EVSYS_INTSTATUS_CHINT8_Pos 8 /**< \brief (EVSYS_INTSTATUS) Channel 8 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT8 (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
#define EVSYS_INTSTATUS_CHINT9_Pos 9 /**< \brief (EVSYS_INTSTATUS) Channel 9 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT9 (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
#define EVSYS_INTSTATUS_CHINT10_Pos 10 /**< \brief (EVSYS_INTSTATUS) Channel 10 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT10 (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
#define EVSYS_INTSTATUS_CHINT11_Pos 11 /**< \brief (EVSYS_INTSTATUS) Channel 11 Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT11 (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
#define EVSYS_INTSTATUS_CHINT_Pos 0 /**< \brief (EVSYS_INTSTATUS) Channel x Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT_Msk (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
#define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
#define EVSYS_INTSTATUS_MASK _U_(0x00000FFF) /**< \brief (EVSYS_INTSTATUS) MASK Register */
/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x018) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_BUSYCH_OFFSET 0x018 /**< \brief (EVSYS_BUSYCH offset) Busy Channels */
#define EVSYS_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_BUSYCH reset_value) Busy Channels */
#define EVSYS_BUSYCH_BUSYCH0_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel 0 */
#define EVSYS_BUSYCH_BUSYCH0 (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
#define EVSYS_BUSYCH_BUSYCH1_Pos 1 /**< \brief (EVSYS_BUSYCH) Busy Channel 1 */
#define EVSYS_BUSYCH_BUSYCH1 (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
#define EVSYS_BUSYCH_BUSYCH2_Pos 2 /**< \brief (EVSYS_BUSYCH) Busy Channel 2 */
#define EVSYS_BUSYCH_BUSYCH2 (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
#define EVSYS_BUSYCH_BUSYCH3_Pos 3 /**< \brief (EVSYS_BUSYCH) Busy Channel 3 */
#define EVSYS_BUSYCH_BUSYCH3 (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
#define EVSYS_BUSYCH_BUSYCH4_Pos 4 /**< \brief (EVSYS_BUSYCH) Busy Channel 4 */
#define EVSYS_BUSYCH_BUSYCH4 (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
#define EVSYS_BUSYCH_BUSYCH5_Pos 5 /**< \brief (EVSYS_BUSYCH) Busy Channel 5 */
#define EVSYS_BUSYCH_BUSYCH5 (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
#define EVSYS_BUSYCH_BUSYCH6_Pos 6 /**< \brief (EVSYS_BUSYCH) Busy Channel 6 */
#define EVSYS_BUSYCH_BUSYCH6 (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
#define EVSYS_BUSYCH_BUSYCH7_Pos 7 /**< \brief (EVSYS_BUSYCH) Busy Channel 7 */
#define EVSYS_BUSYCH_BUSYCH7 (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
#define EVSYS_BUSYCH_BUSYCH8_Pos 8 /**< \brief (EVSYS_BUSYCH) Busy Channel 8 */
#define EVSYS_BUSYCH_BUSYCH8 (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
#define EVSYS_BUSYCH_BUSYCH9_Pos 9 /**< \brief (EVSYS_BUSYCH) Busy Channel 9 */
#define EVSYS_BUSYCH_BUSYCH9 (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
#define EVSYS_BUSYCH_BUSYCH10_Pos 10 /**< \brief (EVSYS_BUSYCH) Busy Channel 10 */
#define EVSYS_BUSYCH_BUSYCH10 (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
#define EVSYS_BUSYCH_BUSYCH11_Pos 11 /**< \brief (EVSYS_BUSYCH) Busy Channel 11 */
#define EVSYS_BUSYCH_BUSYCH11 (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
#define EVSYS_BUSYCH_BUSYCH_Pos 0 /**< \brief (EVSYS_BUSYCH) Busy Channel x */
#define EVSYS_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
#define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
#define EVSYS_BUSYCH_MASK _U_(0x00000FFF) /**< \brief (EVSYS_BUSYCH) MASK Register */
/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x01C) (R/ 32) Ready Users -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t READYUSR0:1; /*!< bit: 0 Ready User for Channel 0 */
uint32_t READYUSR1:1; /*!< bit: 1 Ready User for Channel 1 */
uint32_t READYUSR2:1; /*!< bit: 2 Ready User for Channel 2 */
uint32_t READYUSR3:1; /*!< bit: 3 Ready User for Channel 3 */
uint32_t READYUSR4:1; /*!< bit: 4 Ready User for Channel 4 */
uint32_t READYUSR5:1; /*!< bit: 5 Ready User for Channel 5 */
uint32_t READYUSR6:1; /*!< bit: 6 Ready User for Channel 6 */
uint32_t READYUSR7:1; /*!< bit: 7 Ready User for Channel 7 */
uint32_t READYUSR8:1; /*!< bit: 8 Ready User for Channel 8 */
uint32_t READYUSR9:1; /*!< bit: 9 Ready User for Channel 9 */
uint32_t READYUSR10:1; /*!< bit: 10 Ready User for Channel 10 */
uint32_t READYUSR11:1; /*!< bit: 11 Ready User for Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t READYUSR:12; /*!< bit: 0..11 Ready User for Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_READYUSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_READYUSR_OFFSET 0x01C /**< \brief (EVSYS_READYUSR offset) Ready Users */
#define EVSYS_READYUSR_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (EVSYS_READYUSR reset_value) Ready Users */
#define EVSYS_READYUSR_READYUSR0_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel 0 */
#define EVSYS_READYUSR_READYUSR0 (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
#define EVSYS_READYUSR_READYUSR1_Pos 1 /**< \brief (EVSYS_READYUSR) Ready User for Channel 1 */
#define EVSYS_READYUSR_READYUSR1 (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
#define EVSYS_READYUSR_READYUSR2_Pos 2 /**< \brief (EVSYS_READYUSR) Ready User for Channel 2 */
#define EVSYS_READYUSR_READYUSR2 (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
#define EVSYS_READYUSR_READYUSR3_Pos 3 /**< \brief (EVSYS_READYUSR) Ready User for Channel 3 */
#define EVSYS_READYUSR_READYUSR3 (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
#define EVSYS_READYUSR_READYUSR4_Pos 4 /**< \brief (EVSYS_READYUSR) Ready User for Channel 4 */
#define EVSYS_READYUSR_READYUSR4 (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
#define EVSYS_READYUSR_READYUSR5_Pos 5 /**< \brief (EVSYS_READYUSR) Ready User for Channel 5 */
#define EVSYS_READYUSR_READYUSR5 (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
#define EVSYS_READYUSR_READYUSR6_Pos 6 /**< \brief (EVSYS_READYUSR) Ready User for Channel 6 */
#define EVSYS_READYUSR_READYUSR6 (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
#define EVSYS_READYUSR_READYUSR7_Pos 7 /**< \brief (EVSYS_READYUSR) Ready User for Channel 7 */
#define EVSYS_READYUSR_READYUSR7 (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
#define EVSYS_READYUSR_READYUSR8_Pos 8 /**< \brief (EVSYS_READYUSR) Ready User for Channel 8 */
#define EVSYS_READYUSR_READYUSR8 (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
#define EVSYS_READYUSR_READYUSR9_Pos 9 /**< \brief (EVSYS_READYUSR) Ready User for Channel 9 */
#define EVSYS_READYUSR_READYUSR9 (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
#define EVSYS_READYUSR_READYUSR10_Pos 10 /**< \brief (EVSYS_READYUSR) Ready User for Channel 10 */
#define EVSYS_READYUSR_READYUSR10 (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
#define EVSYS_READYUSR_READYUSR11_Pos 11 /**< \brief (EVSYS_READYUSR) Ready User for Channel 11 */
#define EVSYS_READYUSR_READYUSR11 (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
#define EVSYS_READYUSR_READYUSR_Pos 0 /**< \brief (EVSYS_READYUSR) Ready User for Channel x */
#define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
#define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
#define EVSYS_READYUSR_MASK _U_(0x00000FFF) /**< \brief (EVSYS_READYUSR) MASK Register */
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x020) (R/W 32) CHANNEL Channel n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */
uint32_t :2; /*!< bit: 12..13 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */
uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHANNEL_OFFSET 0x020 /**< \brief (EVSYS_CHANNEL offset) Channel n Control */
#define EVSYS_CHANNEL_RESETVALUE _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n Control */
#define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
#define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
#define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */
#define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) Synchronous path */
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Resynchronized path */
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Asynchronous path */
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
#define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3) /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */
#define EVSYS_CHANNEL_RUNSTDBY (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
#define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
#define EVSYS_CHANNEL_ONDEMAND (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
#define EVSYS_CHANNEL_MASK _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x024) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Disable */
uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Disable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHINTENCLR_OFFSET 0x024 /**< \brief (EVSYS_CHINTENCLR offset) Channel n Interrupt Enable Clear */
#define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */
#define EVSYS_CHINTENCLR_OVR_Pos 0 /**< \brief (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable */
#define EVSYS_CHINTENCLR_OVR (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
#define EVSYS_CHINTENCLR_EVD_Pos 1 /**< \brief (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable */
#define EVSYS_CHINTENCLR_EVD (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
#define EVSYS_CHINTENCLR_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENCLR) MASK Register */
/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x025) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVR:1; /*!< bit: 0 Channel Overrun Interrupt Enable */
uint8_t EVD:1; /*!< bit: 1 Channel Event Detected Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHINTENSET_OFFSET 0x025 /**< \brief (EVSYS_CHINTENSET offset) Channel n Interrupt Enable Set */
#define EVSYS_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTENSET reset_value) Channel n Interrupt Enable Set */
#define EVSYS_CHINTENSET_OVR_Pos 0 /**< \brief (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable */
#define EVSYS_CHINTENSET_OVR (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
#define EVSYS_CHINTENSET_EVD_Pos 1 /**< \brief (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable */
#define EVSYS_CHINTENSET_EVD (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
#define EVSYS_CHINTENSET_MASK _U_(0x03) /**< \brief (EVSYS_CHINTENSET) MASK Register */
/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x026) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t OVR:1; /*!< bit: 0 Channel Overrun */
__I uint8_t EVD:1; /*!< bit: 1 Channel Event Detected */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHINTFLAG_OFFSET 0x026 /**< \brief (EVSYS_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */
#define EVSYS_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */
#define EVSYS_CHINTFLAG_OVR_Pos 0 /**< \brief (EVSYS_CHINTFLAG) Channel Overrun */
#define EVSYS_CHINTFLAG_OVR (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
#define EVSYS_CHINTFLAG_EVD_Pos 1 /**< \brief (EVSYS_CHINTFLAG) Channel Event Detected */
#define EVSYS_CHINTFLAG_EVD (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
#define EVSYS_CHINTFLAG_MASK _U_(0x03) /**< \brief (EVSYS_CHINTFLAG) MASK Register */
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x027) (R/ 8) CHANNEL Channel n Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RDYUSR:1; /*!< bit: 0 Ready User */
uint8_t BUSYCH:1; /*!< bit: 1 Busy Channel */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHSTATUS_OFFSET 0x027 /**< \brief (EVSYS_CHSTATUS offset) Channel n Status */
#define EVSYS_CHSTATUS_RESETVALUE _U_(0x01) /**< \brief (EVSYS_CHSTATUS reset_value) Channel n Status */
#define EVSYS_CHSTATUS_RDYUSR_Pos 0 /**< \brief (EVSYS_CHSTATUS) Ready User */
#define EVSYS_CHSTATUS_RDYUSR (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
#define EVSYS_CHSTATUS_BUSYCH_Pos 1 /**< \brief (EVSYS_CHSTATUS) Busy Channel */
#define EVSYS_CHSTATUS_BUSYCH (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
#define EVSYS_CHSTATUS_MASK _U_(0x03) /**< \brief (EVSYS_CHSTATUS) MASK Register */
/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL:6; /*!< bit: 0.. 5 Channel Event Selection */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_USER_OFFSET 0x120 /**< \brief (EVSYS_USER offset) User Multiplexer n */
#define EVSYS_USER_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
#define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */
#define EVSYS_USER_CHANNEL_Msk (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
#define EVSYS_USER_MASK _U_(0x0000003F) /**< \brief (EVSYS_USER) MASK Register */
/** \brief EvsysChannel hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x000 (R/W 32) Channel n Control */
__IO EVSYS_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x004 (R/W 8) Channel n Interrupt Enable Clear */
__IO EVSYS_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x005 (R/W 8) Channel n Interrupt Enable Set */
__IO EVSYS_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x006 (R/W 8) Channel n Interrupt Flag Status and Clear */
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x007 (R/ 8) Channel n Status */
} EvsysChannel;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control */
RoReg8 Reserved1[0x3];
__O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x004 ( /W 32) Software Event */
__IO EVSYS_PRICTRL_Type PRICTRL; /**< \brief Offset: 0x008 (R/W 8) Priority Control */
RoReg8 Reserved2[0x7];
__IO EVSYS_INTPEND_Type INTPEND; /**< \brief Offset: 0x010 (R/W 16) Channel Pending Interrupt */
RoReg8 Reserved3[0x2];
__I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */
__I EVSYS_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x018 (R/ 32) Busy Channels */
__I EVSYS_READYUSR_Type READYUSR; /**< \brief Offset: 0x01C (R/ 32) Ready Users */
EvsysChannel Channel[32]; /**< \brief Offset: 0x020 EvsysChannel groups [CHANNELS] */
__IO EVSYS_USER_Type USER[67]; /**< \brief Offset: 0x120 (R/W 32) User Multiplexer n */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_EVSYS_COMPONENT_ */

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/**
* \file
*
* \brief Component description for FREQM
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_FREQM_COMPONENT_
#define _SAMD51_FREQM_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR FREQM */
/* ========================================================================== */
/** \addtogroup SAMD51_FREQM Frequency Meter */
/*@{*/
#define FREQM_U2257
#define REV_FREQM 0x110
/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */
#define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
#define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */
#define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
#define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */
#define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
#define FREQM_CTRLA_MASK _U_(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START:1; /*!< bit: 0 Start Measurement */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */
#define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
#define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */
#define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
#define FREQM_CTRLB_MASK _U_(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */
uint16_t :8; /*!< bit: 8..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} FREQM_CFGA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */
#define FREQM_CFGA_RESETVALUE _U_(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
#define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
#define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
#define FREQM_CFGA_MASK _U_(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
#define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
#define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
#define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
#define FREQM_INTENCLR_MASK _U_(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
#define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
#define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
#define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
#define FREQM_INTENSET_MASK _U_(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t DONE:1; /*!< bit: 0 Measurement Done */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
#define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
#define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */
#define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
#define FREQM_INTFLAG_MASK _U_(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t BUSY:1; /*!< bit: 0 FREQM Status */
uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */
#define FREQM_STATUS_RESETVALUE _U_(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
#define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */
#define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
#define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
#define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
#define FREQM_STATUS_MASK _U_(0x03) /**< \brief (FREQM_STATUS) MASK Register */
/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} FREQM_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
#define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
#define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */
#define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
#define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */
#define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
#define FREQM_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} FREQM_VALUE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */
#define FREQM_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
#define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */
#define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
#define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
/** \brief FREQM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */
__O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
__IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */
RoReg8 Reserved1[0x4];
__IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
__IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
__IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */
__IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */
__I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */
__I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */
} Freqm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_FREQM_COMPONENT_ */

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/**
* \file
*
* \brief Component description for GCLK
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_GCLK_COMPONENT_
#define _SAMD51_GCLK_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR GCLK */
/* ========================================================================== */
/** \addtogroup SAMD51_GCLK Generic Clock Generator */
/*@{*/
#define GCLK_U2122
#define REV_GCLK 0x120
/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */
#define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRLA reset_value) Control */
#define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */
#define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
#define GCLK_CTRLA_MASK _U_(0x01) /**< \brief (GCLK_CTRLA) MASK Register */
/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */
uint32_t :1; /*!< bit: 1 Reserved */
uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */
uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */
uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */
uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */
uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */
uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */
uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */
uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */
uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */
uint32_t GENCTRL9:1; /*!< bit: 11 Generic Clock Generator Control 9 Synchronization Busy bits */
uint32_t GENCTRL10:1; /*!< bit: 12 Generic Clock Generator Control 10 Synchronization Busy bits */
uint32_t GENCTRL11:1; /*!< bit: 13 Generic Clock Generator Control 11 Synchronization Busy bits */
uint32_t :18; /*!< bit: 14..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Busy bits */
uint32_t :18; /*!< bit: 14..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} GCLK_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
#define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
#define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
#define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
#define GCLK_SYNCBUSY_GENCTRL0_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
#define GCLK_SYNCBUSY_GENCTRL1_Pos 3 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
#define GCLK_SYNCBUSY_GENCTRL2_Pos 4 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
#define GCLK_SYNCBUSY_GENCTRL3_Pos 5 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
#define GCLK_SYNCBUSY_GENCTRL4_Pos 6 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
#define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
#define GCLK_SYNCBUSY_GENCTRL6_Pos 8 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
#define GCLK_SYNCBUSY_GENCTRL7_Pos 9 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
#define GCLK_SYNCBUSY_GENCTRL8_Pos 10 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
#define GCLK_SYNCBUSY_GENCTRL9_Pos 11 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 9 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL9 (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
#define GCLK_SYNCBUSY_GENCTRL10_Pos 12 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 10 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL10 (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
#define GCLK_SYNCBUSY_GENCTRL11_Pos 13 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 11 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL11 (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
#define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 9 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 10 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 11 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_MASK _U_(0x00003FFD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 10 Output Off Value */
uint32_t OE:1; /*!< bit: 11 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */
uint32_t :2; /*!< bit: 14..15 Reserved */
uint32_t DIV:16; /*!< bit: 16..31 Division Factor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
#define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
#define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */
#define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
#define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC0 oscillator output */
#define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) XOSC1 oscillator output */
#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generator input pad */
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
#define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) DFLL output */
#define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DPLL0 output */
#define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8) /**< \brief (GCLK_GENCTRL) DPLL1 output */
#define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
#define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
#define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
#define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
#define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */
#define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
#define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */
#define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
#define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */
#define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
#define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */
#define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
#define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */
#define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
#define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
#define GCLK_GENCTRL_MASK _U_(0xFFFF3F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t CHEN:1; /*!< bit: 6 Channel Enable */
uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_PCHCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
#define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
#define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
#define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
#define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
#define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
#define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
#define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
#define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
#define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
#define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
#define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
#define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
#define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9) /**< \brief (GCLK_PCHCTRL) Generic clock generator 9 */
#define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA) /**< \brief (GCLK_PCHCTRL) Generic clock generator 10 */
#define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB) /**< \brief (GCLK_PCHCTRL) Generic clock generator 11 */
#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */
#define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
#define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */
#define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
#define GCLK_PCHCTRL_MASK _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
RoReg8 Reserved1[0x3];
__I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
RoReg8 Reserved2[0x18];
__IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
RoReg8 Reserved3[0x30];
__IO GCLK_PCHCTRL_Type PCHCTRL[48]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_GCLK_COMPONENT_ */

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/**
* \file
*
* \brief Component description for HMATRIXB
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_HMATRIXB_COMPONENT_
#define _SAMD51_HMATRIXB_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR HMATRIXB */
/* ========================================================================== */
/** \addtogroup SAMD51_HMATRIXB HSB Matrix */
/*@{*/
#define HMATRIXB_I7638
#define REV_HMATRIXB 0x214
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
#define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
#define HMATRIXB_PRAS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
#define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
#define HMATRIXB_PRBS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
RoReg8 Reserved1[0x80];
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_HMATRIXB_COMPONENT_ */

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/**
* \file
*
* \brief Component description for I2S
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_I2S_COMPONENT_
#define _SAMD51_I2S_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR I2S */
/* ========================================================================== */
/** \addtogroup SAMD51_I2S Inter-IC Sound Interface */
/*@{*/
#define I2S_U2224
#define REV_I2S 0x200
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
uint8_t TXEN:1; /*!< bit: 4 Tx Serializer Enable */
uint8_t RXEN:1; /*!< bit: 5 Rx Serializer Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} I2S_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
#define I2S_CTRLA_RESETVALUE _U_(0x00) /**< \brief (I2S_CTRLA reset_value) Control A */
#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
#define I2S_CTRLA_SWRST (_U_(0x1) << I2S_CTRLA_SWRST_Pos)
#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
#define I2S_CTRLA_ENABLE (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)
#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
#define I2S_CTRLA_CKEN0 (_U_(1) << I2S_CTRLA_CKEN0_Pos)
#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
#define I2S_CTRLA_CKEN1 (_U_(1) << I2S_CTRLA_CKEN1_Pos)
#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
#define I2S_CTRLA_CKEN_Msk (_U_(0x3) << I2S_CTRLA_CKEN_Pos)
#define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
#define I2S_CTRLA_TXEN_Pos 4 /**< \brief (I2S_CTRLA) Tx Serializer Enable */
#define I2S_CTRLA_TXEN (_U_(0x1) << I2S_CTRLA_TXEN_Pos)
#define I2S_CTRLA_RXEN_Pos 5 /**< \brief (I2S_CTRLA) Rx Serializer Enable */
#define I2S_CTRLA_RXEN (_U_(0x1) << I2S_CTRLA_RXEN_Pos)
#define I2S_CTRLA_MASK _U_(0x3F) /**< \brief (I2S_CTRLA) MASK Register */
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
uint32_t FSINV:1; /*!< bit: 9 Frame Sync Invert */
uint32_t FSOUTINV:1; /*!< bit: 10 Frame Sync Output Invert */
uint32_t SCKSEL:1; /*!< bit: 11 Serial Clock Select */
uint32_t SCKOUTINV:1; /*!< bit: 12 Serial Clock Output Invert */
uint32_t MCKSEL:1; /*!< bit: 13 Master Clock Select */
uint32_t MCKEN:1; /*!< bit: 14 Master Clock Enable */
uint32_t MCKOUTINV:1; /*!< bit: 15 Master Clock Output Invert */
uint32_t MCKDIV:6; /*!< bit: 16..21 Master Clock Division Factor */
uint32_t :2; /*!< bit: 22..23 Reserved */
uint32_t MCKOUTDIV:6; /*!< bit: 24..29 Master Clock Output Division Factor */
uint32_t :2; /*!< bit: 30..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
#define I2S_CLKCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
#define I2S_CLKCTRL_SLOTSIZE_Msk (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
#define I2S_CLKCTRL_SLOTSIZE_8_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_16_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_24_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_32_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
#define I2S_CLKCTRL_NBSLOTS_Msk (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
#define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
#define I2S_CLKCTRL_FSWIDTH_Msk (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
#define I2S_CLKCTRL_FSWIDTH_SLOT_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
#define I2S_CLKCTRL_FSWIDTH_HALF_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
#define I2S_CLKCTRL_FSWIDTH_BIT_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
#define I2S_CLKCTRL_FSWIDTH_BURST_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
#define I2S_CLKCTRL_BITDELAY (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_BITDELAY_LJ_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
#define I2S_CLKCTRL_BITDELAY_I2S_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
#define I2S_CLKCTRL_FSSEL (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSSEL_SCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
#define I2S_CLKCTRL_FSSEL_FSPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSINV_Pos 9 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
#define I2S_CLKCTRL_FSINV (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)
#define I2S_CLKCTRL_FSOUTINV_Pos 10 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
#define I2S_CLKCTRL_FSOUTINV (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
#define I2S_CLKCTRL_SCKSEL_Pos 11 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
#define I2S_CLKCTRL_SCKSEL (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_SCKOUTINV_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
#define I2S_CLKCTRL_SCKOUTINV (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
#define I2S_CLKCTRL_MCKSEL_Pos 13 /**< \brief (I2S_CLKCTRL) Master Clock Select */
#define I2S_CLKCTRL_MCKSEL (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKSEL_GCLK_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKEN_Pos 14 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
#define I2S_CLKCTRL_MCKEN (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)
#define I2S_CLKCTRL_MCKOUTINV_Pos 15 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
#define I2S_CLKCTRL_MCKOUTINV (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
#define I2S_CLKCTRL_MCKDIV_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
#define I2S_CLKCTRL_MCKDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos)
#define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
#define I2S_CLKCTRL_MCKOUTDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
#define I2S_CLKCTRL_MASK _U_(0x3F3FFFFF) /**< \brief (I2S_CLKCTRL) MASK Register */
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
#define I2S_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
#define I2S_INTENCLR_RXRDY0 (_U_(1) << I2S_INTENCLR_RXRDY0_Pos)
#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
#define I2S_INTENCLR_RXRDY1 (_U_(1) << I2S_INTENCLR_RXRDY1_Pos)
#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
#define I2S_INTENCLR_RXRDY_Msk (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)
#define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
#define I2S_INTENCLR_RXOR0 (_U_(1) << I2S_INTENCLR_RXOR0_Pos)
#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
#define I2S_INTENCLR_RXOR1 (_U_(1) << I2S_INTENCLR_RXOR1_Pos)
#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
#define I2S_INTENCLR_RXOR_Msk (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)
#define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
#define I2S_INTENCLR_TXRDY0 (_U_(1) << I2S_INTENCLR_TXRDY0_Pos)
#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
#define I2S_INTENCLR_TXRDY1 (_U_(1) << I2S_INTENCLR_TXRDY1_Pos)
#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
#define I2S_INTENCLR_TXRDY_Msk (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)
#define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
#define I2S_INTENCLR_TXUR0 (_U_(1) << I2S_INTENCLR_TXUR0_Pos)
#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
#define I2S_INTENCLR_TXUR1 (_U_(1) << I2S_INTENCLR_TXUR1_Pos)
#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
#define I2S_INTENCLR_TXUR_Msk (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)
#define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
#define I2S_INTENCLR_MASK _U_(0x3333) /**< \brief (I2S_INTENCLR) MASK Register */
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
#define I2S_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
#define I2S_INTENSET_RXRDY0 (_U_(1) << I2S_INTENSET_RXRDY0_Pos)
#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
#define I2S_INTENSET_RXRDY1 (_U_(1) << I2S_INTENSET_RXRDY1_Pos)
#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
#define I2S_INTENSET_RXRDY_Msk (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)
#define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
#define I2S_INTENSET_RXOR0 (_U_(1) << I2S_INTENSET_RXOR0_Pos)
#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
#define I2S_INTENSET_RXOR1 (_U_(1) << I2S_INTENSET_RXOR1_Pos)
#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
#define I2S_INTENSET_RXOR_Msk (_U_(0x3) << I2S_INTENSET_RXOR_Pos)
#define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
#define I2S_INTENSET_TXRDY0 (_U_(1) << I2S_INTENSET_TXRDY0_Pos)
#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
#define I2S_INTENSET_TXRDY1 (_U_(1) << I2S_INTENSET_TXRDY1_Pos)
#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
#define I2S_INTENSET_TXRDY_Msk (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)
#define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
#define I2S_INTENSET_TXUR0 (_U_(1) << I2S_INTENSET_TXUR0_Pos)
#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
#define I2S_INTENSET_TXUR1 (_U_(1) << I2S_INTENSET_TXUR1_Pos)
#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
#define I2S_INTENSET_TXUR_Msk (_U_(0x3) << I2S_INTENSET_TXUR_Pos)
#define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
#define I2S_INTENSET_MASK _U_(0x3333) /**< \brief (I2S_INTENSET) MASK Register */
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
__I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
__I uint16_t :2; /*!< bit: 2.. 3 Reserved */
__I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
__I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
__I uint16_t :2; /*!< bit: 6.. 7 Reserved */
__I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
__I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
__I uint16_t :2; /*!< bit: 10..11 Reserved */
__I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
__I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
__I uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
__I uint16_t :2; /*!< bit: 2.. 3 Reserved */
__I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
__I uint16_t :2; /*!< bit: 6.. 7 Reserved */
__I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
__I uint16_t :2; /*!< bit: 10..11 Reserved */
__I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
__I uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
#define I2S_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
#define I2S_INTFLAG_RXRDY0 (_U_(1) << I2S_INTFLAG_RXRDY0_Pos)
#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
#define I2S_INTFLAG_RXRDY1 (_U_(1) << I2S_INTFLAG_RXRDY1_Pos)
#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
#define I2S_INTFLAG_RXRDY_Msk (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)
#define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
#define I2S_INTFLAG_RXOR0 (_U_(1) << I2S_INTFLAG_RXOR0_Pos)
#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
#define I2S_INTFLAG_RXOR1 (_U_(1) << I2S_INTFLAG_RXOR1_Pos)
#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
#define I2S_INTFLAG_RXOR_Msk (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)
#define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
#define I2S_INTFLAG_TXRDY0 (_U_(1) << I2S_INTFLAG_TXRDY0_Pos)
#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
#define I2S_INTFLAG_TXRDY1 (_U_(1) << I2S_INTFLAG_TXRDY1_Pos)
#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
#define I2S_INTFLAG_TXRDY_Msk (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)
#define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
#define I2S_INTFLAG_TXUR0 (_U_(1) << I2S_INTFLAG_TXUR0_Pos)
#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
#define I2S_INTFLAG_TXUR1 (_U_(1) << I2S_INTFLAG_TXUR1_Pos)
#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
#define I2S_INTFLAG_TXUR_Msk (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)
#define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
#define I2S_INTFLAG_MASK _U_(0x3333) /**< \brief (I2S_INTFLAG) MASK Register */
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
uint16_t TXEN:1; /*!< bit: 4 Tx Serializer Enable Synchronization Status */
uint16_t RXEN:1; /*!< bit: 5 Rx Serializer Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXDATA:1; /*!< bit: 8 Tx Data Synchronization Status */
uint16_t RXDATA:1; /*!< bit: 9 Rx Data Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :2; /*!< bit: 0.. 1 Reserved */
uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
uint16_t :12; /*!< bit: 4..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
#define I2S_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
#define I2S_SYNCBUSY_SWRST (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)
#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
#define I2S_SYNCBUSY_ENABLE (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
#define I2S_SYNCBUSY_CKEN0 (_U_(1) << I2S_SYNCBUSY_CKEN0_Pos)
#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
#define I2S_SYNCBUSY_CKEN1 (_U_(1) << I2S_SYNCBUSY_CKEN1_Pos)
#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
#define I2S_SYNCBUSY_CKEN_Msk (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)
#define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
#define I2S_SYNCBUSY_TXEN_Pos 4 /**< \brief (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status */
#define I2S_SYNCBUSY_TXEN (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos)
#define I2S_SYNCBUSY_RXEN_Pos 5 /**< \brief (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status */
#define I2S_SYNCBUSY_RXEN (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos)
#define I2S_SYNCBUSY_TXDATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Tx Data Synchronization Status */
#define I2S_SYNCBUSY_TXDATA (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos)
#define I2S_SYNCBUSY_RXDATA_Pos 9 /**< \brief (I2S_SYNCBUSY) Rx Data Synchronization Status */
#define I2S_SYNCBUSY_RXDATA (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos)
#define I2S_SYNCBUSY_MASK _U_(0x033F) /**< \brief (I2S_SYNCBUSY) MASK Register */
/* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
uint32_t MONO:1; /*!< bit: 24 Mono Mode */
uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
uint32_t :6; /*!< bit: 26..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
uint32_t :8; /*!< bit: 24..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} I2S_TXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_TXCTRL_OFFSET 0x20 /**< \brief (I2S_TXCTRL offset) Tx Serializer Control */
#define I2S_TXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXCTRL reset_value) Tx Serializer Control */
#define I2S_TXCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_TXCTRL) Line Default Line when Slot Disabled */
#define I2S_TXCTRL_TXDEFAULT_Msk (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos)
#define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
#define I2S_TXCTRL_TXDEFAULT_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Output Default Value is 0 */
#define I2S_TXCTRL_TXDEFAULT_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Output Default Value is 1 */
#define I2S_TXCTRL_TXDEFAULT_HIZ_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Output Default Value is high impedance */
#define I2S_TXCTRL_TXDEFAULT_ZERO (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos)
#define I2S_TXCTRL_TXDEFAULT_ONE (I2S_TXCTRL_TXDEFAULT_ONE_Val << I2S_TXCTRL_TXDEFAULT_Pos)
#define I2S_TXCTRL_TXDEFAULT_HIZ (I2S_TXCTRL_TXDEFAULT_HIZ_Val << I2S_TXCTRL_TXDEFAULT_Pos)
#define I2S_TXCTRL_TXSAME_Pos 4 /**< \brief (I2S_TXCTRL) Transmit Data when Underrun */
#define I2S_TXCTRL_TXSAME (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos)
#define I2S_TXCTRL_TXSAME_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Zero data transmitted in case of underrun */
#define I2S_TXCTRL_TXSAME_SAME_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Last data transmitted in case of underrun */
#define I2S_TXCTRL_TXSAME_ZERO (I2S_TXCTRL_TXSAME_ZERO_Val << I2S_TXCTRL_TXSAME_Pos)
#define I2S_TXCTRL_TXSAME_SAME (I2S_TXCTRL_TXSAME_SAME_Val << I2S_TXCTRL_TXSAME_Pos)
#define I2S_TXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_TXCTRL) Data Slot Formatting Adjust */
#define I2S_TXCTRL_SLOTADJ (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos)
#define I2S_TXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in slot */
#define I2S_TXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in slot */
#define I2S_TXCTRL_SLOTADJ_RIGHT (I2S_TXCTRL_SLOTADJ_RIGHT_Val << I2S_TXCTRL_SLOTADJ_Pos)
#define I2S_TXCTRL_SLOTADJ_LEFT (I2S_TXCTRL_SLOTADJ_LEFT_Val << I2S_TXCTRL_SLOTADJ_Pos)
#define I2S_TXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_TXCTRL) Data Word Size */
#define I2S_TXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE(value) (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
#define I2S_TXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_TXCTRL) 32 bits */
#define I2S_TXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_TXCTRL) 24 bits */
#define I2S_TXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_TXCTRL) 20 bits */
#define I2S_TXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_TXCTRL) 18 bits */
#define I2S_TXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_TXCTRL) 16 bits */
#define I2S_TXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_TXCTRL) 16 bits compact stereo */
#define I2S_TXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_TXCTRL) 8 bits */
#define I2S_TXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_TXCTRL) 8 bits compact stereo */
#define I2S_TXCTRL_DATASIZE_32 (I2S_TXCTRL_DATASIZE_32_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_24 (I2S_TXCTRL_DATASIZE_24_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_20 (I2S_TXCTRL_DATASIZE_20_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_18 (I2S_TXCTRL_DATASIZE_18_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_16 (I2S_TXCTRL_DATASIZE_16_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_16C (I2S_TXCTRL_DATASIZE_16C_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_8 (I2S_TXCTRL_DATASIZE_8_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_8C (I2S_TXCTRL_DATASIZE_8C_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_TXCTRL) Data Word Formatting Adjust */
#define I2S_TXCTRL_WORDADJ (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos)
#define I2S_TXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Data is right adjusted in word */
#define I2S_TXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Data is left adjusted in word */
#define I2S_TXCTRL_WORDADJ_RIGHT (I2S_TXCTRL_WORDADJ_RIGHT_Val << I2S_TXCTRL_WORDADJ_Pos)
#define I2S_TXCTRL_WORDADJ_LEFT (I2S_TXCTRL_WORDADJ_LEFT_Val << I2S_TXCTRL_WORDADJ_Pos)
#define I2S_TXCTRL_EXTEND_Pos 13 /**< \brief (I2S_TXCTRL) Data Formatting Bit Extension */
#define I2S_TXCTRL_EXTEND_Msk (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_EXTEND(value) (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
#define I2S_TXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Extend with zeroes */
#define I2S_TXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Extend with ones */
#define I2S_TXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_TXCTRL) Extend with Most Significant Bit */
#define I2S_TXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_TXCTRL) Extend with Least Significant Bit */
#define I2S_TXCTRL_EXTEND_ZERO (I2S_TXCTRL_EXTEND_ZERO_Val << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_EXTEND_ONE (I2S_TXCTRL_EXTEND_ONE_Val << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_EXTEND_MSBIT (I2S_TXCTRL_EXTEND_MSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_EXTEND_LSBIT (I2S_TXCTRL_EXTEND_LSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_BITREV_Pos 15 /**< \brief (I2S_TXCTRL) Data Formatting Bit Reverse */
#define I2S_TXCTRL_BITREV (_U_(0x1) << I2S_TXCTRL_BITREV_Pos)
#define I2S_TXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
#define I2S_TXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */
#define I2S_TXCTRL_BITREV_MSBIT (I2S_TXCTRL_BITREV_MSBIT_Val << I2S_TXCTRL_BITREV_Pos)
#define I2S_TXCTRL_BITREV_LSBIT (I2S_TXCTRL_BITREV_LSBIT_Val << I2S_TXCTRL_BITREV_Pos)
#define I2S_TXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_TXCTRL) Slot 0 Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS0 (_U_(1) << I2S_TXCTRL_SLOTDIS0_Pos)
#define I2S_TXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_TXCTRL) Slot 1 Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS1 (_U_(1) << I2S_TXCTRL_SLOTDIS1_Pos)
#define I2S_TXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_TXCTRL) Slot 2 Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS2 (_U_(1) << I2S_TXCTRL_SLOTDIS2_Pos)
#define I2S_TXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_TXCTRL) Slot 3 Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS3 (_U_(1) << I2S_TXCTRL_SLOTDIS3_Pos)
#define I2S_TXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_TXCTRL) Slot 4 Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS4 (_U_(1) << I2S_TXCTRL_SLOTDIS4_Pos)
#define I2S_TXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_TXCTRL) Slot 5 Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS5 (_U_(1) << I2S_TXCTRL_SLOTDIS5_Pos)
#define I2S_TXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_TXCTRL) Slot 6 Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS6 (_U_(1) << I2S_TXCTRL_SLOTDIS6_Pos)
#define I2S_TXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_TXCTRL) Slot 7 Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS7 (_U_(1) << I2S_TXCTRL_SLOTDIS7_Pos)
#define I2S_TXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_TXCTRL) Slot x Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos)
#define I2S_TXCTRL_SLOTDIS(value) (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
#define I2S_TXCTRL_MONO_Pos 24 /**< \brief (I2S_TXCTRL) Mono Mode */
#define I2S_TXCTRL_MONO (_U_(0x1) << I2S_TXCTRL_MONO_Pos)
#define I2S_TXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Normal mode */
#define I2S_TXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_TXCTRL) Left channel data is duplicated to right channel */
#define I2S_TXCTRL_MONO_STEREO (I2S_TXCTRL_MONO_STEREO_Val << I2S_TXCTRL_MONO_Pos)
#define I2S_TXCTRL_MONO_MONO (I2S_TXCTRL_MONO_MONO_Val << I2S_TXCTRL_MONO_Pos)
#define I2S_TXCTRL_DMA_Pos 25 /**< \brief (I2S_TXCTRL) Single or Multiple DMA Channels */
#define I2S_TXCTRL_DMA (_U_(0x1) << I2S_TXCTRL_DMA_Pos)
#define I2S_TXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_TXCTRL) Single DMA channel */
#define I2S_TXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_TXCTRL) One DMA channel per data channel */
#define I2S_TXCTRL_DMA_SINGLE (I2S_TXCTRL_DMA_SINGLE_Val << I2S_TXCTRL_DMA_Pos)
#define I2S_TXCTRL_DMA_MULTIPLE (I2S_TXCTRL_DMA_MULTIPLE_Val << I2S_TXCTRL_DMA_Pos)
#define I2S_TXCTRL_MASK _U_(0x03FFF79C) /**< \brief (I2S_TXCTRL) MASK Register */
/* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
uint32_t :3; /*!< bit: 2.. 4 Reserved */
uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
uint32_t :1; /*!< bit: 6 Reserved */
uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
uint32_t MONO:1; /*!< bit: 24 Mono Mode */
uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
uint32_t :8; /*!< bit: 24..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} I2S_RXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_RXCTRL_OFFSET 0x24 /**< \brief (I2S_RXCTRL offset) Rx Serializer Control */
#define I2S_RXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXCTRL reset_value) Rx Serializer Control */
#define I2S_RXCTRL_SERMODE_Pos 0 /**< \brief (I2S_RXCTRL) Serializer Mode */
#define I2S_RXCTRL_SERMODE_Msk (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos)
#define I2S_RXCTRL_SERMODE(value) (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
#define I2S_RXCTRL_SERMODE_RX_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Receive */
#define I2S_RXCTRL_SERMODE_PDM2_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Receive one PDM data on each serial clock edge */
#define I2S_RXCTRL_SERMODE_RX (I2S_RXCTRL_SERMODE_RX_Val << I2S_RXCTRL_SERMODE_Pos)
#define I2S_RXCTRL_SERMODE_PDM2 (I2S_RXCTRL_SERMODE_PDM2_Val << I2S_RXCTRL_SERMODE_Pos)
#define I2S_RXCTRL_CLKSEL_Pos 5 /**< \brief (I2S_RXCTRL) Clock Unit Selection */
#define I2S_RXCTRL_CLKSEL (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos)
#define I2S_RXCTRL_CLKSEL_CLK0_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Use Clock Unit 0 */
#define I2S_RXCTRL_CLKSEL_CLK1_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Use Clock Unit 1 */
#define I2S_RXCTRL_CLKSEL_CLK0 (I2S_RXCTRL_CLKSEL_CLK0_Val << I2S_RXCTRL_CLKSEL_Pos)
#define I2S_RXCTRL_CLKSEL_CLK1 (I2S_RXCTRL_CLKSEL_CLK1_Val << I2S_RXCTRL_CLKSEL_Pos)
#define I2S_RXCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_RXCTRL) Data Slot Formatting Adjust */
#define I2S_RXCTRL_SLOTADJ (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos)
#define I2S_RXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in slot */
#define I2S_RXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in slot */
#define I2S_RXCTRL_SLOTADJ_RIGHT (I2S_RXCTRL_SLOTADJ_RIGHT_Val << I2S_RXCTRL_SLOTADJ_Pos)
#define I2S_RXCTRL_SLOTADJ_LEFT (I2S_RXCTRL_SLOTADJ_LEFT_Val << I2S_RXCTRL_SLOTADJ_Pos)
#define I2S_RXCTRL_DATASIZE_Pos 8 /**< \brief (I2S_RXCTRL) Data Word Size */
#define I2S_RXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE(value) (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
#define I2S_RXCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_RXCTRL) 32 bits */
#define I2S_RXCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_RXCTRL) 24 bits */
#define I2S_RXCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_RXCTRL) 20 bits */
#define I2S_RXCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_RXCTRL) 18 bits */
#define I2S_RXCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_RXCTRL) 16 bits */
#define I2S_RXCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_RXCTRL) 16 bits compact stereo */
#define I2S_RXCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_RXCTRL) 8 bits */
#define I2S_RXCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_RXCTRL) 8 bits compact stereo */
#define I2S_RXCTRL_DATASIZE_32 (I2S_RXCTRL_DATASIZE_32_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_24 (I2S_RXCTRL_DATASIZE_24_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_20 (I2S_RXCTRL_DATASIZE_20_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_18 (I2S_RXCTRL_DATASIZE_18_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_16 (I2S_RXCTRL_DATASIZE_16_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_16C (I2S_RXCTRL_DATASIZE_16C_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_8 (I2S_RXCTRL_DATASIZE_8_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_8C (I2S_RXCTRL_DATASIZE_8C_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_WORDADJ_Pos 12 /**< \brief (I2S_RXCTRL) Data Word Formatting Adjust */
#define I2S_RXCTRL_WORDADJ (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos)
#define I2S_RXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Data is right adjusted in word */
#define I2S_RXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Data is left adjusted in word */
#define I2S_RXCTRL_WORDADJ_RIGHT (I2S_RXCTRL_WORDADJ_RIGHT_Val << I2S_RXCTRL_WORDADJ_Pos)
#define I2S_RXCTRL_WORDADJ_LEFT (I2S_RXCTRL_WORDADJ_LEFT_Val << I2S_RXCTRL_WORDADJ_Pos)
#define I2S_RXCTRL_EXTEND_Pos 13 /**< \brief (I2S_RXCTRL) Data Formatting Bit Extension */
#define I2S_RXCTRL_EXTEND_Msk (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_EXTEND(value) (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
#define I2S_RXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Extend with zeroes */
#define I2S_RXCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Extend with ones */
#define I2S_RXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_RXCTRL) Extend with Most Significant Bit */
#define I2S_RXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_RXCTRL) Extend with Least Significant Bit */
#define I2S_RXCTRL_EXTEND_ZERO (I2S_RXCTRL_EXTEND_ZERO_Val << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_EXTEND_ONE (I2S_RXCTRL_EXTEND_ONE_Val << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_EXTEND_MSBIT (I2S_RXCTRL_EXTEND_MSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_EXTEND_LSBIT (I2S_RXCTRL_EXTEND_LSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_BITREV_Pos 15 /**< \brief (I2S_RXCTRL) Data Formatting Bit Reverse */
#define I2S_RXCTRL_BITREV (_U_(0x1) << I2S_RXCTRL_BITREV_Pos)
#define I2S_RXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
#define I2S_RXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */
#define I2S_RXCTRL_BITREV_MSBIT (I2S_RXCTRL_BITREV_MSBIT_Val << I2S_RXCTRL_BITREV_Pos)
#define I2S_RXCTRL_BITREV_LSBIT (I2S_RXCTRL_BITREV_LSBIT_Val << I2S_RXCTRL_BITREV_Pos)
#define I2S_RXCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_RXCTRL) Slot 0 Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS0 (_U_(1) << I2S_RXCTRL_SLOTDIS0_Pos)
#define I2S_RXCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_RXCTRL) Slot 1 Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS1 (_U_(1) << I2S_RXCTRL_SLOTDIS1_Pos)
#define I2S_RXCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_RXCTRL) Slot 2 Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS2 (_U_(1) << I2S_RXCTRL_SLOTDIS2_Pos)
#define I2S_RXCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_RXCTRL) Slot 3 Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS3 (_U_(1) << I2S_RXCTRL_SLOTDIS3_Pos)
#define I2S_RXCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_RXCTRL) Slot 4 Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS4 (_U_(1) << I2S_RXCTRL_SLOTDIS4_Pos)
#define I2S_RXCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_RXCTRL) Slot 5 Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS5 (_U_(1) << I2S_RXCTRL_SLOTDIS5_Pos)
#define I2S_RXCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_RXCTRL) Slot 6 Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS6 (_U_(1) << I2S_RXCTRL_SLOTDIS6_Pos)
#define I2S_RXCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_RXCTRL) Slot 7 Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS7 (_U_(1) << I2S_RXCTRL_SLOTDIS7_Pos)
#define I2S_RXCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_RXCTRL) Slot x Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos)
#define I2S_RXCTRL_SLOTDIS(value) (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
#define I2S_RXCTRL_MONO_Pos 24 /**< \brief (I2S_RXCTRL) Mono Mode */
#define I2S_RXCTRL_MONO (_U_(0x1) << I2S_RXCTRL_MONO_Pos)
#define I2S_RXCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Normal mode */
#define I2S_RXCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_RXCTRL) Left channel data is duplicated to right channel */
#define I2S_RXCTRL_MONO_STEREO (I2S_RXCTRL_MONO_STEREO_Val << I2S_RXCTRL_MONO_Pos)
#define I2S_RXCTRL_MONO_MONO (I2S_RXCTRL_MONO_MONO_Val << I2S_RXCTRL_MONO_Pos)
#define I2S_RXCTRL_DMA_Pos 25 /**< \brief (I2S_RXCTRL) Single or Multiple DMA Channels */
#define I2S_RXCTRL_DMA (_U_(0x1) << I2S_RXCTRL_DMA_Pos)
#define I2S_RXCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_RXCTRL) Single DMA channel */
#define I2S_RXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_RXCTRL) One DMA channel per data channel */
#define I2S_RXCTRL_DMA_SINGLE (I2S_RXCTRL_DMA_SINGLE_Val << I2S_RXCTRL_DMA_Pos)
#define I2S_RXCTRL_DMA_MULTIPLE (I2S_RXCTRL_DMA_MULTIPLE_Val << I2S_RXCTRL_DMA_Pos)
#define I2S_RXCTRL_RXLOOP_Pos 26 /**< \brief (I2S_RXCTRL) Loop-back Test Mode */
#define I2S_RXCTRL_RXLOOP (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos)
#define I2S_RXCTRL_MASK _U_(0x07FFF7A3) /**< \brief (I2S_RXCTRL) MASK Register */
/* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_TXDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_TXDATA_OFFSET 0x30 /**< \brief (I2S_TXDATA offset) Tx Data */
#define I2S_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_TXDATA reset_value) Tx Data */
#define I2S_TXDATA_DATA_Pos 0 /**< \brief (I2S_TXDATA) Sample Data */
#define I2S_TXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos)
#define I2S_TXDATA_DATA(value) (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
#define I2S_TXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_TXDATA) MASK Register */
/* -------- I2S_RXDATA : (I2S Offset: 0x34) (R/ 32) Rx Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_RXDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_RXDATA_OFFSET 0x34 /**< \brief (I2S_RXDATA offset) Rx Data */
#define I2S_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_RXDATA reset_value) Rx Data */
#define I2S_RXDATA_DATA_Pos 0 /**< \brief (I2S_RXDATA) Sample Data */
#define I2S_RXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos)
#define I2S_RXDATA_DATA(value) (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
#define I2S_RXDATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_RXDATA) MASK Register */
/** \brief I2S hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
RoReg8 Reserved1[0x3];
__IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
__IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
RoReg8 Reserved2[0x2];
__IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
RoReg8 Reserved3[0x2];
__IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x2];
__I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
RoReg8 Reserved5[0x6];
__IO I2S_TXCTRL_Type TXCTRL; /**< \brief Offset: 0x20 (R/W 32) Tx Serializer Control */
__IO I2S_RXCTRL_Type RXCTRL; /**< \brief Offset: 0x24 (R/W 32) Rx Serializer Control */
RoReg8 Reserved6[0x8];
__O I2S_TXDATA_Type TXDATA; /**< \brief Offset: 0x30 ( /W 32) Tx Data */
__I I2S_RXDATA_Type RXDATA; /**< \brief Offset: 0x34 (R/ 32) Rx Data */
} I2s;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_I2S_COMPONENT_ */

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/**
* \file
*
* \brief Component description for ICM
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_ICM_COMPONENT_
#define _SAMD51_ICM_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR ICM */
/* ========================================================================== */
/** \addtogroup SAMD51_ICM Integrity Check Monitor */
/*@{*/
#define ICM_U2010
#define REV_ICM 0x120
/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WBDIS:1; /*!< bit: 0 Write Back Disable */
uint32_t EOMDIS:1; /*!< bit: 1 End of Monitoring Disable */
uint32_t SLBDIS:1; /*!< bit: 2 Secondary List Branching Disable */
uint32_t :1; /*!< bit: 3 Reserved */
uint32_t BBC:4; /*!< bit: 4.. 7 Bus Burden Control */
uint32_t ASCD:1; /*!< bit: 8 Automatic Switch To Compare Digest */
uint32_t DUALBUFF:1; /*!< bit: 9 Dual Input Buffer */
uint32_t :2; /*!< bit: 10..11 Reserved */
uint32_t UIHASH:1; /*!< bit: 12 User Initial Hash Value */
uint32_t UALGO:3; /*!< bit: 13..15 User SHA Algorithm */
uint32_t HAPROT:6; /*!< bit: 16..21 Region Hash Area Protection */
uint32_t :2; /*!< bit: 22..23 Reserved */
uint32_t DAPROT:6; /*!< bit: 24..29 Region Descriptor Area Protection */
uint32_t :2; /*!< bit: 30..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_CFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_CFG_OFFSET 0x00 /**< \brief (ICM_CFG offset) Configuration */
#define ICM_CFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_CFG reset_value) Configuration */
#define ICM_CFG_WBDIS_Pos 0 /**< \brief (ICM_CFG) Write Back Disable */
#define ICM_CFG_WBDIS (_U_(0x1) << ICM_CFG_WBDIS_Pos)
#define ICM_CFG_EOMDIS_Pos 1 /**< \brief (ICM_CFG) End of Monitoring Disable */
#define ICM_CFG_EOMDIS (_U_(0x1) << ICM_CFG_EOMDIS_Pos)
#define ICM_CFG_SLBDIS_Pos 2 /**< \brief (ICM_CFG) Secondary List Branching Disable */
#define ICM_CFG_SLBDIS (_U_(0x1) << ICM_CFG_SLBDIS_Pos)
#define ICM_CFG_BBC_Pos 4 /**< \brief (ICM_CFG) Bus Burden Control */
#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos)
#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
#define ICM_CFG_ASCD_Pos 8 /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
#define ICM_CFG_ASCD (_U_(0x1) << ICM_CFG_ASCD_Pos)
#define ICM_CFG_DUALBUFF_Pos 9 /**< \brief (ICM_CFG) Dual Input Buffer */
#define ICM_CFG_DUALBUFF (_U_(0x1) << ICM_CFG_DUALBUFF_Pos)
#define ICM_CFG_UIHASH_Pos 12 /**< \brief (ICM_CFG) User Initial Hash Value */
#define ICM_CFG_UIHASH (_U_(0x1) << ICM_CFG_UIHASH_Pos)
#define ICM_CFG_UALGO_Pos 13 /**< \brief (ICM_CFG) User SHA Algorithm */
#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos)
#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< \brief (ICM_CFG) SHA1 Algorithm */
#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< \brief (ICM_CFG) SHA256 Algorithm */
#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< \brief (ICM_CFG) SHA224 Algorithm */
#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos)
#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos)
#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos)
#define ICM_CFG_HAPROT_Pos 16 /**< \brief (ICM_CFG) Region Hash Area Protection */
#define ICM_CFG_HAPROT_Msk (_U_(0x3F) << ICM_CFG_HAPROT_Pos)
#define ICM_CFG_HAPROT(value) (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))
#define ICM_CFG_DAPROT_Pos 24 /**< \brief (ICM_CFG) Region Descriptor Area Protection */
#define ICM_CFG_DAPROT_Msk (_U_(0x3F) << ICM_CFG_DAPROT_Pos)
#define ICM_CFG_DAPROT(value) (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))
#define ICM_CFG_MASK _U_(0x3F3FF3F7) /**< \brief (ICM_CFG) MASK Register */
/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /*!< bit: 0 ICM Enable */
uint32_t DISABLE:1; /*!< bit: 1 ICM Disable Register */
uint32_t SWRST:1; /*!< bit: 2 Software Reset */
uint32_t :1; /*!< bit: 3 Reserved */
uint32_t REHASH:4; /*!< bit: 4.. 7 Recompute Internal Hash */
uint32_t RMDIS:4; /*!< bit: 8..11 Region Monitoring Disable */
uint32_t RMEN:4; /*!< bit: 12..15 Region Monitoring Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_CTRL_OFFSET 0x04 /**< \brief (ICM_CTRL offset) Control */
#define ICM_CTRL_ENABLE_Pos 0 /**< \brief (ICM_CTRL) ICM Enable */
#define ICM_CTRL_ENABLE (_U_(0x1) << ICM_CTRL_ENABLE_Pos)
#define ICM_CTRL_DISABLE_Pos 1 /**< \brief (ICM_CTRL) ICM Disable Register */
#define ICM_CTRL_DISABLE (_U_(0x1) << ICM_CTRL_DISABLE_Pos)
#define ICM_CTRL_SWRST_Pos 2 /**< \brief (ICM_CTRL) Software Reset */
#define ICM_CTRL_SWRST (_U_(0x1) << ICM_CTRL_SWRST_Pos)
#define ICM_CTRL_REHASH_Pos 4 /**< \brief (ICM_CTRL) Recompute Internal Hash */
#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos)
#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
#define ICM_CTRL_RMDIS_Pos 8 /**< \brief (ICM_CTRL) Region Monitoring Disable */
#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos)
#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
#define ICM_CTRL_RMEN_Pos 12 /**< \brief (ICM_CTRL) Region Monitoring Enable */
#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos)
#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
#define ICM_CTRL_MASK _U_(0x0000FFF7) /**< \brief (ICM_CTRL) MASK Register */
/* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /*!< bit: 0 ICM Controller Enable Register */
uint32_t :7; /*!< bit: 1.. 7 Reserved */
uint32_t RAWRMDIS:4; /*!< bit: 8..11 RAW Region Monitoring Disabled Status */
uint32_t RMDIS:4; /*!< bit: 12..15 Region Monitoring Disabled Status */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_SR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_SR_OFFSET 0x08 /**< \brief (ICM_SR offset) Status */
#define ICM_SR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_SR reset_value) Status */
#define ICM_SR_ENABLE_Pos 0 /**< \brief (ICM_SR) ICM Controller Enable Register */
#define ICM_SR_ENABLE (_U_(0x1) << ICM_SR_ENABLE_Pos)
#define ICM_SR_RAWRMDIS_Pos 8 /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos)
#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
#define ICM_SR_RMDIS_Pos 12 /**< \brief (ICM_SR) Region Monitoring Disabled Status */
#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos)
#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
#define ICM_SR_MASK _U_(0x0000FF01) /**< \brief (ICM_SR) MASK Register */
/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Enable */
uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Enable */
uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Enable */
uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition detected Interrupt Enable */
uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Enable */
uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */
uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Enable */
uint32_t :7; /*!< bit: 25..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_IER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_IER_OFFSET 0x10 /**< \brief (ICM_IER offset) Interrupt Enable */
#define ICM_IER_RHC_Pos 0 /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos)
#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
#define ICM_IER_RDM_Pos 4 /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos)
#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
#define ICM_IER_RBE_Pos 8 /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos)
#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
#define ICM_IER_RWC_Pos 12 /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos)
#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
#define ICM_IER_REC_Pos 16 /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos)
#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
#define ICM_IER_RSU_Pos 20 /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos)
#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
#define ICM_IER_URAD_Pos 24 /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
#define ICM_IER_URAD (_U_(0x1) << ICM_IER_URAD_Pos)
#define ICM_IER_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IER) MASK Register */
/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Disable */
uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Disable */
uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Disable */
uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */
uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition detected Interrupt Disable */
uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */
uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Disable */
uint32_t :7; /*!< bit: 25..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_IDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_IDR_OFFSET 0x14 /**< \brief (ICM_IDR offset) Interrupt Disable */
#define ICM_IDR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IDR reset_value) Interrupt Disable */
#define ICM_IDR_RHC_Pos 0 /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos)
#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
#define ICM_IDR_RDM_Pos 4 /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos)
#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
#define ICM_IDR_RBE_Pos 8 /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos)
#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
#define ICM_IDR_RWC_Pos 12 /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos)
#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
#define ICM_IDR_REC_Pos 16 /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos)
#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
#define ICM_IDR_RSU_Pos 20 /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos)
#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
#define ICM_IDR_URAD_Pos 24 /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
#define ICM_IDR_URAD (_U_(0x1) << ICM_IDR_URAD_Pos)
#define ICM_IDR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IDR) MASK Register */
/* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Mask */
uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Mask */
uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Mask */
uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */
uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Mask */
uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Mask */
uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Mask */
uint32_t :7; /*!< bit: 25..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_IMR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_IMR_OFFSET 0x18 /**< \brief (ICM_IMR offset) Interrupt Mask */
#define ICM_IMR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IMR reset_value) Interrupt Mask */
#define ICM_IMR_RHC_Pos 0 /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos)
#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
#define ICM_IMR_RDM_Pos 4 /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos)
#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
#define ICM_IMR_RBE_Pos 8 /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos)
#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
#define ICM_IMR_RWC_Pos 12 /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos)
#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
#define ICM_IMR_REC_Pos 16 /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos)
#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
#define ICM_IMR_RSU_Pos 20 /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos)
#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
#define ICM_IMR_URAD_Pos 24 /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
#define ICM_IMR_URAD (_U_(0x1) << ICM_IMR_URAD_Pos)
#define ICM_IMR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IMR) MASK Register */
/* -------- ICM_ISR : (ICM Offset: 0x1C) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed */
uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch */
uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error */
uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected */
uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected */
uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Detected */
uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Status */
uint32_t :7; /*!< bit: 25..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_ISR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_ISR_OFFSET 0x1C /**< \brief (ICM_ISR offset) Interrupt Status */
#define ICM_ISR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_ISR reset_value) Interrupt Status */
#define ICM_ISR_RHC_Pos 0 /**< \brief (ICM_ISR) Region Hash Completed */
#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos)
#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
#define ICM_ISR_RDM_Pos 4 /**< \brief (ICM_ISR) Region Digest Mismatch */
#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos)
#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
#define ICM_ISR_RBE_Pos 8 /**< \brief (ICM_ISR) Region Bus Error */
#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos)
#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
#define ICM_ISR_RWC_Pos 12 /**< \brief (ICM_ISR) Region Wrap Condition Detected */
#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos)
#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
#define ICM_ISR_REC_Pos 16 /**< \brief (ICM_ISR) Region End bit Condition Detected */
#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos)
#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
#define ICM_ISR_RSU_Pos 20 /**< \brief (ICM_ISR) Region Status Updated Detected */
#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos)
#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
#define ICM_ISR_URAD_Pos 24 /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
#define ICM_ISR_URAD (_U_(0x1) << ICM_ISR_URAD_Pos)
#define ICM_ISR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_ISR) MASK Register */
/* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t URAT:3; /*!< bit: 0.. 2 Undefined Register Access Trace */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_UASR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_UASR_OFFSET 0x20 /**< \brief (ICM_UASR offset) Undefined Access Status */
#define ICM_UASR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UASR reset_value) Undefined Access Status */
#define ICM_UASR_URAT_Pos 0 /**< \brief (ICM_UASR) Undefined Register Access Trace */
#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos)
#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */
#define ICM_UASR_URAT_CFG_MODIFIED_Val _U_(0x1) /**< \brief (ICM_UASR) CFG modified during active monitoring */
#define ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2) /**< \brief (ICM_UASR) DSCR modified during active monitoring */
#define ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3) /**< \brief (ICM_UASR) HASH modified during active monitoring */
#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< \brief (ICM_UASR) Write-only register read access */
#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos)
#define ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos)
#define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos)
#define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos)
#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos)
#define ICM_UASR_MASK _U_(0x00000007) /**< \brief (ICM_UASR) MASK Register */
/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :6; /*!< bit: 0.. 5 Reserved */
uint32_t DASA:26; /*!< bit: 6..31 Descriptor Area Start Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_DSCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_DSCR_OFFSET 0x30 /**< \brief (ICM_DSCR offset) Region Descriptor Area Start Address */
#define ICM_DSCR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_DSCR reset_value) Region Descriptor Area Start Address */
#define ICM_DSCR_DASA_Pos 6 /**< \brief (ICM_DSCR) Descriptor Area Start Address */
#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos)
#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
#define ICM_DSCR_MASK _U_(0xFFFFFFC0) /**< \brief (ICM_DSCR) MASK Register */
/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :7; /*!< bit: 0.. 6 Reserved */
uint32_t HASA:25; /*!< bit: 7..31 Hash Area Start Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_HASH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_HASH_OFFSET 0x34 /**< \brief (ICM_HASH offset) Region Hash Area Start Address */
#define ICM_HASH_RESETVALUE _U_(0x00000000) /**< \brief (ICM_HASH reset_value) Region Hash Area Start Address */
#define ICM_HASH_HASA_Pos 7 /**< \brief (ICM_HASH) Hash Area Start Address */
#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos)
#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
#define ICM_HASH_MASK _U_(0xFFFFFF80) /**< \brief (ICM_HASH) MASK Register */
/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t VAL:32; /*!< bit: 0..31 Initial Hash Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_UIHVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_UIHVAL_OFFSET 0x38 /**< \brief (ICM_UIHVAL offset) User Initial Hash Value n */
#define ICM_UIHVAL_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UIHVAL reset_value) User Initial Hash Value n */
#define ICM_UIHVAL_VAL_Pos 0 /**< \brief (ICM_UIHVAL) Initial Hash Value */
#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos)
#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
#define ICM_UIHVAL_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_UIHVAL) MASK Register */
/* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} ICM_RADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_RADDR_OFFSET 0x00 /**< \brief (ICM_RADDR offset) Region Start Address */
#define ICM_RADDR_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RADDR) MASK Register */
/* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CDWBN:1; /*!< bit: 0 Compare Digest Write Back */
uint32_t WRAP:1; /*!< bit: 1 Region Wrap */
uint32_t EOM:1; /*!< bit: 2 End of Monitoring */
uint32_t :1; /*!< bit: 3 Reserved */
uint32_t RHIEN:1; /*!< bit: 4 Region Hash Interrupt Enable */
uint32_t DMIEN:1; /*!< bit: 5 Region Digest Mismatch Interrupt Enable */
uint32_t BEIEN:1; /*!< bit: 6 Region Bus Error Interrupt Enable */
uint32_t WCIEN:1; /*!< bit: 7 Region Wrap Condition Detected Interrupt Enable */
uint32_t ECIEN:1; /*!< bit: 8 Region End bit Condition detected Interrupt Enable */
uint32_t SUIEN:1; /*!< bit: 9 Region Status Updated Interrupt Enable */
uint32_t PROCDLY:1; /*!< bit: 10 SHA Processing Delay */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t ALGO:3; /*!< bit: 12..14 SHA Algorithm */
uint32_t :9; /*!< bit: 15..23 Reserved */
uint32_t MRPROT:6; /*!< bit: 24..29 Memory Region AHB Protection */
uint32_t :2; /*!< bit: 30..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_RCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_RCFG_OFFSET 0x04 /**< \brief (ICM_RCFG offset) Region Configuration */
#define ICM_RCFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_RCFG reset_value) Region Configuration */
#define ICM_RCFG_CDWBN_Pos 0 /**< \brief (ICM_RCFG) Compare Digest Write Back */
#define ICM_RCFG_CDWBN (_U_(0x1) << ICM_RCFG_CDWBN_Pos)
#define ICM_RCFG_CDWBN_WRBA_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_CDWBN_COMP_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos)
#define ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos)
#define ICM_RCFG_WRAP_Pos 1 /**< \brief (ICM_RCFG) Region Wrap */
#define ICM_RCFG_WRAP (_U_(0x1) << ICM_RCFG_WRAP_Pos)
#define ICM_RCFG_WRAP_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_WRAP_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos)
#define ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos)
#define ICM_RCFG_EOM_Pos 2 /**< \brief (ICM_RCFG) End of Monitoring */
#define ICM_RCFG_EOM (_U_(0x1) << ICM_RCFG_EOM_Pos)
#define ICM_RCFG_EOM_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_EOM_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos)
#define ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos)
#define ICM_RCFG_RHIEN_Pos 4 /**< \brief (ICM_RCFG) Region Hash Interrupt Enable */
#define ICM_RCFG_RHIEN (_U_(0x1) << ICM_RCFG_RHIEN_Pos)
#define ICM_RCFG_RHIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_RHIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos)
#define ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos)
#define ICM_RCFG_DMIEN_Pos 5 /**< \brief (ICM_RCFG) Region Digest Mismatch Interrupt Enable */
#define ICM_RCFG_DMIEN (_U_(0x1) << ICM_RCFG_DMIEN_Pos)
#define ICM_RCFG_DMIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_DMIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos)
#define ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos)
#define ICM_RCFG_BEIEN_Pos 6 /**< \brief (ICM_RCFG) Region Bus Error Interrupt Enable */
#define ICM_RCFG_BEIEN (_U_(0x1) << ICM_RCFG_BEIEN_Pos)
#define ICM_RCFG_BEIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_BEIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos)
#define ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos)
#define ICM_RCFG_WCIEN_Pos 7 /**< \brief (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable */
#define ICM_RCFG_WCIEN (_U_(0x1) << ICM_RCFG_WCIEN_Pos)
#define ICM_RCFG_WCIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_WCIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos)
#define ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos)
#define ICM_RCFG_ECIEN_Pos 8 /**< \brief (ICM_RCFG) Region End bit Condition detected Interrupt Enable */
#define ICM_RCFG_ECIEN (_U_(0x1) << ICM_RCFG_ECIEN_Pos)
#define ICM_RCFG_ECIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_ECIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos)
#define ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos)
#define ICM_RCFG_SUIEN_Pos 9 /**< \brief (ICM_RCFG) Region Status Updated Interrupt Enable */
#define ICM_RCFG_SUIEN (_U_(0x1) << ICM_RCFG_SUIEN_Pos)
#define ICM_RCFG_SUIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_SUIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos)
#define ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos)
#define ICM_RCFG_PROCDLY_Pos 10 /**< \brief (ICM_RCFG) SHA Processing Delay */
#define ICM_RCFG_PROCDLY (_U_(0x1) << ICM_RCFG_PROCDLY_Pos)
#define ICM_RCFG_PROCDLY_SHORT_Val _U_(0x0) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_PROCDLY_LONG_Val _U_(0x1) /**< \brief (ICM_RCFG) */
#define ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos)
#define ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos)
#define ICM_RCFG_ALGO_Pos 12 /**< \brief (ICM_RCFG) SHA Algorithm */
#define ICM_RCFG_ALGO_Msk (_U_(0x7) << ICM_RCFG_ALGO_Pos)
#define ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))
#define ICM_RCFG_MRPROT_Pos 24 /**< \brief (ICM_RCFG) Memory Region AHB Protection */
#define ICM_RCFG_MRPROT_Msk (_U_(0x3F) << ICM_RCFG_MRPROT_Pos)
#define ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))
#define ICM_RCFG_MASK _U_(0x3F0077F7) /**< \brief (ICM_RCFG) MASK Register */
/* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TRSIZE:16; /*!< bit: 0..15 Transfer Size */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ICM_RCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_RCTRL_OFFSET 0x08 /**< \brief (ICM_RCTRL offset) Region Control */
#define ICM_RCTRL_TRSIZE_Pos 0 /**< \brief (ICM_RCTRL) Transfer Size */
#define ICM_RCTRL_TRSIZE_Msk (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos)
#define ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))
#define ICM_RCTRL_MASK _U_(0x0000FFFF) /**< \brief (ICM_RCTRL) MASK Register */
/* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} ICM_RNEXT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ICM_RNEXT_OFFSET 0x0C /**< \brief (ICM_RNEXT offset) Region Next Address */
#define ICM_RNEXT_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RNEXT) MASK Register */
/** \brief ICM APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO ICM_CFG_Type CFG; /**< \brief Offset: 0x00 (R/W 32) Configuration */
__O ICM_CTRL_Type CTRL; /**< \brief Offset: 0x04 ( /W 32) Control */
__I ICM_SR_Type SR; /**< \brief Offset: 0x08 (R/ 32) Status */
RoReg8 Reserved1[0x4];
__O ICM_IER_Type IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */
__O ICM_IDR_Type IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */
__I ICM_IMR_Type IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask */
__I ICM_ISR_Type ISR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Status */
__I ICM_UASR_Type UASR; /**< \brief Offset: 0x20 (R/ 32) Undefined Access Status */
RoReg8 Reserved2[0xC];
__IO ICM_DSCR_Type DSCR; /**< \brief Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */
__IO ICM_HASH_Type HASH; /**< \brief Offset: 0x34 (R/W 32) Region Hash Area Start Address */
__O ICM_UIHVAL_Type UIHVAL[8]; /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Value n */
} Icm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief ICM Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO ICM_RADDR_Type RADDR; /**< \brief Offset: 0x00 (R/W 32) Region Start Address */
__IO ICM_RCFG_Type RCFG; /**< \brief Offset: 0x04 (R/W 32) Region Configuration */
__IO ICM_RCTRL_Type RCTRL; /**< \brief Offset: 0x08 (R/W 32) Region Control */
__IO ICM_RNEXT_Type RNEXT; /**< \brief Offset: 0x0C (R/W 32) Region Next Address */
} IcmDescriptor;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_ICM_DESCRIPTOR
/*@}*/
#endif /* _SAMD51_ICM_COMPONENT_ */

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/**
* \file
*
* \brief Component description for MCLK
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_MCLK_COMPONENT_
#define _SAMD51_MCLK_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR MCLK */
/* ========================================================================== */
/** \addtogroup SAMD51_MCLK Main Clock */
/*@{*/
#define MCLK_U2408
#define REV_MCLK 0x100
/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
#define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
#define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
#define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
#define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */
/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
#define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
#define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
#define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
#define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */
/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
#define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */
#define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
#define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */
/* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/ 8) HS Clock Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_HSDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_HSDIV_OFFSET 0x04 /**< \brief (MCLK_HSDIV offset) HS Clock Division */
#define MCLK_HSDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_HSDIV reset_value) HS Clock Division */
#define MCLK_HSDIV_DIV_Pos 0 /**< \brief (MCLK_HSDIV) CPU Clock Division Factor */
#define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
#define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
#define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_HSDIV) Divide by 1 */
#define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)
#define MCLK_HSDIV_MASK _U_(0xFF) /**< \brief (MCLK_HSDIV) MASK Register */
/* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_CPUDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_CPUDIV_OFFSET 0x05 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
#define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
#define MCLK_CPUDIV_DIV_Pos 0 /**< \brief (MCLK_CPUDIV) Low-Power Clock Division Factor */
#define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
#define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */
#define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */
#define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */
#define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */
#define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */
#define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */
#define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */
#define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */
#define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)
#define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */
/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */
uint32_t DSU_:1; /*!< bit: 4 DSU AHB Clock Mask */
uint32_t HMATRIX_:1; /*!< bit: 5 HMATRIX AHB Clock Mask */
uint32_t NVMCTRL_:1; /*!< bit: 6 NVMCTRL AHB Clock Mask */
uint32_t HSRAM_:1; /*!< bit: 7 HSRAM AHB Clock Mask */
uint32_t CMCC_:1; /*!< bit: 8 CMCC AHB Clock Mask */
uint32_t DMAC_:1; /*!< bit: 9 DMAC AHB Clock Mask */
uint32_t USB_:1; /*!< bit: 10 USB AHB Clock Mask */
uint32_t BKUPRAM_:1; /*!< bit: 11 BKUPRAM AHB Clock Mask */
uint32_t PAC_:1; /*!< bit: 12 PAC AHB Clock Mask */
uint32_t QSPI_:1; /*!< bit: 13 QSPI AHB Clock Mask */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t SDHC0_:1; /*!< bit: 15 SDHC0 AHB Clock Mask */
uint32_t SDHC1_:1; /*!< bit: 16 SDHC1 AHB Clock Mask */
uint32_t :2; /*!< bit: 17..18 Reserved */
uint32_t ICM_:1; /*!< bit: 19 ICM AHB Clock Mask */
uint32_t PUKCC_:1; /*!< bit: 20 PUKCC AHB Clock Mask */
uint32_t QSPI_2X_:1; /*!< bit: 21 QSPI_2X AHB Clock Mask */
uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit: 22 NVMCTRL_SMEEPROM AHB Clock Mask */
uint32_t NVMCTRL_CACHE_:1; /*!< bit: 23 NVMCTRL_CACHE AHB Clock Mask */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */
#define MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
#define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
#define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
#define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
#define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
#define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
#define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
#define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */
#define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
#define MCLK_AHBMASK_DSU_Pos 4 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
#define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
#define MCLK_AHBMASK_HMATRIX_Pos 5 /**< \brief (MCLK_AHBMASK) HMATRIX AHB Clock Mask */
#define MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
#define MCLK_AHBMASK_NVMCTRL_Pos 6 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
#define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
#define MCLK_AHBMASK_HSRAM_Pos 7 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
#define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
#define MCLK_AHBMASK_CMCC_Pos 8 /**< \brief (MCLK_AHBMASK) CMCC AHB Clock Mask */
#define MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
#define MCLK_AHBMASK_DMAC_Pos 9 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
#define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
#define MCLK_AHBMASK_USB_Pos 10 /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */
#define MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
#define MCLK_AHBMASK_BKUPRAM_Pos 11 /**< \brief (MCLK_AHBMASK) BKUPRAM AHB Clock Mask */
#define MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
#define MCLK_AHBMASK_PAC_Pos 12 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
#define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
#define MCLK_AHBMASK_QSPI_Pos 13 /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */
#define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
#define MCLK_AHBMASK_SDHC0_Pos 15 /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */
#define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
#define MCLK_AHBMASK_SDHC1_Pos 16 /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */
#define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
#define MCLK_AHBMASK_ICM_Pos 19 /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */
#define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
#define MCLK_AHBMASK_PUKCC_Pos 20 /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */
#define MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
#define MCLK_AHBMASK_QSPI_2X_Pos 21 /**< \brief (MCLK_AHBMASK) QSPI_2X AHB Clock Mask */
#define MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22 /**< \brief (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask */
#define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23 /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */
#define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
#define MCLK_AHBMASK_MASK _U_(0x00F9BFFF) /**< \brief (MCLK_AHBMASK) MASK Register */
/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */
uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */
uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */
uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */
uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */
uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */
uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */
uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */
uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */
uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */
uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Clock Enable */
uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Clock Enable */
uint32_t TC0_:1; /*!< bit: 14 TC0 APB Clock Enable */
uint32_t TC1_:1; /*!< bit: 15 TC1 APB Clock Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */
#define MCLK_APBAMASK_RESETVALUE _U_(0x000007FF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
#define MCLK_APBAMASK_PAC_Pos 0 /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */
#define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
#define MCLK_APBAMASK_PM_Pos 1 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
#define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
#define MCLK_APBAMASK_MCLK_Pos 2 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
#define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
#define MCLK_APBAMASK_RSTC_Pos 3 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
#define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
#define MCLK_APBAMASK_OSCCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
#define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
#define MCLK_APBAMASK_OSC32KCTRL_Pos 5 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
#define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
#define MCLK_APBAMASK_SUPC_Pos 6 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
#define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
#define MCLK_APBAMASK_GCLK_Pos 7 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
#define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
#define MCLK_APBAMASK_WDT_Pos 8 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
#define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
#define MCLK_APBAMASK_RTC_Pos 9 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
#define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
#define MCLK_APBAMASK_EIC_Pos 10 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
#define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
#define MCLK_APBAMASK_FREQM_Pos 11 /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */
#define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
#define MCLK_APBAMASK_SERCOM0_Pos 12 /**< \brief (MCLK_APBAMASK) SERCOM0 APB Clock Enable */
#define MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
#define MCLK_APBAMASK_SERCOM1_Pos 13 /**< \brief (MCLK_APBAMASK) SERCOM1 APB Clock Enable */
#define MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
#define MCLK_APBAMASK_TC0_Pos 14 /**< \brief (MCLK_APBAMASK) TC0 APB Clock Enable */
#define MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
#define MCLK_APBAMASK_TC1_Pos 15 /**< \brief (MCLK_APBAMASK) TC1 APB Clock Enable */
#define MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
#define MCLK_APBAMASK_MASK _U_(0x0000FFFF) /**< \brief (MCLK_APBAMASK) MASK Register */
/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t :1; /*!< bit: 3 Reserved */
uint32_t PORT_:1; /*!< bit: 4 PORT APB Clock Enable */
uint32_t :1; /*!< bit: 5 Reserved */
uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Clock Enable */
uint32_t :1; /*!< bit: 8 Reserved */
uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Clock Enable */
uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Clock Enable */
uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Clock Enable */
uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Clock Enable */
uint32_t TC2_:1; /*!< bit: 13 TC2 APB Clock Enable */
uint32_t TC3_:1; /*!< bit: 14 TC3 APB Clock Enable */
uint32_t TAL_:1; /*!< bit: 15 TAL APB Clock Enable */
uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Clock Enable */
uint32_t :15; /*!< bit: 17..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */
#define MCLK_APBBMASK_RESETVALUE _U_(0x00018056) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
#define MCLK_APBBMASK_USB_Pos 0 /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */
#define MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
#define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
#define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
#define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
#define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
#define MCLK_APBBMASK_PORT_Pos 4 /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */
#define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
#define MCLK_APBBMASK_HMATRIX_Pos 6 /**< \brief (MCLK_APBBMASK) HMATRIX APB Clock Enable */
#define MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
#define MCLK_APBBMASK_EVSYS_Pos 7 /**< \brief (MCLK_APBBMASK) EVSYS APB Clock Enable */
#define MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
#define MCLK_APBBMASK_SERCOM2_Pos 9 /**< \brief (MCLK_APBBMASK) SERCOM2 APB Clock Enable */
#define MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
#define MCLK_APBBMASK_SERCOM3_Pos 10 /**< \brief (MCLK_APBBMASK) SERCOM3 APB Clock Enable */
#define MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
#define MCLK_APBBMASK_TCC0_Pos 11 /**< \brief (MCLK_APBBMASK) TCC0 APB Clock Enable */
#define MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
#define MCLK_APBBMASK_TCC1_Pos 12 /**< \brief (MCLK_APBBMASK) TCC1 APB Clock Enable */
#define MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
#define MCLK_APBBMASK_TC2_Pos 13 /**< \brief (MCLK_APBBMASK) TC2 APB Clock Enable */
#define MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
#define MCLK_APBBMASK_TC3_Pos 14 /**< \brief (MCLK_APBBMASK) TC3 APB Clock Enable */
#define MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
#define MCLK_APBBMASK_TAL_Pos 15 /**< \brief (MCLK_APBBMASK) TAL APB Clock Enable */
#define MCLK_APBBMASK_TAL (_U_(0x1) << MCLK_APBBMASK_TAL_Pos)
#define MCLK_APBBMASK_RAMECC_Pos 16 /**< \brief (MCLK_APBBMASK) RAMECC APB Clock Enable */
#define MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
#define MCLK_APBBMASK_MASK _U_(0x0001FED7) /**< \brief (MCLK_APBBMASK) MASK Register */
/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :3; /*!< bit: 0.. 2 Reserved */
uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Clock Enable */
uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Clock Enable */
uint32_t TC4_:1; /*!< bit: 5 TC4 APB Clock Enable */
uint32_t TC5_:1; /*!< bit: 6 TC5 APB Clock Enable */
uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Clock Enable */
uint32_t AC_:1; /*!< bit: 8 AC APB Clock Enable */
uint32_t AES_:1; /*!< bit: 9 AES APB Clock Enable */
uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Clock Enable */
uint32_t ICM_:1; /*!< bit: 11 ICM APB Clock Enable */
uint32_t :1; /*!< bit: 12 Reserved */
uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Clock Enable */
uint32_t CCL_:1; /*!< bit: 14 CCL APB Clock Enable */
uint32_t :17; /*!< bit: 15..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */
#define MCLK_APBCMASK_RESETVALUE _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
#define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
#define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
#define MCLK_APBCMASK_TCC3_Pos 4 /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */
#define MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
#define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */
#define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
#define MCLK_APBCMASK_TC5_Pos 6 /**< \brief (MCLK_APBCMASK) TC5 APB Clock Enable */
#define MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
#define MCLK_APBCMASK_PDEC_Pos 7 /**< \brief (MCLK_APBCMASK) PDEC APB Clock Enable */
#define MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
#define MCLK_APBCMASK_AC_Pos 8 /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */
#define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
#define MCLK_APBCMASK_AES_Pos 9 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */
#define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
#define MCLK_APBCMASK_TRNG_Pos 10 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */
#define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
#define MCLK_APBCMASK_ICM_Pos 11 /**< \brief (MCLK_APBCMASK) ICM APB Clock Enable */
#define MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
#define MCLK_APBCMASK_QSPI_Pos 13 /**< \brief (MCLK_APBCMASK) QSPI APB Clock Enable */
#define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
#define MCLK_APBCMASK_CCL_Pos 14 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
#define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
#define MCLK_APBCMASK_MASK _U_(0x00006FF8) /**< \brief (MCLK_APBCMASK) MASK Register */
/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Clock Enable */
uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */
uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Clock Enable */
uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Clock Enable */
uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Clock Enable */
uint32_t TC6_:1; /*!< bit: 5 TC6 APB Clock Enable */
uint32_t TC7_:1; /*!< bit: 6 TC7 APB Clock Enable */
uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Clock Enable */
uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Clock Enable */
uint32_t DAC_:1; /*!< bit: 9 DAC APB Clock Enable */
uint32_t I2S_:1; /*!< bit: 10 I2S APB Clock Enable */
uint32_t PCC_:1; /*!< bit: 11 PCC APB Clock Enable */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_APBDMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */
#define MCLK_APBDMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */
#define MCLK_APBDMASK_SERCOM4_Pos 0 /**< \brief (MCLK_APBDMASK) SERCOM4 APB Clock Enable */
#define MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
#define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */
#define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
#define MCLK_APBDMASK_SERCOM6_Pos 2 /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */
#define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
#define MCLK_APBDMASK_SERCOM7_Pos 3 /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */
#define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
#define MCLK_APBDMASK_TCC4_Pos 4 /**< \brief (MCLK_APBDMASK) TCC4 APB Clock Enable */
#define MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
#define MCLK_APBDMASK_TC6_Pos 5 /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */
#define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
#define MCLK_APBDMASK_TC7_Pos 6 /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */
#define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
#define MCLK_APBDMASK_ADC0_Pos 7 /**< \brief (MCLK_APBDMASK) ADC0 APB Clock Enable */
#define MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
#define MCLK_APBDMASK_ADC1_Pos 8 /**< \brief (MCLK_APBDMASK) ADC1 APB Clock Enable */
#define MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
#define MCLK_APBDMASK_DAC_Pos 9 /**< \brief (MCLK_APBDMASK) DAC APB Clock Enable */
#define MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
#define MCLK_APBDMASK_I2S_Pos 10 /**< \brief (MCLK_APBDMASK) I2S APB Clock Enable */
#define MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
#define MCLK_APBDMASK_PCC_Pos 11 /**< \brief (MCLK_APBDMASK) PCC APB Clock Enable */
#define MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
#define MCLK_APBDMASK_MASK _U_(0x00000FFF) /**< \brief (MCLK_APBDMASK) MASK Register */
/** \brief MCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
RoReg8 Reserved1[0x1];
__IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */
__IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */
__IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */
__I MCLK_HSDIV_Type HSDIV; /**< \brief Offset: 0x04 (R/ 8) HS Clock Division */
__IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */
RoReg8 Reserved2[0xA];
__IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
__IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
__IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
__IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
__IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */
} Mclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_MCLK_COMPONENT_ */

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lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/nvmctrl.h Normal file
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/**
* \file
*
* \brief Component description for NVMCTRL
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_NVMCTRL_COMPONENT_
#define _SAMD51_NVMCTRL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR NVMCTRL */
/* ========================================================================== */
/** \addtogroup SAMD51_NVMCTRL Non-Volatile Memory Controller */
/*@{*/
#define NVMCTRL_U2409
#define REV_NVMCTRL 0x100
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :2; /*!< bit: 0.. 1 Reserved */
uint16_t AUTOWS:1; /*!< bit: 2 Auto Wait State Enable */
uint16_t SUSPEN:1; /*!< bit: 3 Suspend Enable */
uint16_t WMODE:2; /*!< bit: 4.. 5 Write Mode */
uint16_t PRM:2; /*!< bit: 6.. 7 Power Reduction Mode during Sleep */
uint16_t RWS:4; /*!< bit: 8..11 NVM Read Wait States */
uint16_t AHBNS0:1; /*!< bit: 12 Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */
uint16_t AHBNS1:1; /*!< bit: 13 Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */
uint16_t CACHEDIS0:1; /*!< bit: 14 AHB0 Cache Disable */
uint16_t CACHEDIS1:1; /*!< bit: 15 AHB1 Cache Disable */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
#define NVMCTRL_CTRLA_RESETVALUE _U_(0x0004) /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
#define NVMCTRL_CTRLA_AUTOWS_Pos 2 /**< \brief (NVMCTRL_CTRLA) Auto Wait State Enable */
#define NVMCTRL_CTRLA_AUTOWS (_U_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos)
#define NVMCTRL_CTRLA_SUSPEN_Pos 3 /**< \brief (NVMCTRL_CTRLA) Suspend Enable */
#define NVMCTRL_CTRLA_SUSPEN (_U_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos)
#define NVMCTRL_CTRLA_WMODE_Pos 4 /**< \brief (NVMCTRL_CTRLA) Write Mode */
#define NVMCTRL_CTRLA_WMODE_Msk (_U_(0x3) << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_WMODE(value) (NVMCTRL_CTRLA_WMODE_Msk & ((value) << NVMCTRL_CTRLA_WMODE_Pos))
#define NVMCTRL_CTRLA_WMODE_MAN_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLA) Manual Write */
#define NVMCTRL_CTRLA_WMODE_ADW_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLA) Automatic Double Word Write */
#define NVMCTRL_CTRLA_WMODE_AQW_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLA) Automatic Quad Word */
#define NVMCTRL_CTRLA_WMODE_AP_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLA) Automatic Page Write */
#define NVMCTRL_CTRLA_WMODE_MAN (NVMCTRL_CTRLA_WMODE_MAN_Val << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_WMODE_ADW (NVMCTRL_CTRLA_WMODE_ADW_Val << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_WMODE_AQW (NVMCTRL_CTRLA_WMODE_AQW_Val << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_WMODE_AP (NVMCTRL_CTRLA_WMODE_AP_Val << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_PRM_Pos 6 /**< \brief (NVMCTRL_CTRLA) Power Reduction Mode during Sleep */
#define NVMCTRL_CTRLA_PRM_Msk (_U_(0x3) << NVMCTRL_CTRLA_PRM_Pos)
#define NVMCTRL_CTRLA_PRM(value) (NVMCTRL_CTRLA_PRM_Msk & ((value) << NVMCTRL_CTRLA_PRM_Pos))
#define NVMCTRL_CTRLA_PRM_SEMIAUTO_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
#define NVMCTRL_CTRLA_PRM_FULLAUTO_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. */
#define NVMCTRL_CTRLA_PRM_MANUAL_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
#define NVMCTRL_CTRLA_PRM_SEMIAUTO (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
#define NVMCTRL_CTRLA_PRM_FULLAUTO (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
#define NVMCTRL_CTRLA_PRM_MANUAL (NVMCTRL_CTRLA_PRM_MANUAL_Val << NVMCTRL_CTRLA_PRM_Pos)
#define NVMCTRL_CTRLA_RWS_Pos 8 /**< \brief (NVMCTRL_CTRLA) NVM Read Wait States */
#define NVMCTRL_CTRLA_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLA_RWS_Pos)
#define NVMCTRL_CTRLA_RWS(value) (NVMCTRL_CTRLA_RWS_Msk & ((value) << NVMCTRL_CTRLA_RWS_Pos))
#define NVMCTRL_CTRLA_AHBNS0_Pos 12 /**< \brief (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */
#define NVMCTRL_CTRLA_AHBNS0 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos)
#define NVMCTRL_CTRLA_AHBNS1_Pos 13 /**< \brief (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */
#define NVMCTRL_CTRLA_AHBNS1 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos)
#define NVMCTRL_CTRLA_CACHEDIS0_Pos 14 /**< \brief (NVMCTRL_CTRLA) AHB0 Cache Disable */
#define NVMCTRL_CTRLA_CACHEDIS0 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos)
#define NVMCTRL_CTRLA_CACHEDIS1_Pos 15 /**< \brief (NVMCTRL_CTRLA) AHB1 Cache Disable */
#define NVMCTRL_CTRLA_CACHEDIS1 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos)
#define NVMCTRL_CTRLA_MASK _U_(0xFFFC) /**< \brief (NVMCTRL_CTRLA) MASK Register */
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
#define NVMCTRL_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
#define NVMCTRL_CTRLB_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLB) Command */
#define NVMCTRL_CTRLB_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD(value) (NVMCTRL_CTRLB_CMD_Msk & ((value) << NVMCTRL_CTRLB_CMD_Pos))
#define NVMCTRL_CTRLB_CMD_EP_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. */
#define NVMCTRL_CTRLB_CMD_EB_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page */
#define NVMCTRL_CTRLB_CMD_WP_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page */
#define NVMCTRL_CTRLB_CMD_WQW_Val _U_(0x4) /**< \brief (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. */
#define NVMCTRL_CTRLB_CMD_SWRST_Val _U_(0x10) /**< \brief (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers */
#define NVMCTRL_CTRLB_CMD_LR_Val _U_(0x11) /**< \brief (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. */
#define NVMCTRL_CTRLB_CMD_UR_Val _U_(0x12) /**< \brief (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
#define NVMCTRL_CTRLB_CMD_SPRM_Val _U_(0x13) /**< \brief (NVMCTRL_CTRLB) Sets the power reduction mode. */
#define NVMCTRL_CTRLB_CMD_CPRM_Val _U_(0x14) /**< \brief (NVMCTRL_CTRLB) Clears the power reduction mode. */
#define NVMCTRL_CTRLB_CMD_PBC_Val _U_(0x15) /**< \brief (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. */
#define NVMCTRL_CTRLB_CMD_SSB_Val _U_(0x16) /**< \brief (NVMCTRL_CTRLB) Set Security Bit */
#define NVMCTRL_CTRLB_CMD_BKSWRST_Val _U_(0x17) /**< \brief (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK */
#define NVMCTRL_CTRLB_CMD_CELCK_Val _U_(0x18) /**< \brief (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available */
#define NVMCTRL_CTRLB_CMD_CEULCK_Val _U_(0x19) /**< \brief (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available */
#define NVMCTRL_CTRLB_CMD_SBPDIS_Val _U_(0x1A) /**< \brief (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence */
#define NVMCTRL_CTRLB_CMD_CBPDIS_Val _U_(0x1B) /**< \brief (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded */
#define NVMCTRL_CTRLB_CMD_ASEES0_Val _U_(0x30) /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 */
#define NVMCTRL_CTRLB_CMD_ASEES1_Val _U_(0x31) /**< \brief (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 */
#define NVMCTRL_CTRLB_CMD_SEERALOC_Val _U_(0x32) /**< \brief (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm */
#define NVMCTRL_CTRLB_CMD_SEEFLUSH_Val _U_(0x33) /**< \brief (NVMCTRL_CTRLB) Flush SMEE data when in buffered mode */
#define NVMCTRL_CTRLB_CMD_LSEE_Val _U_(0x34) /**< \brief (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean */
#define NVMCTRL_CTRLB_CMD_USEE_Val _U_(0x35) /**< \brief (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data */
#define NVMCTRL_CTRLB_CMD_LSEER_Val _U_(0x36) /**< \brief (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) */
#define NVMCTRL_CTRLB_CMD_USEER_Val _U_(0x37) /**< \brief (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) */
#define NVMCTRL_CTRLB_CMD_EP (NVMCTRL_CTRLB_CMD_EP_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_EB (NVMCTRL_CTRLB_CMD_EB_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_WP (NVMCTRL_CTRLB_CMD_WP_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_WQW (NVMCTRL_CTRLB_CMD_WQW_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SWRST (NVMCTRL_CTRLB_CMD_SWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_LR (NVMCTRL_CTRLB_CMD_LR_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_UR (NVMCTRL_CTRLB_CMD_UR_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SPRM (NVMCTRL_CTRLB_CMD_SPRM_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_CPRM (NVMCTRL_CTRLB_CMD_CPRM_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_PBC (NVMCTRL_CTRLB_CMD_PBC_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SSB (NVMCTRL_CTRLB_CMD_SSB_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_BKSWRST (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_CELCK (NVMCTRL_CTRLB_CMD_CELCK_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_CEULCK (NVMCTRL_CTRLB_CMD_CEULCK_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SBPDIS (NVMCTRL_CTRLB_CMD_SBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_CBPDIS (NVMCTRL_CTRLB_CMD_CBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_ASEES0 (NVMCTRL_CTRLB_CMD_ASEES0_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_ASEES1 (NVMCTRL_CTRLB_CMD_ASEES1_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SEERALOC (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SEEFLUSH (NVMCTRL_CTRLB_CMD_SEEFLUSH_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_LSEE (NVMCTRL_CTRLB_CMD_LSEE_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_USEE (NVMCTRL_CTRLB_CMD_USEE_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_LSEER (NVMCTRL_CTRLB_CMD_LSEER_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_USEER (NVMCTRL_CTRLB_CMD_USEER_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLB) Command Execution */
#define NVMCTRL_CTRLB_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos)
#define NVMCTRL_CTRLB_CMDEX(value) (NVMCTRL_CTRLB_CMDEX_Msk & ((value) << NVMCTRL_CTRLB_CMDEX_Pos))
#define NVMCTRL_CTRLB_CMDEX_KEY_Val _U_(0xA5) /**< \brief (NVMCTRL_CTRLB) Execution Key */
#define NVMCTRL_CTRLB_CMDEX_KEY (NVMCTRL_CTRLB_CMDEX_KEY_Val << NVMCTRL_CTRLB_CMDEX_Pos)
#define NVMCTRL_CTRLB_MASK _U_(0xFF7F) /**< \brief (NVMCTRL_CTRLB) MASK Register */
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/ 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :12; /*!< bit: 19..30 Reserved */
uint32_t SEE:1; /*!< bit: 31 SmartEEPROM Supported */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
#define NVMCTRL_PARAM_RESETVALUE _U_(0x00060000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
#define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
#define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
#define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0) /**< \brief (NVMCTRL_PARAM) 8 bytes */
#define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1) /**< \brief (NVMCTRL_PARAM) 16 bytes */
#define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2) /**< \brief (NVMCTRL_PARAM) 32 bytes */
#define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3) /**< \brief (NVMCTRL_PARAM) 64 bytes */
#define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4) /**< \brief (NVMCTRL_PARAM) 128 bytes */
#define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5) /**< \brief (NVMCTRL_PARAM) 256 bytes */
#define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6) /**< \brief (NVMCTRL_PARAM) 512 bytes */
#define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7) /**< \brief (NVMCTRL_PARAM) 1024 bytes */
#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_SEE_Pos 31 /**< \brief (NVMCTRL_PARAM) SmartEEPROM Supported */
#define NVMCTRL_PARAM_SEE (_U_(0x1) << NVMCTRL_PARAM_SEE_Pos)
#define NVMCTRL_PARAM_MASK _U_(0x8007FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DONE:1; /*!< bit: 0 Command Done Interrupt Clear */
uint16_t ADDRE:1; /*!< bit: 1 Address Error */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Interrupt Clear */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Interrupt Clear */
uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error Interrupt Clear */
uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error Interrupt Clear */
uint16_t NVME:1; /*!< bit: 6 NVM Error Interrupt Clear */
uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Interrupt Clear */
uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full Interrupt Clear */
uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow Interrupt Clear */
uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed Interrupt Clear */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
#define NVMCTRL_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
#define NVMCTRL_INTENCLR_DONE_Pos 0 /**< \brief (NVMCTRL_INTENCLR) Command Done Interrupt Clear */
#define NVMCTRL_INTENCLR_DONE (_U_(0x1) << NVMCTRL_INTENCLR_DONE_Pos)
#define NVMCTRL_INTENCLR_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Address Error */
#define NVMCTRL_INTENCLR_ADDRE (_U_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos)
#define NVMCTRL_INTENCLR_PROGE_Pos 2 /**< \brief (NVMCTRL_INTENCLR) Programming Error Interrupt Clear */
#define NVMCTRL_INTENCLR_PROGE (_U_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos)
#define NVMCTRL_INTENCLR_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTENCLR) Lock Error Interrupt Clear */
#define NVMCTRL_INTENCLR_LOCKE (_U_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos)
#define NVMCTRL_INTENCLR_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear */
#define NVMCTRL_INTENCLR_ECCSE (_U_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos)
#define NVMCTRL_INTENCLR_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear */
#define NVMCTRL_INTENCLR_ECCDE (_U_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos)
#define NVMCTRL_INTENCLR_NVME_Pos 6 /**< \brief (NVMCTRL_INTENCLR) NVM Error Interrupt Clear */
#define NVMCTRL_INTENCLR_NVME (_U_(0x1) << NVMCTRL_INTENCLR_NVME_Pos)
#define NVMCTRL_INTENCLR_SUSP_Pos 7 /**< \brief (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear */
#define NVMCTRL_INTENCLR_SUSP (_U_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos)
#define NVMCTRL_INTENCLR_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear */
#define NVMCTRL_INTENCLR_SEESFULL (_U_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos)
#define NVMCTRL_INTENCLR_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear */
#define NVMCTRL_INTENCLR_SEESOVF (_U_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos)
#define NVMCTRL_INTENCLR_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear */
#define NVMCTRL_INTENCLR_SEEWRC (_U_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos)
#define NVMCTRL_INTENCLR_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTENCLR) MASK Register */
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DONE:1; /*!< bit: 0 Command Done Interrupt Enable */
uint16_t ADDRE:1; /*!< bit: 1 Address Error Interrupt Enable */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Interrupt Enable */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Interrupt Enable */
uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error Interrupt Enable */
uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error Interrupt Enable */
uint16_t NVME:1; /*!< bit: 6 NVM Error Interrupt Enable */
uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Interrupt Enable */
uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full Interrupt Enable */
uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow Interrupt Enable */
uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed Interrupt Enable */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTENSET_OFFSET 0x0E /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
#define NVMCTRL_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
#define NVMCTRL_INTENSET_DONE_Pos 0 /**< \brief (NVMCTRL_INTENSET) Command Done Interrupt Enable */
#define NVMCTRL_INTENSET_DONE (_U_(0x1) << NVMCTRL_INTENSET_DONE_Pos)
#define NVMCTRL_INTENSET_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTENSET) Address Error Interrupt Enable */
#define NVMCTRL_INTENSET_ADDRE (_U_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos)
#define NVMCTRL_INTENSET_PROGE_Pos 2 /**< \brief (NVMCTRL_INTENSET) Programming Error Interrupt Enable */
#define NVMCTRL_INTENSET_PROGE (_U_(0x1) << NVMCTRL_INTENSET_PROGE_Pos)
#define NVMCTRL_INTENSET_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTENSET) Lock Error Interrupt Enable */
#define NVMCTRL_INTENSET_LOCKE (_U_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos)
#define NVMCTRL_INTENSET_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable */
#define NVMCTRL_INTENSET_ECCSE (_U_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos)
#define NVMCTRL_INTENSET_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable */
#define NVMCTRL_INTENSET_ECCDE (_U_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos)
#define NVMCTRL_INTENSET_NVME_Pos 6 /**< \brief (NVMCTRL_INTENSET) NVM Error Interrupt Enable */
#define NVMCTRL_INTENSET_NVME (_U_(0x1) << NVMCTRL_INTENSET_NVME_Pos)
#define NVMCTRL_INTENSET_SUSP_Pos 7 /**< \brief (NVMCTRL_INTENSET) Suspended Write Or Erase Interrupt Enable */
#define NVMCTRL_INTENSET_SUSP (_U_(0x1) << NVMCTRL_INTENSET_SUSP_Pos)
#define NVMCTRL_INTENSET_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable */
#define NVMCTRL_INTENSET_SEESFULL (_U_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos)
#define NVMCTRL_INTENSET_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable */
#define NVMCTRL_INTENSET_SEESOVF (_U_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos)
#define NVMCTRL_INTENSET_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable */
#define NVMCTRL_INTENSET_SEEWRC (_U_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos)
#define NVMCTRL_INTENSET_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTENSET) MASK Register */
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint16_t DONE:1; /*!< bit: 0 Command Done */
__I uint16_t ADDRE:1; /*!< bit: 1 Address Error */
__I uint16_t PROGE:1; /*!< bit: 2 Programming Error */
__I uint16_t LOCKE:1; /*!< bit: 3 Lock Error */
__I uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error */
__I uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error */
__I uint16_t NVME:1; /*!< bit: 6 NVM Error */
__I uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Operation */
__I uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full */
__I uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow */
__I uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed */
__I uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTFLAG_OFFSET 0x10 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
#define NVMCTRL_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define NVMCTRL_INTFLAG_DONE_Pos 0 /**< \brief (NVMCTRL_INTFLAG) Command Done */
#define NVMCTRL_INTFLAG_DONE (_U_(0x1) << NVMCTRL_INTFLAG_DONE_Pos)
#define NVMCTRL_INTFLAG_ADDRE_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Address Error */
#define NVMCTRL_INTFLAG_ADDRE (_U_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos)
#define NVMCTRL_INTFLAG_PROGE_Pos 2 /**< \brief (NVMCTRL_INTFLAG) Programming Error */
#define NVMCTRL_INTFLAG_PROGE (_U_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos)
#define NVMCTRL_INTFLAG_LOCKE_Pos 3 /**< \brief (NVMCTRL_INTFLAG) Lock Error */
#define NVMCTRL_INTFLAG_LOCKE (_U_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos)
#define NVMCTRL_INTFLAG_ECCSE_Pos 4 /**< \brief (NVMCTRL_INTFLAG) ECC Single Error */
#define NVMCTRL_INTFLAG_ECCSE (_U_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos)
#define NVMCTRL_INTFLAG_ECCDE_Pos 5 /**< \brief (NVMCTRL_INTFLAG) ECC Dual Error */
#define NVMCTRL_INTFLAG_ECCDE (_U_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos)
#define NVMCTRL_INTFLAG_NVME_Pos 6 /**< \brief (NVMCTRL_INTFLAG) NVM Error */
#define NVMCTRL_INTFLAG_NVME (_U_(0x1) << NVMCTRL_INTFLAG_NVME_Pos)
#define NVMCTRL_INTFLAG_SUSP_Pos 7 /**< \brief (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation */
#define NVMCTRL_INTFLAG_SUSP (_U_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos)
#define NVMCTRL_INTFLAG_SEESFULL_Pos 8 /**< \brief (NVMCTRL_INTFLAG) Active SEES Full */
#define NVMCTRL_INTFLAG_SEESFULL (_U_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos)
#define NVMCTRL_INTFLAG_SEESOVF_Pos 9 /**< \brief (NVMCTRL_INTFLAG) Active SEES Overflow */
#define NVMCTRL_INTFLAG_SEESOVF (_U_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos)
#define NVMCTRL_INTFLAG_SEEWRC_Pos 10 /**< \brief (NVMCTRL_INTFLAG) SEE Write Completed */
#define NVMCTRL_INTFLAG_SEEWRC (_U_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos)
#define NVMCTRL_INTFLAG_MASK _U_(0x07FF) /**< \brief (NVMCTRL_INTFLAG) MASK Register */
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) (R/ 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t READY:1; /*!< bit: 0 Ready to accept a command */
uint16_t PRM:1; /*!< bit: 1 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 2 NVM Page Buffer Active Loading */
uint16_t SUSP:1; /*!< bit: 3 NVM Write Or Erase Operation Is Suspended */
uint16_t AFIRST:1; /*!< bit: 4 BANKA First */
uint16_t BPDIS:1; /*!< bit: 5 Boot Loader Protection Disable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t BOOTPROT:4; /*!< bit: 8..11 Boot Loader Protection Size */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_STATUS_OFFSET 0x12 /**< \brief (NVMCTRL_STATUS offset) Status */
#define NVMCTRL_STATUS_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_STATUS reset_value) Status */
#define NVMCTRL_STATUS_READY_Pos 0 /**< \brief (NVMCTRL_STATUS) Ready to accept a command */
#define NVMCTRL_STATUS_READY (_U_(0x1) << NVMCTRL_STATUS_READY_Pos)
#define NVMCTRL_STATUS_PRM_Pos 1 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
#define NVMCTRL_STATUS_PRM (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos)
#define NVMCTRL_STATUS_LOAD_Pos 2 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
#define NVMCTRL_STATUS_LOAD (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos)
#define NVMCTRL_STATUS_SUSP_Pos 3 /**< \brief (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended */
#define NVMCTRL_STATUS_SUSP (_U_(0x1) << NVMCTRL_STATUS_SUSP_Pos)
#define NVMCTRL_STATUS_AFIRST_Pos 4 /**< \brief (NVMCTRL_STATUS) BANKA First */
#define NVMCTRL_STATUS_AFIRST (_U_(0x1) << NVMCTRL_STATUS_AFIRST_Pos)
#define NVMCTRL_STATUS_BPDIS_Pos 5 /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Disable */
#define NVMCTRL_STATUS_BPDIS (_U_(0x1) << NVMCTRL_STATUS_BPDIS_Pos)
#define NVMCTRL_STATUS_BOOTPROT_Pos 8 /**< \brief (NVMCTRL_STATUS) Boot Loader Protection Size */
#define NVMCTRL_STATUS_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos)
#define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & ((value) << NVMCTRL_STATUS_BOOTPROT_Pos))
#define NVMCTRL_STATUS_MASK _U_(0x0F3F) /**< \brief (NVMCTRL_STATUS) MASK Register */
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:24; /*!< bit: 0..23 NVM Address */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_ADDR_OFFSET 0x14 /**< \brief (NVMCTRL_ADDR offset) Address */
#define NVMCTRL_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */
#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
#define NVMCTRL_ADDR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos)
#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
#define NVMCTRL_ADDR_MASK _U_(0x00FFFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */
/* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) (R/ 32) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RUNLOCK:32; /*!< bit: 0..31 Region Un-Lock Bits */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_RUNLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_RUNLOCK_OFFSET 0x18 /**< \brief (NVMCTRL_RUNLOCK offset) Lock Section */
#define NVMCTRL_RUNLOCK_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_RUNLOCK reset_value) Lock Section */
#define NVMCTRL_RUNLOCK_RUNLOCK_Pos 0 /**< \brief (NVMCTRL_RUNLOCK) Region Un-Lock Bits */
#define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_U_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos)
#define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & ((value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos))
#define NVMCTRL_RUNLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_RUNLOCK) MASK Register */
/* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) (R/ 32) Page Buffer Load Data x -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Page Buffer Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PBLDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_PBLDATA_OFFSET 0x1C /**< \brief (NVMCTRL_PBLDATA offset) Page Buffer Load Data x */
#define NVMCTRL_PBLDATA_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA reset_value) Page Buffer Load Data x */
#define NVMCTRL_PBLDATA_DATA_Pos 0 /**< \brief (NVMCTRL_PBLDATA) Page Buffer Data */
#define NVMCTRL_PBLDATA_DATA_Msk (_U_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos)
#define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & ((value) << NVMCTRL_PBLDATA_DATA_Pos))
#define NVMCTRL_PBLDATA_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA) MASK Register */
/* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) (R/ 32) ECC Error Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:24; /*!< bit: 0..23 Error Address */
uint32_t :4; /*!< bit: 24..27 Reserved */
uint32_t TYPEL:2; /*!< bit: 28..29 Low Double-Word Error Type */
uint32_t TYPEH:2; /*!< bit: 30..31 High Double-Word Error Type */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ECCERR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_ECCERR_OFFSET 0x24 /**< \brief (NVMCTRL_ECCERR offset) ECC Error Status Register */
#define NVMCTRL_ECCERR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ECCERR reset_value) ECC Error Status Register */
#define NVMCTRL_ECCERR_ADDR_Pos 0 /**< \brief (NVMCTRL_ECCERR) Error Address */
#define NVMCTRL_ECCERR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos)
#define NVMCTRL_ECCERR_ADDR(value) (NVMCTRL_ECCERR_ADDR_Msk & ((value) << NVMCTRL_ECCERR_ADDR_Pos))
#define NVMCTRL_ECCERR_TYPEL_Pos 28 /**< \brief (NVMCTRL_ECCERR) Low Double-Word Error Type */
#define NVMCTRL_ECCERR_TYPEL_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos)
#define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & ((value) << NVMCTRL_ECCERR_TYPEL_Pos))
#define NVMCTRL_ECCERR_TYPEL_NONE_Val _U_(0x0) /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */
#define NVMCTRL_ECCERR_TYPEL_SINGLE_Val _U_(0x1) /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
#define NVMCTRL_ECCERR_TYPEL_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
#define NVMCTRL_ECCERR_TYPEL_NONE (NVMCTRL_ECCERR_TYPEL_NONE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
#define NVMCTRL_ECCERR_TYPEL_SINGLE (NVMCTRL_ECCERR_TYPEL_SINGLE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
#define NVMCTRL_ECCERR_TYPEL_DUAL (NVMCTRL_ECCERR_TYPEL_DUAL_Val << NVMCTRL_ECCERR_TYPEL_Pos)
#define NVMCTRL_ECCERR_TYPEH_Pos 30 /**< \brief (NVMCTRL_ECCERR) High Double-Word Error Type */
#define NVMCTRL_ECCERR_TYPEH_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos)
#define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & ((value) << NVMCTRL_ECCERR_TYPEH_Pos))
#define NVMCTRL_ECCERR_TYPEH_NONE_Val _U_(0x0) /**< \brief (NVMCTRL_ECCERR) No Error Detected Since Last Read */
#define NVMCTRL_ECCERR_TYPEH_SINGLE_Val _U_(0x1) /**< \brief (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
#define NVMCTRL_ECCERR_TYPEH_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
#define NVMCTRL_ECCERR_TYPEH_NONE (NVMCTRL_ECCERR_TYPEH_NONE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
#define NVMCTRL_ECCERR_TYPEH_SINGLE (NVMCTRL_ECCERR_TYPEH_SINGLE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
#define NVMCTRL_ECCERR_TYPEH_DUAL (NVMCTRL_ECCERR_TYPEH_DUAL_Val << NVMCTRL_ECCERR_TYPEH_Pos)
#define NVMCTRL_ECCERR_MASK _U_(0xF0FFFFFF) /**< \brief (NVMCTRL_ECCERR) MASK Register */
/* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ECCDIS:1; /*!< bit: 0 Debugger ECC Read Disable */
uint8_t ECCELOG:1; /*!< bit: 1 Debugger ECC Error Tracking Mode */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_DBGCTRL_OFFSET 0x28 /**< \brief (NVMCTRL_DBGCTRL offset) Debug Control */
#define NVMCTRL_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_DBGCTRL reset_value) Debug Control */
#define NVMCTRL_DBGCTRL_ECCDIS_Pos 0 /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Read Disable */
#define NVMCTRL_DBGCTRL_ECCDIS (_U_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos)
#define NVMCTRL_DBGCTRL_ECCELOG_Pos 1 /**< \brief (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode */
#define NVMCTRL_DBGCTRL_ECCELOG (_U_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos)
#define NVMCTRL_DBGCTRL_MASK _U_(0x03) /**< \brief (NVMCTRL_DBGCTRL) MASK Register */
/* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W 8) SmartEEPROM Configuration Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WMODE:1; /*!< bit: 0 Write Mode */
uint8_t APRDIS:1; /*!< bit: 1 Automatic Page Reallocation Disable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_SEECFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_SEECFG_OFFSET 0x2A /**< \brief (NVMCTRL_SEECFG offset) SmartEEPROM Configuration Register */
#define NVMCTRL_SEECFG_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_SEECFG reset_value) SmartEEPROM Configuration Register */
#define NVMCTRL_SEECFG_WMODE_Pos 0 /**< \brief (NVMCTRL_SEECFG) Write Mode */
#define NVMCTRL_SEECFG_WMODE (_U_(0x1) << NVMCTRL_SEECFG_WMODE_Pos)
#define NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _U_(0x0) /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer */
#define NVMCTRL_SEECFG_WMODE_BUFFERED_Val _U_(0x1) /**< \brief (NVMCTRL_SEECFG) A NVM write command is issued when a write to a new page is requested */
#define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
#define NVMCTRL_SEECFG_WMODE_BUFFERED (NVMCTRL_SEECFG_WMODE_BUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
#define NVMCTRL_SEECFG_APRDIS_Pos 1 /**< \brief (NVMCTRL_SEECFG) Automatic Page Reallocation Disable */
#define NVMCTRL_SEECFG_APRDIS (_U_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos)
#define NVMCTRL_SEECFG_MASK _U_(0x03) /**< \brief (NVMCTRL_SEECFG) MASK Register */
/* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) (R/ 32) SmartEEPROM Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ASEES:1; /*!< bit: 0 Active SmartEEPROM Sector */
uint32_t LOAD:1; /*!< bit: 1 Page Buffer Loaded */
uint32_t BUSY:1; /*!< bit: 2 Busy */
uint32_t LOCK:1; /*!< bit: 3 SmartEEPROM Write Access Is Locked */
uint32_t RLOCK:1; /*!< bit: 4 SmartEEPROM Write Access To Register Address Space Is Locked */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t SBLK:4; /*!< bit: 8..11 Blocks Number In a Sector */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t PSZ:3; /*!< bit: 16..18 SmartEEPROM Page Size */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_SEESTAT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_SEESTAT_OFFSET 0x2C /**< \brief (NVMCTRL_SEESTAT offset) SmartEEPROM Status Register */
#define NVMCTRL_SEESTAT_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_SEESTAT reset_value) SmartEEPROM Status Register */
#define NVMCTRL_SEESTAT_ASEES_Pos 0 /**< \brief (NVMCTRL_SEESTAT) Active SmartEEPROM Sector */
#define NVMCTRL_SEESTAT_ASEES (_U_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos)
#define NVMCTRL_SEESTAT_LOAD_Pos 1 /**< \brief (NVMCTRL_SEESTAT) Page Buffer Loaded */
#define NVMCTRL_SEESTAT_LOAD (_U_(0x1) << NVMCTRL_SEESTAT_LOAD_Pos)
#define NVMCTRL_SEESTAT_BUSY_Pos 2 /**< \brief (NVMCTRL_SEESTAT) Busy */
#define NVMCTRL_SEESTAT_BUSY (_U_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos)
#define NVMCTRL_SEESTAT_LOCK_Pos 3 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked */
#define NVMCTRL_SEESTAT_LOCK (_U_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos)
#define NVMCTRL_SEESTAT_RLOCK_Pos 4 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked */
#define NVMCTRL_SEESTAT_RLOCK (_U_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos)
#define NVMCTRL_SEESTAT_SBLK_Pos 8 /**< \brief (NVMCTRL_SEESTAT) Blocks Number In a Sector */
#define NVMCTRL_SEESTAT_SBLK_Msk (_U_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos)
#define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & ((value) << NVMCTRL_SEESTAT_SBLK_Pos))
#define NVMCTRL_SEESTAT_PSZ_Pos 16 /**< \brief (NVMCTRL_SEESTAT) SmartEEPROM Page Size */
#define NVMCTRL_SEESTAT_PSZ_Msk (_U_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos)
#define NVMCTRL_SEESTAT_PSZ(value) (NVMCTRL_SEESTAT_PSZ_Msk & ((value) << NVMCTRL_SEESTAT_PSZ_Pos))
#define NVMCTRL_SEESTAT_MASK _U_(0x00070F1F) /**< \brief (NVMCTRL_SEESTAT) MASK Register */
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__O NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 ( /W 16) Control B */
RoReg8 Reserved2[0x2];
__I NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/ 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x0E (R/W 16) Interrupt Enable Set */
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear */
__I NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x12 (R/ 16) Status */
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) Address */
__I NVMCTRL_RUNLOCK_Type RUNLOCK; /**< \brief Offset: 0x18 (R/ 32) Lock Section */
__I NVMCTRL_PBLDATA_Type PBLDATA[2]; /**< \brief Offset: 0x1C (R/ 32) Page Buffer Load Data x */
__I NVMCTRL_ECCERR_Type ECCERR; /**< \brief Offset: 0x24 (R/ 32) ECC Error Status Register */
__IO NVMCTRL_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x28 (R/W 8) Debug Control */
RoReg8 Reserved3[0x1];
__IO NVMCTRL_SEECFG_Type SEECFG; /**< \brief Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register */
RoReg8 Reserved4[0x1];
__I NVMCTRL_SEESTAT_Type SEESTAT; /**< \brief Offset: 0x2C (R/ 32) SmartEEPROM Status Register */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CB
#define SECTION_NVMCTRL_CBW0
#define SECTION_NVMCTRL_CBW1
#define SECTION_NVMCTRL_CBW2
#define SECTION_NVMCTRL_CBW3
#define SECTION_NVMCTRL_CBW4
#define SECTION_NVMCTRL_CBW5
#define SECTION_NVMCTRL_CBW6
#define SECTION_NVMCTRL_CBW7
#define SECTION_NVMCTRL_FS
#define SECTION_NVMCTRL_GB
#define SECTION_NVMCTRL_SW0
#define SECTION_NVMCTRL_SW1
#define SECTION_NVMCTRL_SW2
#define SECTION_NVMCTRL_SW3
#define SECTION_NVMCTRL_SW4
#define SECTION_NVMCTRL_SW5
#define SECTION_NVMCTRL_SW6
#define SECTION_NVMCTRL_SW7
#define SECTION_NVMCTRL_TEMP_LOG
#define SECTION_NVMCTRL_TEMP_LOG_W0
#define SECTION_NVMCTRL_TEMP_LOG_W1
#define SECTION_NVMCTRL_TEMP_LOG_W2
#define SECTION_NVMCTRL_TEMP_LOG_W3
#define SECTION_NVMCTRL_TEMP_LOG_W4
#define SECTION_NVMCTRL_TEMP_LOG_W5
#define SECTION_NVMCTRL_TEMP_LOG_W6
#define SECTION_NVMCTRL_TEMP_LOG_W7
#define SECTION_NVMCTRL_TLATCH
#define SECTION_NVMCTRL_USER
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
/* ************************************************************************** */
/** \addtogroup fuses_api Peripheral Software API */
/*@{*/
#define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0
#define AC_FUSES_BIAS0_Pos 0 /**< \brief (NVMCTRL_SW0) PAIR0 Bias Calibration */
#define AC_FUSES_BIAS0_Msk (_U_(0x3) << AC_FUSES_BIAS0_Pos)
#define AC_FUSES_BIAS0(value) (AC_FUSES_BIAS0_Msk & ((value) << AC_FUSES_BIAS0_Pos))
#define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
#define ADC0_FUSES_BIASCOMP_Pos 2 /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */
#define ADC0_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos)
#define ADC0_FUSES_BIASCOMP(value) (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos))
#define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0
#define ADC0_FUSES_BIASR2R_Pos 8 /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */
#define ADC0_FUSES_BIASR2R_Msk (_U_(0x7) << ADC0_FUSES_BIASR2R_Pos)
#define ADC0_FUSES_BIASR2R(value) (ADC0_FUSES_BIASR2R_Msk & ((value) << ADC0_FUSES_BIASR2R_Pos))
#define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
#define ADC0_FUSES_BIASREFBUF_Pos 5 /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */
#define ADC0_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos)
#define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos))
#define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
#define ADC1_FUSES_BIASCOMP_Pos 16 /**< \brief (NVMCTRL_SW0) ADC Comparator Scaling */
#define ADC1_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos)
#define ADC1_FUSES_BIASCOMP(value) (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos))
#define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0
#define ADC1_FUSES_BIASR2R_Pos 22 /**< \brief (NVMCTRL_SW0) ADC Bias R2R ampli scaling */
#define ADC1_FUSES_BIASR2R_Msk (_U_(0x7) << ADC1_FUSES_BIASR2R_Pos)
#define ADC1_FUSES_BIASR2R(value) (ADC1_FUSES_BIASR2R_Msk & ((value) << ADC1_FUSES_BIASR2R_Pos))
#define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
#define ADC1_FUSES_BIASREFBUF_Pos 19 /**< \brief (NVMCTRL_SW0) ADC Bias Reference Buffer Scaling */
#define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
#define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
#define FUSES_BOD12USERLEVEL_ADDR NVMCTRL_USER
#define FUSES_BOD12USERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BOD12 User Level */
#define FUSES_BOD12USERLEVEL_Msk (_U_(0x3F) << FUSES_BOD12USERLEVEL_Pos)
#define FUSES_BOD12USERLEVEL(value) (FUSES_BOD12USERLEVEL_Msk & ((value) << FUSES_BOD12USERLEVEL_Pos))
#define FUSES_BOD12_ACTION_ADDR NVMCTRL_USER
#define FUSES_BOD12_ACTION_Pos 23 /**< \brief (NVMCTRL_USER) BOD12 Action */
#define FUSES_BOD12_ACTION_Msk (_U_(0x3) << FUSES_BOD12_ACTION_Pos)
#define FUSES_BOD12_ACTION(value) (FUSES_BOD12_ACTION_Msk & ((value) << FUSES_BOD12_ACTION_Pos))
#define FUSES_BOD12_DIS_ADDR NVMCTRL_USER
#define FUSES_BOD12_DIS_Pos 16 /**< \brief (NVMCTRL_USER) BOD12 Disable */
#define FUSES_BOD12_DIS_Msk (_U_(0x1) << FUSES_BOD12_DIS_Pos)
#define FUSES_BOD12_HYST_ADDR NVMCTRL_USER
#define FUSES_BOD12_HYST_Pos 25 /**< \brief (NVMCTRL_USER) BOD12 Hysteresis */
#define FUSES_BOD12_HYST_Msk (_U_(0x1) << FUSES_BOD12_HYST_Pos)
#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
#define FUSES_BOD33USERLEVEL_Pos 1 /**< \brief (NVMCTRL_USER) BOD33 User Level */
#define FUSES_BOD33USERLEVEL_Msk (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos)
#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
#define FUSES_BOD33_ACTION_Pos 9 /**< \brief (NVMCTRL_USER) BOD33 Action */
#define FUSES_BOD33_ACTION_Msk (_U_(0x3) << FUSES_BOD33_ACTION_Pos)
#define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
#define FUSES_BOD33_DIS_ADDR NVMCTRL_USER
#define FUSES_BOD33_DIS_Pos 0 /**< \brief (NVMCTRL_USER) BOD33 Disable */
#define FUSES_BOD33_DIS_Msk (_U_(0x1) << FUSES_BOD33_DIS_Pos)
#define FUSES_BOD33_HYST_ADDR NVMCTRL_USER
#define FUSES_BOD33_HYST_Pos 11 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
#define FUSES_BOD33_HYST_Msk (_U_(0xF) << FUSES_BOD33_HYST_Pos)
#define FUSES_BOD33_HYST(value) (FUSES_BOD33_HYST_Msk & ((value) << FUSES_BOD33_HYST_Pos))
#define FUSES_HOT_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
#define FUSES_HOT_ADC_VAL_CTAT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature CTAT */
#define FUSES_HOT_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_CTAT_Pos)
#define FUSES_HOT_ADC_VAL_CTAT(value) (FUSES_HOT_ADC_VAL_CTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_CTAT_Pos))
#define FUSES_HOT_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
#define FUSES_HOT_ADC_VAL_PTAT_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature PTAT */
#define FUSES_HOT_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_PTAT_Pos)
#define FUSES_HOT_ADC_VAL_PTAT(value) (FUSES_HOT_ADC_VAL_PTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_PTAT_Pos))
#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
#define FUSES_HOT_INT1V_VAL_Msk (_U_(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
#define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
#define FUSES_HOT_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
#define FUSES_HOT_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
#define FUSES_ROOM_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
#define FUSES_ROOM_ADC_VAL_CTAT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature CTAT */
#define FUSES_ROOM_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_CTAT_Pos)
#define FUSES_ROOM_ADC_VAL_CTAT(value) (FUSES_ROOM_ADC_VAL_CTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_CTAT_Pos))
#define FUSES_ROOM_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
#define FUSES_ROOM_ADC_VAL_PTAT_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature PTAT */
#define FUSES_ROOM_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_PTAT_Pos)
#define FUSES_ROOM_ADC_VAL_PTAT(value) (FUSES_ROOM_ADC_VAL_PTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_PTAT_Pos))
#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
#define FUSES_ROOM_INT1V_VAL_Msk (_U_(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
#define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
#define FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
#define NVMCTRL_FUSES_BOOTPROT_Pos 26 /**< \brief (NVMCTRL_USER) Bootloader Size */
#define NVMCTRL_FUSES_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_FUSES_BOOTPROT_Pos)
#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 8)
#define NVMCTRL_FUSES_REGION_LOCKS_Pos 0 /**< \brief (NVMCTRL_USER) NVM Region Locks */
#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFFFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
#define NVMCTRL_FUSES_SEEPSZ_ADDR (NVMCTRL_USER + 4)
#define NVMCTRL_FUSES_SEEPSZ_Pos 4 /**< \brief (NVMCTRL_USER) Size Of SmartEEPROM Page */
#define NVMCTRL_FUSES_SEEPSZ_Msk (_U_(0x7) << NVMCTRL_FUSES_SEEPSZ_Pos)
#define NVMCTRL_FUSES_SEEPSZ(value) (NVMCTRL_FUSES_SEEPSZ_Msk & ((value) << NVMCTRL_FUSES_SEEPSZ_Pos))
#define NVMCTRL_FUSES_SEESBLK_ADDR (NVMCTRL_USER + 4)
#define NVMCTRL_FUSES_SEESBLK_Pos 0 /**< \brief (NVMCTRL_USER) Number Of Physical NVM Blocks Composing a SmartEEPROM Sector */
#define NVMCTRL_FUSES_SEESBLK_Msk (_U_(0xF) << NVMCTRL_FUSES_SEESBLK_Pos)
#define NVMCTRL_FUSES_SEESBLK(value) (NVMCTRL_FUSES_SEESBLK_Msk & ((value) << NVMCTRL_FUSES_SEESBLK_Pos))
#define RAMECC_FUSES_ECCDIS_ADDR (NVMCTRL_USER + 4)
#define RAMECC_FUSES_ECCDIS_Pos 7 /**< \brief (NVMCTRL_USER) RAM ECC Disable fuse */
#define RAMECC_FUSES_ECCDIS_Msk (_U_(0x1) << RAMECC_FUSES_ECCDIS_Pos)
#define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4)
#define USB_FUSES_TRANSN_Pos 0 /**< \brief (NVMCTRL_SW0) USB pad Transn calibration */
#define USB_FUSES_TRANSN_Msk (_U_(0x1F) << USB_FUSES_TRANSN_Pos)
#define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
#define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4)
#define USB_FUSES_TRANSP_Pos 5 /**< \brief (NVMCTRL_SW0) USB pad Transp calibration */
#define USB_FUSES_TRANSP_Msk (_U_(0x1F) << USB_FUSES_TRANSP_Pos)
#define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
#define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4)
#define USB_FUSES_TRIM_Pos 10 /**< \brief (NVMCTRL_SW0) USB pad Trim calibration */
#define USB_FUSES_TRIM_Msk (_U_(0x7) << USB_FUSES_TRIM_Pos)
#define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
#define WDT_FUSES_ALWAYSON_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_ALWAYSON_Pos 17 /**< \brief (NVMCTRL_USER) WDT Always On */
#define WDT_FUSES_ALWAYSON_Msk (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos)
#define WDT_FUSES_ENABLE_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_ENABLE_Pos 16 /**< \brief (NVMCTRL_USER) WDT Enable */
#define WDT_FUSES_ENABLE_Msk (_U_(0x1) << WDT_FUSES_ENABLE_Pos)
#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_EWOFFSET_Pos 26 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
#define WDT_FUSES_EWOFFSET_Msk (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos)
#define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
#define WDT_FUSES_PER_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_PER_Pos 18 /**< \brief (NVMCTRL_USER) WDT Period */
#define WDT_FUSES_PER_Msk (_U_(0xF) << WDT_FUSES_PER_Pos)
#define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_WEN_Pos 30 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
#define WDT_FUSES_WEN_Msk (_U_(0x1) << WDT_FUSES_WEN_Pos)
#define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_WINDOW_Pos 22 /**< \brief (NVMCTRL_USER) WDT Window */
#define WDT_FUSES_WINDOW_Msk (_U_(0xF) << WDT_FUSES_WINDOW_Pos)
#define WDT_FUSES_WINDOW(value) (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))
/*@}*/
#endif /* _SAMD51_NVMCTRL_COMPONENT_ */

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/**
* \file
*
* \brief Component description for OSC32KCTRL
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_OSC32KCTRL_COMPONENT_
#define _SAMD51_OSC32KCTRL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR OSC32KCTRL */
/* ========================================================================== */
/** \addtogroup SAMD51_OSC32KCTRL 32kHz Oscillators Control */
/*@{*/
#define OSC32KCTRL_U2400
#define REV_OSC32KCTRL 0x100
/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
uint32_t :1; /*!< bit: 1 Reserved */
uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */
#define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
#define OSC32KCTRL_INTENCLR_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
uint32_t :1; /*!< bit: 1 Reserved */
uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */
#define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
#define OSC32KCTRL_INTENSET_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
__I uint32_t :1; /*!< bit: 1 Reserved */
__I uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
__I uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */
#define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
#define OSC32KCTRL_INTFLAG_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
uint32_t :1; /*!< bit: 1 Reserved */
uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
uint32_t XOSC32KSW:1; /*!< bit: 3 XOSC32K Clock switch */
uint32_t :28; /*!< bit: 4..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */
#define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
#define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */
#define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
#define OSC32KCTRL_STATUS_MASK _U_(0x0000000D) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSC32KCTRL_RTCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) RTC Clock Selection */
#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection */
#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
uint16_t :1; /*!< bit: 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint16_t CGM:2; /*!< bit: 13..14 Control Gain Mode */
uint16_t :1; /*!< bit: 15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} OSC32KCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
#define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
#define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
#define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
#define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
#define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
#define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
#define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
#define OSC32KCTRL_XOSC32K_CGM_Pos 13 /**< \brief (OSC32KCTRL_XOSC32K) Control Gain Mode */
#define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
#define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1) /**< \brief (OSC32KCTRL_XOSC32K) Standard mode */
#define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2) /**< \brief (OSC32KCTRL_XOSC32K) High Speed mode */
#define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
#define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
#define OSC32KCTRL_XOSC32K_MASK _U_(0x77DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */
uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */
uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSC32KCTRL_CFDCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_CFDCTRL_OFFSET 0x16 /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */
#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */
#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */
#define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */
#define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */
#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
#define OSC32KCTRL_CFDCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */
/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSC32KCTRL_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_EVCTRL_OFFSET 0x17 /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */
#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */
#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
#define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
#define OSC32KCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */
/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t EN32K:1; /*!< bit: 1 Enable Out 32k */
uint32_t EN1K:1; /*!< bit: 2 Enable Out 1k */
uint32_t :5; /*!< bit: 3.. 7 Reserved */
uint32_t CALIB:6; /*!< bit: 8..13 Oscillator Calibration */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#define OSC32KCTRL_OSCULP32K_EN32K_Pos 1 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 32k */
#define OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
#define OSC32KCTRL_OSCULP32K_EN1K_Pos 2 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 1k */
#define OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
#define OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
/** \brief OSC32KCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 8) RTC Clock Selection */
RoReg8 Reserved1[0x3];
__IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
__IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */
__IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */
RoReg8 Reserved2[0x4];
__IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
} Osc32kctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_OSC32KCTRL_COMPONENT_ */

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/**
* \file
*
* \brief Component description for OSCCTRL
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_OSCCTRL_COMPONENT_
#define _SAMD51_OSCCTRL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR OSCCTRL */
/* ========================================================================== */
/** \addtogroup SAMD51_OSCCTRL Oscillators Control */
/*@{*/
#define OSCCTRL_U2401
#define REV_OSCCTRL 0x100
/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDEO0:1; /*!< bit: 0 Clock 0 Failure Detector Event Output Enable */
uint8_t CFDEO1:1; /*!< bit: 1 Clock 1 Failure Detector Event Output Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CFDEO:2; /*!< bit: 0.. 1 Clock x Failure Detector Event Output Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_EVCTRL_OFFSET 0x00 /**< \brief (OSCCTRL_EVCTRL offset) Event Control */
#define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */
#define OSCCTRL_EVCTRL_CFDEO0_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable */
#define OSCCTRL_EVCTRL_CFDEO0 (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos)
#define OSCCTRL_EVCTRL_CFDEO1_Pos 1 /**< \brief (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable */
#define OSCCTRL_EVCTRL_CFDEO1 (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos)
#define OSCCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock x Failure Detector Event Output Enable */
#define OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)
#define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
#define OSCCTRL_EVCTRL_MASK _U_(0x03) /**< \brief (OSCCTRL_EVCTRL) MASK Register */
/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */
uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */
uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */
uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */
uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */
uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */
uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */
uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */
uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */
uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */
uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */
uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_INTENCLR_OFFSET 0x04 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */
#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */
#define OSCCTRL_INTENCLR_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCRDY0 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)
#define OSCCTRL_INTENCLR_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCRDY1 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)
#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC x Ready Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
#define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)
#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)
#define OSCCTRL_INTENCLR_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC x Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)
#define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
#define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */
#define OSCCTRL_INTENCLR_DFLLRDY (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)
#define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
#define OSCCTRL_INTENCLR_DFLLOOB (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)
#define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
#define OSCCTRL_INTENCLR_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)
#define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
#define OSCCTRL_INTENCLR_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)
#define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
#define OSCCTRL_INTENCLR_DFLLRCS (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)
#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)
#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)
#define OSCCTRL_INTENCLR_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)
#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)
#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)
#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)
#define OSCCTRL_INTENCLR_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)
#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)
#define OSCCTRL_INTENCLR_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENCLR) MASK Register */
/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */
uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */
uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */
uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */
uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */
uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */
uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */
uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */
uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */
uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */
uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */
uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_INTENSET_OFFSET 0x08 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */
#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */
#define OSCCTRL_INTENSET_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCRDY0 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)
#define OSCCTRL_INTENSET_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCRDY1 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)
#define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC x Ready Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)
#define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
#define OSCCTRL_INTENSET_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)
#define OSCCTRL_INTENSET_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)
#define OSCCTRL_INTENSET_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC x Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)
#define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
#define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */
#define OSCCTRL_INTENSET_DFLLRDY (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)
#define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
#define OSCCTRL_INTENSET_DFLLOOB (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)
#define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
#define OSCCTRL_INTENSET_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)
#define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
#define OSCCTRL_INTENSET_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)
#define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
#define OSCCTRL_INTENSET_DFLLRCS (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)
#define OSCCTRL_INTENSET_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable */
#define OSCCTRL_INTENSET_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)
#define OSCCTRL_INTENSET_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable */
#define OSCCTRL_INTENSET_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)
#define OSCCTRL_INTENSET_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable */
#define OSCCTRL_INTENSET_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)
#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */
#define OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)
#define OSCCTRL_INTENSET_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable */
#define OSCCTRL_INTENSET_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)
#define OSCCTRL_INTENSET_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable */
#define OSCCTRL_INTENSET_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)
#define OSCCTRL_INTENSET_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable */
#define OSCCTRL_INTENSET_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)
#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */
#define OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)
#define OSCCTRL_INTENSET_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENSET) MASK Register */
/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
__I uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
__I uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
__I uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
__I uint32_t :4; /*!< bit: 4.. 7 Reserved */
__I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
__I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
__I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
__I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
__I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
__I uint32_t :3; /*!< bit: 13..15 Reserved */
__I uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */
__I uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */
__I uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout */
__I uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */
__I uint32_t :4; /*!< bit: 20..23 Reserved */
__I uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */
__I uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */
__I uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout */
__I uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */
__I uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */
__I uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */
__I uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_INTFLAG_OFFSET 0x0C /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
#define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define OSCCTRL_INTFLAG_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Ready */
#define OSCCTRL_INTFLAG_XOSCRDY0 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)
#define OSCCTRL_INTFLAG_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Ready */
#define OSCCTRL_INTFLAG_XOSCRDY1 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)
#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC x Ready */
#define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
#define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector */
#define OSCCTRL_INTFLAG_XOSCFAIL0 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)
#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector */
#define OSCCTRL_INTFLAG_XOSCFAIL1 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)
#define OSCCTRL_INTFLAG_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC x Clock Failure Detector */
#define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)
#define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
#define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */
#define OSCCTRL_INTFLAG_DFLLRDY (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)
#define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */
#define OSCCTRL_INTFLAG_DFLLOOB (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)
#define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */
#define OSCCTRL_INTFLAG_DFLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)
#define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */
#define OSCCTRL_INTFLAG_DFLLLCKC (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)
#define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */
#define OSCCTRL_INTFLAG_DFLLRCS (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)
#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Rise */
#define OSCCTRL_INTFLAG_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)
#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Fall */
#define OSCCTRL_INTFLAG_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)
#define OSCCTRL_INTFLAG_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Timeout */
#define OSCCTRL_INTFLAG_DPLL0LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)
#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete */
#define OSCCTRL_INTFLAG_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)
#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Rise */
#define OSCCTRL_INTFLAG_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)
#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Fall */
#define OSCCTRL_INTFLAG_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)
#define OSCCTRL_INTFLAG_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Timeout */
#define OSCCTRL_INTFLAG_DPLL1LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)
#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete */
#define OSCCTRL_INTFLAG_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)
#define OSCCTRL_INTFLAG_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTFLAG) MASK Register */
/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) (R/ 32) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
uint32_t XOSCCKSW0:1; /*!< bit: 4 XOSC 0 Clock Switch */
uint32_t XOSCCKSW1:1; /*!< bit: 5 XOSC 1 Clock Switch */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */
uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */
uint32_t DPLL0TO:1; /*!< bit: 18 DPLL0 Timeout */
uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */
uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */
uint32_t DPLL1TO:1; /*!< bit: 26 DPLL1 Timeout */
uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */
uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */
uint32_t XOSCCKSW:2; /*!< bit: 4.. 5 XOSC x Clock Switch */
uint32_t :26; /*!< bit: 6..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_STATUS_OFFSET 0x10 /**< \brief (OSCCTRL_STATUS offset) Status */
#define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Status */
#define OSCCTRL_STATUS_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC 0 Ready */
#define OSCCTRL_STATUS_XOSCRDY0 (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos)
#define OSCCTRL_STATUS_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_STATUS) XOSC 1 Ready */
#define OSCCTRL_STATUS_XOSCRDY1 (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos)
#define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC x Ready */
#define OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)
#define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
#define OSCCTRL_STATUS_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector */
#define OSCCTRL_STATUS_XOSCFAIL0 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)
#define OSCCTRL_STATUS_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector */
#define OSCCTRL_STATUS_XOSCFAIL1 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)
#define OSCCTRL_STATUS_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Failure Detector */
#define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)
#define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
#define OSCCTRL_STATUS_XOSCCKSW0_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Switch */
#define OSCCTRL_STATUS_XOSCCKSW0 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)
#define OSCCTRL_STATUS_XOSCCKSW1_Pos 5 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Switch */
#define OSCCTRL_STATUS_XOSCCKSW1 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)
#define OSCCTRL_STATUS_XOSCCKSW_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Switch */
#define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)
#define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
#define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */
#define OSCCTRL_STATUS_DFLLRDY (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)
#define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */
#define OSCCTRL_STATUS_DFLLOOB (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)
#define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */
#define OSCCTRL_STATUS_DFLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)
#define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */
#define OSCCTRL_STATUS_DFLLLCKC (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)
#define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */
#define OSCCTRL_STATUS_DFLLRCS (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)
#define OSCCTRL_STATUS_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Rise */
#define OSCCTRL_STATUS_DPLL0LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)
#define OSCCTRL_STATUS_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Fall */
#define OSCCTRL_STATUS_DPLL0LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)
#define OSCCTRL_STATUS_DPLL0TO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL0 Timeout */
#define OSCCTRL_STATUS_DPLL0TO (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)
#define OSCCTRL_STATUS_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete */
#define OSCCTRL_STATUS_DPLL0LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)
#define OSCCTRL_STATUS_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Rise */
#define OSCCTRL_STATUS_DPLL1LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)
#define OSCCTRL_STATUS_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Fall */
#define OSCCTRL_STATUS_DPLL1LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)
#define OSCCTRL_STATUS_DPLL1TO_Pos 26 /**< \brief (OSCCTRL_STATUS) DPLL1 Timeout */
#define OSCCTRL_STATUS_DPLL1TO (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)
#define OSCCTRL_STATUS_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete */
#define OSCCTRL_STATUS_DPLL1LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)
#define OSCCTRL_STATUS_MASK _U_(0x0F0F1F3F) /**< \brief (OSCCTRL_STATUS) MASK Register */
/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint32_t :3; /*!< bit: 3.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t LOWBUFGAIN:1; /*!< bit: 8 Low Buffer Gain Enable */
uint32_t IPTAT:2; /*!< bit: 9..10 Oscillator Current Reference */
uint32_t IMULT:4; /*!< bit: 11..14 Oscillator Current Multiplier */
uint32_t ENALC:1; /*!< bit: 15 Automatic Loop Control Enable */
uint32_t CFDEN:1; /*!< bit: 16 Clock Failure Detector Enable */
uint32_t SWBEN:1; /*!< bit: 17 Xosc Clock Switch Enable */
uint32_t :2; /*!< bit: 18..19 Reserved */
uint32_t STARTUP:4; /*!< bit: 20..23 Start-Up Time */
uint32_t CFDPRESC:4; /*!< bit: 24..27 Clock Failure Detector Prescaler */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_XOSCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_XOSCCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator Control */
#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator Control */
#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */
#define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */
#define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */
#define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */
#define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable */
#define OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
#define OSCCTRL_XOSCCTRL_IPTAT_Pos 9 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Reference */
#define OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)
#define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
#define OSCCTRL_XOSCCTRL_IMULT_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier */
#define OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)
#define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
#define OSCCTRL_XOSCCTRL_ENALC_Pos 15 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable */
#define OSCCTRL_XOSCCTRL_ENALC (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)
#define OSCCTRL_XOSCCTRL_CFDEN_Pos 16 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable */
#define OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)
#define OSCCTRL_XOSCCTRL_SWBEN_Pos 17 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */
#define OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)
#define OSCCTRL_XOSCCTRL_STARTUP_Pos 20 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */
#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler */
#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)
#define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
#define OSCCTRL_XOSCCTRL_MASK _U_(0x0FF3FFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */
/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 DFLL Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_DFLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DFLLCTRLA_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLCTRLA offset) DFLL48M Control A */
#define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82) /**< \brief (OSCCTRL_DFLLCTRLA reset_value) DFLL48M Control A */
#define OSCCTRL_DFLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLA) DFLL Enable */
#define OSCCTRL_DFLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)
#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLA) Run in Standby */
#define OSCCTRL_DFLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)
#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLA) On Demand Control */
#define OSCCTRL_DFLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)
#define OSCCTRL_DFLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DFLLCTRLA) MASK Register */
/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t MODE:1; /*!< bit: 0 Operating Mode Selection */
uint8_t STABLE:1; /*!< bit: 1 Stable DFLL Frequency */
uint8_t LLAW:1; /*!< bit: 2 Lose Lock After Wake */
uint8_t USBCRM:1; /*!< bit: 3 USB Clock Recovery Mode */
uint8_t CCDIS:1; /*!< bit: 4 Chill Cycle Disable */
uint8_t QLDIS:1; /*!< bit: 5 Quick Lock Disable */
uint8_t BPLCKC:1; /*!< bit: 6 Bypass Coarse Lock */
uint8_t WAITLOCK:1; /*!< bit: 7 Wait Lock */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_DFLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DFLLCTRLB_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLCTRLB offset) DFLL48M Control B */
#define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLCTRLB reset_value) DFLL48M Control B */
#define OSCCTRL_DFLLCTRLB_MODE_Pos 0 /**< \brief (OSCCTRL_DFLLCTRLB) Operating Mode Selection */
#define OSCCTRL_DFLLCTRLB_MODE (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)
#define OSCCTRL_DFLLCTRLB_STABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency */
#define OSCCTRL_DFLLCTRLB_STABLE (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)
#define OSCCTRL_DFLLCTRLB_LLAW_Pos 2 /**< \brief (OSCCTRL_DFLLCTRLB) Lose Lock After Wake */
#define OSCCTRL_DFLLCTRLB_LLAW (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)
#define OSCCTRL_DFLLCTRLB_USBCRM_Pos 3 /**< \brief (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode */
#define OSCCTRL_DFLLCTRLB_USBCRM (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)
#define OSCCTRL_DFLLCTRLB_CCDIS_Pos 4 /**< \brief (OSCCTRL_DFLLCTRLB) Chill Cycle Disable */
#define OSCCTRL_DFLLCTRLB_CCDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
#define OSCCTRL_DFLLCTRLB_QLDIS_Pos 5 /**< \brief (OSCCTRL_DFLLCTRLB) Quick Lock Disable */
#define OSCCTRL_DFLLCTRLB_QLDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)
#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock */
#define OSCCTRL_DFLLCTRLB_BPLCKC (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLB) Wait Lock */
#define OSCCTRL_DFLLCTRLB_WAITLOCK (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)
#define OSCCTRL_DFLLCTRLB_MASK _U_(0xFF) /**< \brief (OSCCTRL_DFLLCTRLB) MASK Register */
/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FINE:8; /*!< bit: 0.. 7 Fine Value */
uint32_t :2; /*!< bit: 8.. 9 Reserved */
uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_DFLLVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DFLLVAL_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */
#define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */
#define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */
#define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)
#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
#define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */
#define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)
#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
#define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */
#define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)
#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
#define OSCCTRL_DFLLVAL_MASK _U_(0xFFFFFCFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */
/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
uint32_t FSTEP:8; /*!< bit: 16..23 Fine Maximum Step */
uint32_t :2; /*!< bit: 24..25 Reserved */
uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_DFLLMUL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DFLLMUL_OFFSET 0x28 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */
#define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
#define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */
#define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)
#define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
#define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */
#define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)
#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
#define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */
#define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)
#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
#define OSCCTRL_DFLLMUL_MASK _U_(0xFCFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */
/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
uint8_t DFLLCTRLB:1; /*!< bit: 2 DFLLCTRLB Synchronization Busy */
uint8_t DFLLVAL:1; /*!< bit: 3 DFLLVAL Synchronization Busy */
uint8_t DFLLMUL:1; /*!< bit: 4 DFLLMUL Synchronization Busy */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_DFLLSYNC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DFLLSYNC_OFFSET 0x2C /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */
#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
#define OSCCTRL_DFLLSYNC_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy */
#define OSCCTRL_DFLLSYNC_ENABLE (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)
#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2 /**< \brief (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy */
#define OSCCTRL_DFLLSYNC_DFLLCTRLB (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)
#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3 /**< \brief (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy */
#define OSCCTRL_DFLLSYNC_DFLLVAL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)
#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4 /**< \brief (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy */
#define OSCCTRL_DFLLSYNC_DFLLMUL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)
#define OSCCTRL_DFLLSYNC_MASK _U_(0x1E) /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */
/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W 8) DPLL DPLL Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLCTRLA_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control A */
#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control A */
#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) DPLL Enable */
#define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */
#define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand Control */
#define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
#define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */
/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LDR:13; /*!< bit: 0..12 Loop Divider Ratio */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t LDRFRAC:5; /*!< bit: 16..20 Loop Divider Ratio Fractional Part */
uint32_t :11; /*!< bit: 21..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLRATIO_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */
#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
#define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */
#define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
#define OSCCTRL_DPLLRATIO_MASK _U_(0x001F1FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */
/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL DPLL Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FILTER:4; /*!< bit: 0.. 3 Proportional Integral Filter Selection */
uint32_t WUF:1; /*!< bit: 4 Wake Up Fast */
uint32_t REFCLK:3; /*!< bit: 5.. 7 Reference Clock Selection */
uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
uint32_t LBYPASS:1; /*!< bit: 11 Lock Bypass */
uint32_t DCOFILTER:3; /*!< bit: 12..14 Sigma-Delta DCO Filter Selection */
uint32_t DCOEN:1; /*!< bit: 15 DCO Filter Enable */
uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLCTRLB_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLCTRLB offset) DPLL Control B */
#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) DPLL Control B */
#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
#define OSCCTRL_DPLLCTRLB_WUF_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */
#define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 5 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */
#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */
#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */
#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */
#define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */
#define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */
#define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */
#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */
#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
#define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
#define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
#define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */
#define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)
#define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
#define OSCCTRL_DPLLCTRLB_DCOEN_Pos 15 /**< \brief (OSCCTRL_DPLLCTRLB) DCO Filter Enable */
#define OSCCTRL_DPLLCTRLB_DCOEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
#define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */
#define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
#define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FFFFFF) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */
/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) (R/ 32) DPLL DPLL Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */
uint32_t DPLLRATIO:1; /*!< bit: 2 DPLL Loop Divider Ratio Synchronization Status */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLSYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */
#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */
#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */
#define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status */
#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
#define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x00000006) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */
/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) (R/ 32) DPLL DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
uint32_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLSTATUS_OFFSET 0x40 /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */
#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */
#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */
#define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */
#define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
#define OSCCTRL_DPLLSTATUS_MASK _U_(0x00000003) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */
/** \brief OscctrlDpll hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x00 (R/W 8) DPLL Control A */
RoReg8 Reserved1[0x3];
__IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x04 (R/W 32) DPLL Ratio Control */
__IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x08 (R/W 32) DPLL Control B */
__I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) DPLL Synchronization Busy */
__I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x10 (R/ 32) DPLL Status */
} OscctrlDpll;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief OSCCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO OSCCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x00 (R/W 8) Event Control */
RoReg8 Reserved1[0x3];
__IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Clear */
__IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set */
__IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */
__I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/ 32) Status */
__IO OSCCTRL_XOSCCTRL_Type XOSCCTRL[2]; /**< \brief Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */
__IO OSCCTRL_DFLLCTRLA_Type DFLLCTRLA; /**< \brief Offset: 0x1C (R/W 8) DFLL48M Control A */
RoReg8 Reserved2[0x3];
__IO OSCCTRL_DFLLCTRLB_Type DFLLCTRLB; /**< \brief Offset: 0x20 (R/W 8) DFLL48M Control B */
RoReg8 Reserved3[0x3];
__IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x24 (R/W 32) DFLL48M Value */
__IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Multiplier */
__IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x2C (R/W 8) DFLL48M Synchronization */
RoReg8 Reserved4[0x3];
OscctrlDpll Dpll[2]; /**< \brief Offset: 0x30 OscctrlDpll groups [DPLLS_NUM] */
} Oscctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_OSCCTRL_COMPONENT_ */

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/**
* \file
*
* \brief Component description for PAC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PAC_COMPONENT_
#define _SAMD51_PAC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PAC */
/* ========================================================================== */
/** \addtogroup SAMD51_PAC Peripheral Access Controller */
/*@{*/
#define PAC_U2120
#define REV_PAC 0x120
/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */
uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WRCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */
#define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */
#define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */
#define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
#define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
#define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */
#define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
#define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */
#define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */
#define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */
#define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */
#define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */
/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */
#define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */
#define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
#define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
#define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */
/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
#define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */
#define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
#define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
#define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */
/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */
#define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */
#define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
#define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos)
#define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */
/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t FLASH_:1; /*!< bit: 0 FLASH */
__I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */
__I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */
__I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */
__I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */
__I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */
__I uint32_t RAMDMACICM_:1; /*!< bit: 6 RAMDMACICM */
__I uint32_t HPB0_:1; /*!< bit: 7 HPB0 */
__I uint32_t HPB1_:1; /*!< bit: 8 HPB1 */
__I uint32_t HPB2_:1; /*!< bit: 9 HPB2 */
__I uint32_t HPB3_:1; /*!< bit: 10 HPB3 */
__I uint32_t PUKCC_:1; /*!< bit: 11 PUKCC */
__I uint32_t SDHC0_:1; /*!< bit: 12 SDHC0 */
__I uint32_t SDHC1_:1; /*!< bit: 13 SDHC1 */
__I uint32_t QSPI_:1; /*!< bit: 14 QSPI */
__I uint32_t BKUPRAM_:1; /*!< bit: 15 BKUPRAM */
__I uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGAHB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
#define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */
#define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */
#define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
#define PAC_INTFLAGAHB_FLASH_ALT_Pos 1 /**< \brief (PAC_INTFLAGAHB) FLASH_ALT */
#define PAC_INTFLAGAHB_FLASH_ALT (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos)
#define PAC_INTFLAGAHB_SEEPROM_Pos 2 /**< \brief (PAC_INTFLAGAHB) SEEPROM */
#define PAC_INTFLAGAHB_SEEPROM (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos)
#define PAC_INTFLAGAHB_RAMCM4S_Pos 3 /**< \brief (PAC_INTFLAGAHB) RAMCM4S */
#define PAC_INTFLAGAHB_RAMCM4S (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos)
#define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4 /**< \brief (PAC_INTFLAGAHB) RAMPPPDSU */
#define PAC_INTFLAGAHB_RAMPPPDSU (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)
#define PAC_INTFLAGAHB_RAMDMAWR_Pos 5 /**< \brief (PAC_INTFLAGAHB) RAMDMAWR */
#define PAC_INTFLAGAHB_RAMDMAWR (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos)
#define PAC_INTFLAGAHB_RAMDMACICM_Pos 6 /**< \brief (PAC_INTFLAGAHB) RAMDMACICM */
#define PAC_INTFLAGAHB_RAMDMACICM (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos)
#define PAC_INTFLAGAHB_HPB0_Pos 7 /**< \brief (PAC_INTFLAGAHB) HPB0 */
#define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
#define PAC_INTFLAGAHB_HPB1_Pos 8 /**< \brief (PAC_INTFLAGAHB) HPB1 */
#define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
#define PAC_INTFLAGAHB_HPB2_Pos 9 /**< \brief (PAC_INTFLAGAHB) HPB2 */
#define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
#define PAC_INTFLAGAHB_HPB3_Pos 10 /**< \brief (PAC_INTFLAGAHB) HPB3 */
#define PAC_INTFLAGAHB_HPB3 (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
#define PAC_INTFLAGAHB_PUKCC_Pos 11 /**< \brief (PAC_INTFLAGAHB) PUKCC */
#define PAC_INTFLAGAHB_PUKCC (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos)
#define PAC_INTFLAGAHB_SDHC0_Pos 12 /**< \brief (PAC_INTFLAGAHB) SDHC0 */
#define PAC_INTFLAGAHB_SDHC0 (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos)
#define PAC_INTFLAGAHB_SDHC1_Pos 13 /**< \brief (PAC_INTFLAGAHB) SDHC1 */
#define PAC_INTFLAGAHB_SDHC1 (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos)
#define PAC_INTFLAGAHB_QSPI_Pos 14 /**< \brief (PAC_INTFLAGAHB) QSPI */
#define PAC_INTFLAGAHB_QSPI (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos)
#define PAC_INTFLAGAHB_BKUPRAM_Pos 15 /**< \brief (PAC_INTFLAGAHB) BKUPRAM */
#define PAC_INTFLAGAHB_BKUPRAM (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos)
#define PAC_INTFLAGAHB_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGAHB) MASK Register */
/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t PAC_:1; /*!< bit: 0 PAC */
__I uint32_t PM_:1; /*!< bit: 1 PM */
__I uint32_t MCLK_:1; /*!< bit: 2 MCLK */
__I uint32_t RSTC_:1; /*!< bit: 3 RSTC */
__I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */
__I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */
__I uint32_t SUPC_:1; /*!< bit: 6 SUPC */
__I uint32_t GCLK_:1; /*!< bit: 7 GCLK */
__I uint32_t WDT_:1; /*!< bit: 8 WDT */
__I uint32_t RTC_:1; /*!< bit: 9 RTC */
__I uint32_t EIC_:1; /*!< bit: 10 EIC */
__I uint32_t FREQM_:1; /*!< bit: 11 FREQM */
__I uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 */
__I uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 */
__I uint32_t TC0_:1; /*!< bit: 14 TC0 */
__I uint32_t TC1_:1; /*!< bit: 15 TC1 */
__I uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
#define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */
#define PAC_INTFLAGA_PAC_Pos 0 /**< \brief (PAC_INTFLAGA) PAC */
#define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
#define PAC_INTFLAGA_PM_Pos 1 /**< \brief (PAC_INTFLAGA) PM */
#define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
#define PAC_INTFLAGA_MCLK_Pos 2 /**< \brief (PAC_INTFLAGA) MCLK */
#define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
#define PAC_INTFLAGA_RSTC_Pos 3 /**< \brief (PAC_INTFLAGA) RSTC */
#define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
#define PAC_INTFLAGA_OSCCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSCCTRL */
#define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
#define PAC_INTFLAGA_OSC32KCTRL_Pos 5 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
#define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
#define PAC_INTFLAGA_SUPC_Pos 6 /**< \brief (PAC_INTFLAGA) SUPC */
#define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
#define PAC_INTFLAGA_GCLK_Pos 7 /**< \brief (PAC_INTFLAGA) GCLK */
#define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
#define PAC_INTFLAGA_WDT_Pos 8 /**< \brief (PAC_INTFLAGA) WDT */
#define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
#define PAC_INTFLAGA_RTC_Pos 9 /**< \brief (PAC_INTFLAGA) RTC */
#define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
#define PAC_INTFLAGA_EIC_Pos 10 /**< \brief (PAC_INTFLAGA) EIC */
#define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
#define PAC_INTFLAGA_FREQM_Pos 11 /**< \brief (PAC_INTFLAGA) FREQM */
#define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
#define PAC_INTFLAGA_SERCOM0_Pos 12 /**< \brief (PAC_INTFLAGA) SERCOM0 */
#define PAC_INTFLAGA_SERCOM0 (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos)
#define PAC_INTFLAGA_SERCOM1_Pos 13 /**< \brief (PAC_INTFLAGA) SERCOM1 */
#define PAC_INTFLAGA_SERCOM1 (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos)
#define PAC_INTFLAGA_TC0_Pos 14 /**< \brief (PAC_INTFLAGA) TC0 */
#define PAC_INTFLAGA_TC0 (_U_(0x1) << PAC_INTFLAGA_TC0_Pos)
#define PAC_INTFLAGA_TC1_Pos 15 /**< \brief (PAC_INTFLAGA) TC1 */
#define PAC_INTFLAGA_TC1 (_U_(0x1) << PAC_INTFLAGA_TC1_Pos)
#define PAC_INTFLAGA_MASK _U_(0x0000FFFF) /**< \brief (PAC_INTFLAGA) MASK Register */
/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t USB_:1; /*!< bit: 0 USB */
__I uint32_t DSU_:1; /*!< bit: 1 DSU */
__I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */
__I uint32_t CMCC_:1; /*!< bit: 3 CMCC */
__I uint32_t PORT_:1; /*!< bit: 4 PORT */
__I uint32_t DMAC_:1; /*!< bit: 5 DMAC */
__I uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX */
__I uint32_t EVSYS_:1; /*!< bit: 7 EVSYS */
__I uint32_t :1; /*!< bit: 8 Reserved */
__I uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 */
__I uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 */
__I uint32_t TCC0_:1; /*!< bit: 11 TCC0 */
__I uint32_t TCC1_:1; /*!< bit: 12 TCC1 */
__I uint32_t TC2_:1; /*!< bit: 13 TC2 */
__I uint32_t TC3_:1; /*!< bit: 14 TC3 */
__I uint32_t TAL_:1; /*!< bit: 15 TAL */
__I uint32_t RAMECC_:1; /*!< bit: 16 RAMECC */
__I uint32_t :15; /*!< bit: 17..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
#define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */
#define PAC_INTFLAGB_USB_Pos 0 /**< \brief (PAC_INTFLAGB) USB */
#define PAC_INTFLAGB_USB (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
#define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */
#define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
#define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */
#define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
#define PAC_INTFLAGB_CMCC_Pos 3 /**< \brief (PAC_INTFLAGB) CMCC */
#define PAC_INTFLAGB_CMCC (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos)
#define PAC_INTFLAGB_PORT_Pos 4 /**< \brief (PAC_INTFLAGB) PORT */
#define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
#define PAC_INTFLAGB_DMAC_Pos 5 /**< \brief (PAC_INTFLAGB) DMAC */
#define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
#define PAC_INTFLAGB_HMATRIX_Pos 6 /**< \brief (PAC_INTFLAGB) HMATRIX */
#define PAC_INTFLAGB_HMATRIX (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos)
#define PAC_INTFLAGB_EVSYS_Pos 7 /**< \brief (PAC_INTFLAGB) EVSYS */
#define PAC_INTFLAGB_EVSYS (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos)
#define PAC_INTFLAGB_SERCOM2_Pos 9 /**< \brief (PAC_INTFLAGB) SERCOM2 */
#define PAC_INTFLAGB_SERCOM2 (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos)
#define PAC_INTFLAGB_SERCOM3_Pos 10 /**< \brief (PAC_INTFLAGB) SERCOM3 */
#define PAC_INTFLAGB_SERCOM3 (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos)
#define PAC_INTFLAGB_TCC0_Pos 11 /**< \brief (PAC_INTFLAGB) TCC0 */
#define PAC_INTFLAGB_TCC0 (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos)
#define PAC_INTFLAGB_TCC1_Pos 12 /**< \brief (PAC_INTFLAGB) TCC1 */
#define PAC_INTFLAGB_TCC1 (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos)
#define PAC_INTFLAGB_TC2_Pos 13 /**< \brief (PAC_INTFLAGB) TC2 */
#define PAC_INTFLAGB_TC2 (_U_(0x1) << PAC_INTFLAGB_TC2_Pos)
#define PAC_INTFLAGB_TC3_Pos 14 /**< \brief (PAC_INTFLAGB) TC3 */
#define PAC_INTFLAGB_TC3 (_U_(0x1) << PAC_INTFLAGB_TC3_Pos)
#define PAC_INTFLAGB_TAL_Pos 15 /**< \brief (PAC_INTFLAGB) TAL */
#define PAC_INTFLAGB_TAL (_U_(0x1) << PAC_INTFLAGB_TAL_Pos)
#define PAC_INTFLAGB_RAMECC_Pos 16 /**< \brief (PAC_INTFLAGB) RAMECC */
#define PAC_INTFLAGB_RAMECC (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos)
#define PAC_INTFLAGB_MASK _U_(0x0001FEFF) /**< \brief (PAC_INTFLAGB) MASK Register */
/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t :3; /*!< bit: 0.. 2 Reserved */
__I uint32_t TCC2_:1; /*!< bit: 3 TCC2 */
__I uint32_t TCC3_:1; /*!< bit: 4 TCC3 */
__I uint32_t TC4_:1; /*!< bit: 5 TC4 */
__I uint32_t TC5_:1; /*!< bit: 6 TC5 */
__I uint32_t PDEC_:1; /*!< bit: 7 PDEC */
__I uint32_t AC_:1; /*!< bit: 8 AC */
__I uint32_t AES_:1; /*!< bit: 9 AES */
__I uint32_t TRNG_:1; /*!< bit: 10 TRNG */
__I uint32_t ICM_:1; /*!< bit: 11 ICM */
__I uint32_t PUKCC_:1; /*!< bit: 12 PUKCC */
__I uint32_t QSPI_:1; /*!< bit: 13 QSPI */
__I uint32_t CCL_:1; /*!< bit: 14 CCL */
__I uint32_t :17; /*!< bit: 15..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
#define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
#define PAC_INTFLAGC_TCC2_Pos 3 /**< \brief (PAC_INTFLAGC) TCC2 */
#define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
#define PAC_INTFLAGC_TCC3_Pos 4 /**< \brief (PAC_INTFLAGC) TCC3 */
#define PAC_INTFLAGC_TCC3 (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos)
#define PAC_INTFLAGC_TC4_Pos 5 /**< \brief (PAC_INTFLAGC) TC4 */
#define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
#define PAC_INTFLAGC_TC5_Pos 6 /**< \brief (PAC_INTFLAGC) TC5 */
#define PAC_INTFLAGC_TC5 (_U_(0x1) << PAC_INTFLAGC_TC5_Pos)
#define PAC_INTFLAGC_PDEC_Pos 7 /**< \brief (PAC_INTFLAGC) PDEC */
#define PAC_INTFLAGC_PDEC (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos)
#define PAC_INTFLAGC_AC_Pos 8 /**< \brief (PAC_INTFLAGC) AC */
#define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
#define PAC_INTFLAGC_AES_Pos 9 /**< \brief (PAC_INTFLAGC) AES */
#define PAC_INTFLAGC_AES (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
#define PAC_INTFLAGC_TRNG_Pos 10 /**< \brief (PAC_INTFLAGC) TRNG */
#define PAC_INTFLAGC_TRNG (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
#define PAC_INTFLAGC_ICM_Pos 11 /**< \brief (PAC_INTFLAGC) ICM */
#define PAC_INTFLAGC_ICM (_U_(0x1) << PAC_INTFLAGC_ICM_Pos)
#define PAC_INTFLAGC_PUKCC_Pos 12 /**< \brief (PAC_INTFLAGC) PUKCC */
#define PAC_INTFLAGC_PUKCC (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos)
#define PAC_INTFLAGC_QSPI_Pos 13 /**< \brief (PAC_INTFLAGC) QSPI */
#define PAC_INTFLAGC_QSPI (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
#define PAC_INTFLAGC_CCL_Pos 14 /**< \brief (PAC_INTFLAGC) CCL */
#define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
#define PAC_INTFLAGC_MASK _U_(0x00007FF8) /**< \brief (PAC_INTFLAGC) MASK Register */
/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 */
__I uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */
__I uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 */
__I uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 */
__I uint32_t TCC4_:1; /*!< bit: 4 TCC4 */
__I uint32_t TC6_:1; /*!< bit: 5 TC6 */
__I uint32_t TC7_:1; /*!< bit: 6 TC7 */
__I uint32_t ADC0_:1; /*!< bit: 7 ADC0 */
__I uint32_t ADC1_:1; /*!< bit: 8 ADC1 */
__I uint32_t DAC_:1; /*!< bit: 9 DAC */
__I uint32_t I2S_:1; /*!< bit: 10 I2S */
__I uint32_t PCC_:1; /*!< bit: 11 PCC */
__I uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGD_OFFSET 0x20 /**< \brief (PAC_INTFLAGD offset) Peripheral interrupt flag status - Bridge D */
#define PAC_INTFLAGD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGD reset_value) Peripheral interrupt flag status - Bridge D */
#define PAC_INTFLAGD_SERCOM4_Pos 0 /**< \brief (PAC_INTFLAGD) SERCOM4 */
#define PAC_INTFLAGD_SERCOM4 (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos)
#define PAC_INTFLAGD_SERCOM5_Pos 1 /**< \brief (PAC_INTFLAGD) SERCOM5 */
#define PAC_INTFLAGD_SERCOM5 (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
#define PAC_INTFLAGD_SERCOM6_Pos 2 /**< \brief (PAC_INTFLAGD) SERCOM6 */
#define PAC_INTFLAGD_SERCOM6 (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos)
#define PAC_INTFLAGD_SERCOM7_Pos 3 /**< \brief (PAC_INTFLAGD) SERCOM7 */
#define PAC_INTFLAGD_SERCOM7 (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos)
#define PAC_INTFLAGD_TCC4_Pos 4 /**< \brief (PAC_INTFLAGD) TCC4 */
#define PAC_INTFLAGD_TCC4 (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos)
#define PAC_INTFLAGD_TC6_Pos 5 /**< \brief (PAC_INTFLAGD) TC6 */
#define PAC_INTFLAGD_TC6 (_U_(0x1) << PAC_INTFLAGD_TC6_Pos)
#define PAC_INTFLAGD_TC7_Pos 6 /**< \brief (PAC_INTFLAGD) TC7 */
#define PAC_INTFLAGD_TC7 (_U_(0x1) << PAC_INTFLAGD_TC7_Pos)
#define PAC_INTFLAGD_ADC0_Pos 7 /**< \brief (PAC_INTFLAGD) ADC0 */
#define PAC_INTFLAGD_ADC0 (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos)
#define PAC_INTFLAGD_ADC1_Pos 8 /**< \brief (PAC_INTFLAGD) ADC1 */
#define PAC_INTFLAGD_ADC1 (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos)
#define PAC_INTFLAGD_DAC_Pos 9 /**< \brief (PAC_INTFLAGD) DAC */
#define PAC_INTFLAGD_DAC (_U_(0x1) << PAC_INTFLAGD_DAC_Pos)
#define PAC_INTFLAGD_I2S_Pos 10 /**< \brief (PAC_INTFLAGD) I2S */
#define PAC_INTFLAGD_I2S (_U_(0x1) << PAC_INTFLAGD_I2S_Pos)
#define PAC_INTFLAGD_PCC_Pos 11 /**< \brief (PAC_INTFLAGD) PCC */
#define PAC_INTFLAGD_PCC (_U_(0x1) << PAC_INTFLAGD_PCC_Pos)
#define PAC_INTFLAGD_MASK _U_(0x00000FFF) /**< \brief (PAC_INTFLAGD) MASK Register */
/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */
uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */
uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */
uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */
uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */
uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */
uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */
uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */
uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */
uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */
uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */
uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Protect Enable */
uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Protect Enable */
uint32_t TC0_:1; /*!< bit: 14 TC0 APB Protect Enable */
uint32_t TC1_:1; /*!< bit: 15 TC1 APB Protect Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
#define PAC_STATUSA_RESETVALUE _U_(0x00010000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */
#define PAC_STATUSA_PAC_Pos 0 /**< \brief (PAC_STATUSA) PAC APB Protect Enable */
#define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos)
#define PAC_STATUSA_PM_Pos 1 /**< \brief (PAC_STATUSA) PM APB Protect Enable */
#define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos)
#define PAC_STATUSA_MCLK_Pos 2 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
#define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
#define PAC_STATUSA_RSTC_Pos 3 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
#define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
#define PAC_STATUSA_OSCCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
#define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
#define PAC_STATUSA_OSC32KCTRL_Pos 5 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
#define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
#define PAC_STATUSA_SUPC_Pos 6 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
#define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
#define PAC_STATUSA_GCLK_Pos 7 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
#define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
#define PAC_STATUSA_WDT_Pos 8 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
#define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos)
#define PAC_STATUSA_RTC_Pos 9 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
#define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos)
#define PAC_STATUSA_EIC_Pos 10 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
#define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos)
#define PAC_STATUSA_FREQM_Pos 11 /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */
#define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
#define PAC_STATUSA_SERCOM0_Pos 12 /**< \brief (PAC_STATUSA) SERCOM0 APB Protect Enable */
#define PAC_STATUSA_SERCOM0 (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos)
#define PAC_STATUSA_SERCOM1_Pos 13 /**< \brief (PAC_STATUSA) SERCOM1 APB Protect Enable */
#define PAC_STATUSA_SERCOM1 (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos)
#define PAC_STATUSA_TC0_Pos 14 /**< \brief (PAC_STATUSA) TC0 APB Protect Enable */
#define PAC_STATUSA_TC0 (_U_(0x1) << PAC_STATUSA_TC0_Pos)
#define PAC_STATUSA_TC1_Pos 15 /**< \brief (PAC_STATUSA) TC1 APB Protect Enable */
#define PAC_STATUSA_TC1 (_U_(0x1) << PAC_STATUSA_TC1_Pos)
#define PAC_STATUSA_MASK _U_(0x0000FFFF) /**< \brief (PAC_STATUSA) MASK Register */
/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */
uint32_t CMCC_:1; /*!< bit: 3 CMCC APB Protect Enable */
uint32_t PORT_:1; /*!< bit: 4 PORT APB Protect Enable */
uint32_t DMAC_:1; /*!< bit: 5 DMAC APB Protect Enable */
uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Protect Enable */
uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Protect Enable */
uint32_t :1; /*!< bit: 8 Reserved */
uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Protect Enable */
uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Protect Enable */
uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Protect Enable */
uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Protect Enable */
uint32_t TC2_:1; /*!< bit: 13 TC2 APB Protect Enable */
uint32_t TC3_:1; /*!< bit: 14 TC3 APB Protect Enable */
uint32_t TAL_:1; /*!< bit: 15 TAL APB Protect Enable */
uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Protect Enable */
uint32_t :15; /*!< bit: 17..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
#define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */
#define PAC_STATUSB_USB_Pos 0 /**< \brief (PAC_STATUSB) USB APB Protect Enable */
#define PAC_STATUSB_USB (_U_(0x1) << PAC_STATUSB_USB_Pos)
#define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
#define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos)
#define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
#define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
#define PAC_STATUSB_CMCC_Pos 3 /**< \brief (PAC_STATUSB) CMCC APB Protect Enable */
#define PAC_STATUSB_CMCC (_U_(0x1) << PAC_STATUSB_CMCC_Pos)
#define PAC_STATUSB_PORT_Pos 4 /**< \brief (PAC_STATUSB) PORT APB Protect Enable */
#define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos)
#define PAC_STATUSB_DMAC_Pos 5 /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */
#define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
#define PAC_STATUSB_HMATRIX_Pos 6 /**< \brief (PAC_STATUSB) HMATRIX APB Protect Enable */
#define PAC_STATUSB_HMATRIX (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos)
#define PAC_STATUSB_EVSYS_Pos 7 /**< \brief (PAC_STATUSB) EVSYS APB Protect Enable */
#define PAC_STATUSB_EVSYS (_U_(0x1) << PAC_STATUSB_EVSYS_Pos)
#define PAC_STATUSB_SERCOM2_Pos 9 /**< \brief (PAC_STATUSB) SERCOM2 APB Protect Enable */
#define PAC_STATUSB_SERCOM2 (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos)
#define PAC_STATUSB_SERCOM3_Pos 10 /**< \brief (PAC_STATUSB) SERCOM3 APB Protect Enable */
#define PAC_STATUSB_SERCOM3 (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos)
#define PAC_STATUSB_TCC0_Pos 11 /**< \brief (PAC_STATUSB) TCC0 APB Protect Enable */
#define PAC_STATUSB_TCC0 (_U_(0x1) << PAC_STATUSB_TCC0_Pos)
#define PAC_STATUSB_TCC1_Pos 12 /**< \brief (PAC_STATUSB) TCC1 APB Protect Enable */
#define PAC_STATUSB_TCC1 (_U_(0x1) << PAC_STATUSB_TCC1_Pos)
#define PAC_STATUSB_TC2_Pos 13 /**< \brief (PAC_STATUSB) TC2 APB Protect Enable */
#define PAC_STATUSB_TC2 (_U_(0x1) << PAC_STATUSB_TC2_Pos)
#define PAC_STATUSB_TC3_Pos 14 /**< \brief (PAC_STATUSB) TC3 APB Protect Enable */
#define PAC_STATUSB_TC3 (_U_(0x1) << PAC_STATUSB_TC3_Pos)
#define PAC_STATUSB_TAL_Pos 15 /**< \brief (PAC_STATUSB) TAL APB Protect Enable */
#define PAC_STATUSB_TAL (_U_(0x1) << PAC_STATUSB_TAL_Pos)
#define PAC_STATUSB_RAMECC_Pos 16 /**< \brief (PAC_STATUSB) RAMECC APB Protect Enable */
#define PAC_STATUSB_RAMECC (_U_(0x1) << PAC_STATUSB_RAMECC_Pos)
#define PAC_STATUSB_MASK _U_(0x0001FEFF) /**< \brief (PAC_STATUSB) MASK Register */
/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :3; /*!< bit: 0.. 2 Reserved */
uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Protect Enable */
uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Protect Enable */
uint32_t TC4_:1; /*!< bit: 5 TC4 APB Protect Enable */
uint32_t TC5_:1; /*!< bit: 6 TC5 APB Protect Enable */
uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Protect Enable */
uint32_t AC_:1; /*!< bit: 8 AC APB Protect Enable */
uint32_t AES_:1; /*!< bit: 9 AES APB Protect Enable */
uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Protect Enable */
uint32_t ICM_:1; /*!< bit: 11 ICM APB Protect Enable */
uint32_t PUKCC_:1; /*!< bit: 12 PUKCC APB Protect Enable */
uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Protect Enable */
uint32_t CCL_:1; /*!< bit: 14 CCL APB Protect Enable */
uint32_t :17; /*!< bit: 15..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
#define PAC_STATUSC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
#define PAC_STATUSC_TCC2_Pos 3 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
#define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
#define PAC_STATUSC_TCC3_Pos 4 /**< \brief (PAC_STATUSC) TCC3 APB Protect Enable */
#define PAC_STATUSC_TCC3 (_U_(0x1) << PAC_STATUSC_TCC3_Pos)
#define PAC_STATUSC_TC4_Pos 5 /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */
#define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos)
#define PAC_STATUSC_TC5_Pos 6 /**< \brief (PAC_STATUSC) TC5 APB Protect Enable */
#define PAC_STATUSC_TC5 (_U_(0x1) << PAC_STATUSC_TC5_Pos)
#define PAC_STATUSC_PDEC_Pos 7 /**< \brief (PAC_STATUSC) PDEC APB Protect Enable */
#define PAC_STATUSC_PDEC (_U_(0x1) << PAC_STATUSC_PDEC_Pos)
#define PAC_STATUSC_AC_Pos 8 /**< \brief (PAC_STATUSC) AC APB Protect Enable */
#define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos)
#define PAC_STATUSC_AES_Pos 9 /**< \brief (PAC_STATUSC) AES APB Protect Enable */
#define PAC_STATUSC_AES (_U_(0x1) << PAC_STATUSC_AES_Pos)
#define PAC_STATUSC_TRNG_Pos 10 /**< \brief (PAC_STATUSC) TRNG APB Protect Enable */
#define PAC_STATUSC_TRNG (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
#define PAC_STATUSC_ICM_Pos 11 /**< \brief (PAC_STATUSC) ICM APB Protect Enable */
#define PAC_STATUSC_ICM (_U_(0x1) << PAC_STATUSC_ICM_Pos)
#define PAC_STATUSC_PUKCC_Pos 12 /**< \brief (PAC_STATUSC) PUKCC APB Protect Enable */
#define PAC_STATUSC_PUKCC (_U_(0x1) << PAC_STATUSC_PUKCC_Pos)
#define PAC_STATUSC_QSPI_Pos 13 /**< \brief (PAC_STATUSC) QSPI APB Protect Enable */
#define PAC_STATUSC_QSPI (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
#define PAC_STATUSC_CCL_Pos 14 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
#define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos)
#define PAC_STATUSC_MASK _U_(0x00007FF8) /**< \brief (PAC_STATUSC) MASK Register */
/* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Protect Enable */
uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */
uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Protect Enable */
uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Protect Enable */
uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Protect Enable */
uint32_t TC6_:1; /*!< bit: 5 TC6 APB Protect Enable */
uint32_t TC7_:1; /*!< bit: 6 TC7 APB Protect Enable */
uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Protect Enable */
uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Protect Enable */
uint32_t DAC_:1; /*!< bit: 9 DAC APB Protect Enable */
uint32_t I2S_:1; /*!< bit: 10 I2S APB Protect Enable */
uint32_t PCC_:1; /*!< bit: 11 PCC APB Protect Enable */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_STATUSD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_STATUSD_OFFSET 0x40 /**< \brief (PAC_STATUSD offset) Peripheral write protection status - Bridge D */
#define PAC_STATUSD_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSD reset_value) Peripheral write protection status - Bridge D */
#define PAC_STATUSD_SERCOM4_Pos 0 /**< \brief (PAC_STATUSD) SERCOM4 APB Protect Enable */
#define PAC_STATUSD_SERCOM4 (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos)
#define PAC_STATUSD_SERCOM5_Pos 1 /**< \brief (PAC_STATUSD) SERCOM5 APB Protect Enable */
#define PAC_STATUSD_SERCOM5 (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
#define PAC_STATUSD_SERCOM6_Pos 2 /**< \brief (PAC_STATUSD) SERCOM6 APB Protect Enable */
#define PAC_STATUSD_SERCOM6 (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos)
#define PAC_STATUSD_SERCOM7_Pos 3 /**< \brief (PAC_STATUSD) SERCOM7 APB Protect Enable */
#define PAC_STATUSD_SERCOM7 (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos)
#define PAC_STATUSD_TCC4_Pos 4 /**< \brief (PAC_STATUSD) TCC4 APB Protect Enable */
#define PAC_STATUSD_TCC4 (_U_(0x1) << PAC_STATUSD_TCC4_Pos)
#define PAC_STATUSD_TC6_Pos 5 /**< \brief (PAC_STATUSD) TC6 APB Protect Enable */
#define PAC_STATUSD_TC6 (_U_(0x1) << PAC_STATUSD_TC6_Pos)
#define PAC_STATUSD_TC7_Pos 6 /**< \brief (PAC_STATUSD) TC7 APB Protect Enable */
#define PAC_STATUSD_TC7 (_U_(0x1) << PAC_STATUSD_TC7_Pos)
#define PAC_STATUSD_ADC0_Pos 7 /**< \brief (PAC_STATUSD) ADC0 APB Protect Enable */
#define PAC_STATUSD_ADC0 (_U_(0x1) << PAC_STATUSD_ADC0_Pos)
#define PAC_STATUSD_ADC1_Pos 8 /**< \brief (PAC_STATUSD) ADC1 APB Protect Enable */
#define PAC_STATUSD_ADC1 (_U_(0x1) << PAC_STATUSD_ADC1_Pos)
#define PAC_STATUSD_DAC_Pos 9 /**< \brief (PAC_STATUSD) DAC APB Protect Enable */
#define PAC_STATUSD_DAC (_U_(0x1) << PAC_STATUSD_DAC_Pos)
#define PAC_STATUSD_I2S_Pos 10 /**< \brief (PAC_STATUSD) I2S APB Protect Enable */
#define PAC_STATUSD_I2S (_U_(0x1) << PAC_STATUSD_I2S_Pos)
#define PAC_STATUSD_PCC_Pos 11 /**< \brief (PAC_STATUSD) PCC APB Protect Enable */
#define PAC_STATUSD_PCC (_U_(0x1) << PAC_STATUSD_PCC_Pos)
#define PAC_STATUSD_MASK _U_(0x00000FFF) /**< \brief (PAC_STATUSD) MASK Register */
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */
__IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */
RoReg8 Reserved1[0x3];
__IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */
__IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */
RoReg8 Reserved2[0x6];
__IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
__IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
__IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
__IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
__IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */
RoReg8 Reserved3[0x10];
__I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */
__I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */
__I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */
__I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_PAC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for PCC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PCC_COMPONENT_
#define _SAMD51_PCC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PCC */
/* ========================================================================== */
/** \addtogroup SAMD51_PCC Parallel Capture Controller */
/*@{*/
#define PCC_U2017
#define REV_PCC 0x110
/* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PCEN:1; /*!< bit: 0 Parallel Capture Enable */
uint32_t :3; /*!< bit: 1.. 3 Reserved */
uint32_t DSIZE:2; /*!< bit: 4.. 5 Data size */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t SCALE:1; /*!< bit: 8 Scale data */
uint32_t ALWYS:1; /*!< bit: 9 Always Sampling */
uint32_t HALFS:1; /*!< bit: 10 Half Sampling */
uint32_t FRSTS:1; /*!< bit: 11 First sample */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t ISIZE:3; /*!< bit: 16..18 Input Data Size */
uint32_t :11; /*!< bit: 19..29 Reserved */
uint32_t CID:2; /*!< bit: 30..31 Clear If Disabled */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PCC_MR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PCC_MR_OFFSET 0x00 /**< \brief (PCC_MR offset) Mode Register */
#define PCC_MR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_MR reset_value) Mode Register */
#define PCC_MR_PCEN_Pos 0 /**< \brief (PCC_MR) Parallel Capture Enable */
#define PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos)
#define PCC_MR_DSIZE_Pos 4 /**< \brief (PCC_MR) Data size */
#define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos)
#define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
#define PCC_MR_SCALE_Pos 8 /**< \brief (PCC_MR) Scale data */
#define PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos)
#define PCC_MR_ALWYS_Pos 9 /**< \brief (PCC_MR) Always Sampling */
#define PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos)
#define PCC_MR_HALFS_Pos 10 /**< \brief (PCC_MR) Half Sampling */
#define PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos)
#define PCC_MR_FRSTS_Pos 11 /**< \brief (PCC_MR) First sample */
#define PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos)
#define PCC_MR_ISIZE_Pos 16 /**< \brief (PCC_MR) Input Data Size */
#define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos)
#define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
#define PCC_MR_CID_Pos 30 /**< \brief (PCC_MR) Clear If Disabled */
#define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos)
#define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
#define PCC_MR_MASK _U_(0xC0070F31) /**< \brief (PCC_MR) MASK Register */
/* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Enable */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PCC_IER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PCC_IER_OFFSET 0x04 /**< \brief (PCC_IER offset) Interrupt Enable Register */
#define PCC_IER_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IER reset_value) Interrupt Enable Register */
#define PCC_IER_DRDY_Pos 0 /**< \brief (PCC_IER) Data Ready Interrupt Enable */
#define PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos)
#define PCC_IER_OVRE_Pos 1 /**< \brief (PCC_IER) Overrun Error Interrupt Enable */
#define PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos)
#define PCC_IER_MASK _U_(0x00000003) /**< \brief (PCC_IER) MASK Register */
/* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Disable */
uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Disable */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PCC_IDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PCC_IDR_OFFSET 0x08 /**< \brief (PCC_IDR offset) Interrupt Disable Register */
#define PCC_IDR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IDR reset_value) Interrupt Disable Register */
#define PCC_IDR_DRDY_Pos 0 /**< \brief (PCC_IDR) Data Ready Interrupt Disable */
#define PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos)
#define PCC_IDR_OVRE_Pos 1 /**< \brief (PCC_IDR) Overrun Error Interrupt Disable */
#define PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos)
#define PCC_IDR_MASK _U_(0x00000003) /**< \brief (PCC_IDR) MASK Register */
/* -------- PCC_IMR : (PCC Offset: 0x0C) (R/ 32) Interrupt Mask Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Mask */
uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Mask */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PCC_IMR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PCC_IMR_OFFSET 0x0C /**< \brief (PCC_IMR offset) Interrupt Mask Register */
#define PCC_IMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IMR reset_value) Interrupt Mask Register */
#define PCC_IMR_DRDY_Pos 0 /**< \brief (PCC_IMR) Data Ready Interrupt Mask */
#define PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos)
#define PCC_IMR_OVRE_Pos 1 /**< \brief (PCC_IMR) Overrun Error Interrupt Mask */
#define PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos)
#define PCC_IMR_MASK _U_(0x00000003) /**< \brief (PCC_IMR) MASK Register */
/* -------- PCC_ISR : (PCC Offset: 0x10) (R/ 32) Interrupt Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Status */
uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Status */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PCC_ISR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PCC_ISR_OFFSET 0x10 /**< \brief (PCC_ISR offset) Interrupt Status Register */
#define PCC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_ISR reset_value) Interrupt Status Register */
#define PCC_ISR_DRDY_Pos 0 /**< \brief (PCC_ISR) Data Ready Interrupt Status */
#define PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos)
#define PCC_ISR_OVRE_Pos 1 /**< \brief (PCC_ISR) Overrun Error Interrupt Status */
#define PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos)
#define PCC_ISR_MASK _U_(0x00000003) /**< \brief (PCC_ISR) MASK Register */
/* -------- PCC_RHR : (PCC Offset: 0x14) (R/ 32) Reception Holding Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RDATA:32; /*!< bit: 0..31 Reception Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PCC_RHR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PCC_RHR_OFFSET 0x14 /**< \brief (PCC_RHR offset) Reception Holding Register */
#define PCC_RHR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_RHR reset_value) Reception Holding Register */
#define PCC_RHR_RDATA_Pos 0 /**< \brief (PCC_RHR) Reception Data */
#define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
#define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
#define PCC_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (PCC_RHR) MASK Register */
/* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPEN:1; /*!< bit: 0 Write Protection Enable */
uint32_t :7; /*!< bit: 1.. 7 Reserved */
uint32_t WPKEY:24; /*!< bit: 8..31 Write Protection Key */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PCC_WPMR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PCC_WPMR_OFFSET 0xE0 /**< \brief (PCC_WPMR offset) Write Protection Mode Register */
#define PCC_WPMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPMR reset_value) Write Protection Mode Register */
#define PCC_WPMR_WPEN_Pos 0 /**< \brief (PCC_WPMR) Write Protection Enable */
#define PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos)
#define PCC_WPMR_WPKEY_Pos 8 /**< \brief (PCC_WPMR) Write Protection Key */
#define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
#define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
#define PCC_WPMR_MASK _U_(0xFFFFFF01) /**< \brief (PCC_WPMR) MASK Register */
/* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/ 32) Write Protection Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WPVS:1; /*!< bit: 0 Write Protection Violation Source */
uint32_t :7; /*!< bit: 1.. 7 Reserved */
uint32_t WPVSRC:16; /*!< bit: 8..23 Write Protection Violation Status */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PCC_WPSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PCC_WPSR_OFFSET 0xE4 /**< \brief (PCC_WPSR offset) Write Protection Status Register */
#define PCC_WPSR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPSR reset_value) Write Protection Status Register */
#define PCC_WPSR_WPVS_Pos 0 /**< \brief (PCC_WPSR) Write Protection Violation Source */
#define PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos)
#define PCC_WPSR_WPVSRC_Pos 8 /**< \brief (PCC_WPSR) Write Protection Violation Status */
#define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
#define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
#define PCC_WPSR_MASK _U_(0x00FFFF01) /**< \brief (PCC_WPSR) MASK Register */
/** \brief PCC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */
__O PCC_IER_Type IER; /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */
__O PCC_IDR_Type IDR; /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */
__I PCC_IMR_Type IMR; /**< \brief Offset: 0x0C (R/ 32) Interrupt Mask Register */
__I PCC_ISR_Type ISR; /**< \brief Offset: 0x10 (R/ 32) Interrupt Status Register */
__I PCC_RHR_Type RHR; /**< \brief Offset: 0x14 (R/ 32) Reception Holding Register */
RoReg8 Reserved1[0xC8];
__IO PCC_WPMR_Type WPMR; /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */
__I PCC_WPSR_Type WPSR; /**< \brief Offset: 0xE4 (R/ 32) Write Protection Status Register */
} Pcc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_PCC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for PDEC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PDEC_COMPONENT_
#define _SAMD51_PDEC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PDEC */
/* ========================================================================== */
/** \addtogroup SAMD51_PDEC Quadrature Decodeur */
/*@{*/
#define PDEC_U2263
#define REV_PDEC 0x100
/* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t MODE:2; /*!< bit: 2.. 3 Operation Mode */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t CONF:3; /*!< bit: 8..10 PDEC Configuration */
uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
uint32_t :2; /*!< bit: 12..13 Reserved */
uint32_t SWAP:1; /*!< bit: 14 PDEC Phase A and B Swap */
uint32_t PEREN:1; /*!< bit: 15 Period Enable */
uint32_t PINEN0:1; /*!< bit: 16 PDEC Input From Pin 0 Enable */
uint32_t PINEN1:1; /*!< bit: 17 PDEC Input From Pin 1 Enable */
uint32_t PINEN2:1; /*!< bit: 18 PDEC Input From Pin 2 Enable */
uint32_t :1; /*!< bit: 19 Reserved */
uint32_t PINVEN0:1; /*!< bit: 20 IO Pin 0 Invert Enable */
uint32_t PINVEN1:1; /*!< bit: 21 IO Pin 1 Invert Enable */
uint32_t PINVEN2:1; /*!< bit: 22 IO Pin 2 Invert Enable */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t ANGULAR:3; /*!< bit: 24..26 Angular Counter Length */
uint32_t :1; /*!< bit: 27 Reserved */
uint32_t MAXCMP:4; /*!< bit: 28..31 Maximum Consecutive Missing Pulses */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t PINEN:3; /*!< bit: 16..18 PDEC Input From Pin x Enable */
uint32_t :1; /*!< bit: 19 Reserved */
uint32_t PINVEN:3; /*!< bit: 20..22 IO Pin x Invert Enable */
uint32_t :9; /*!< bit: 23..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} PDEC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_CTRLA_OFFSET 0x00 /**< \brief (PDEC_CTRLA offset) Control A */
#define PDEC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CTRLA reset_value) Control A */
#define PDEC_CTRLA_SWRST_Pos 0 /**< \brief (PDEC_CTRLA) Software Reset */
#define PDEC_CTRLA_SWRST (_U_(0x1) << PDEC_CTRLA_SWRST_Pos)
#define PDEC_CTRLA_ENABLE_Pos 1 /**< \brief (PDEC_CTRLA) Enable */
#define PDEC_CTRLA_ENABLE (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos)
#define PDEC_CTRLA_MODE_Pos 2 /**< \brief (PDEC_CTRLA) Operation Mode */
#define PDEC_CTRLA_MODE_Msk (_U_(0x3) << PDEC_CTRLA_MODE_Pos)
#define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
#define PDEC_CTRLA_MODE_QDEC_Val _U_(0x0) /**< \brief (PDEC_CTRLA) QDEC operating mode */
#define PDEC_CTRLA_MODE_HALL_Val _U_(0x1) /**< \brief (PDEC_CTRLA) HALL operating mode */
#define PDEC_CTRLA_MODE_COUNTER_Val _U_(0x2) /**< \brief (PDEC_CTRLA) COUNTER operating mode */
#define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos)
#define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos)
#define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos)
#define PDEC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (PDEC_CTRLA) Run in Standby */
#define PDEC_CTRLA_RUNSTDBY (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos)
#define PDEC_CTRLA_CONF_Pos 8 /**< \brief (PDEC_CTRLA) PDEC Configuration */
#define PDEC_CTRLA_CONF_Msk (_U_(0x7) << PDEC_CTRLA_CONF_Pos)
#define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
#define PDEC_CTRLA_CONF_X4_Val _U_(0x0) /**< \brief (PDEC_CTRLA) Quadrature decoder direction */
#define PDEC_CTRLA_CONF_X4S_Val _U_(0x1) /**< \brief (PDEC_CTRLA) Secure Quadrature decoder direction */
#define PDEC_CTRLA_CONF_X2_Val _U_(0x2) /**< \brief (PDEC_CTRLA) Decoder direction */
#define PDEC_CTRLA_CONF_X2S_Val _U_(0x3) /**< \brief (PDEC_CTRLA) Secure decoder direction */
#define PDEC_CTRLA_CONF_AUTOC_Val _U_(0x4) /**< \brief (PDEC_CTRLA) Auto correction mode */
#define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos)
#define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos)
#define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos)
#define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos)
#define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos)
#define PDEC_CTRLA_ALOCK_Pos 11 /**< \brief (PDEC_CTRLA) Auto Lock */
#define PDEC_CTRLA_ALOCK (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos)
#define PDEC_CTRLA_SWAP_Pos 14 /**< \brief (PDEC_CTRLA) PDEC Phase A and B Swap */
#define PDEC_CTRLA_SWAP (_U_(0x1) << PDEC_CTRLA_SWAP_Pos)
#define PDEC_CTRLA_PEREN_Pos 15 /**< \brief (PDEC_CTRLA) Period Enable */
#define PDEC_CTRLA_PEREN (_U_(0x1) << PDEC_CTRLA_PEREN_Pos)
#define PDEC_CTRLA_PINEN0_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 0 Enable */
#define PDEC_CTRLA_PINEN0 (_U_(1) << PDEC_CTRLA_PINEN0_Pos)
#define PDEC_CTRLA_PINEN1_Pos 17 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 1 Enable */
#define PDEC_CTRLA_PINEN1 (_U_(1) << PDEC_CTRLA_PINEN1_Pos)
#define PDEC_CTRLA_PINEN2_Pos 18 /**< \brief (PDEC_CTRLA) PDEC Input From Pin 2 Enable */
#define PDEC_CTRLA_PINEN2 (_U_(1) << PDEC_CTRLA_PINEN2_Pos)
#define PDEC_CTRLA_PINEN_Pos 16 /**< \brief (PDEC_CTRLA) PDEC Input From Pin x Enable */
#define PDEC_CTRLA_PINEN_Msk (_U_(0x7) << PDEC_CTRLA_PINEN_Pos)
#define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
#define PDEC_CTRLA_PINVEN0_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin 0 Invert Enable */
#define PDEC_CTRLA_PINVEN0 (_U_(1) << PDEC_CTRLA_PINVEN0_Pos)
#define PDEC_CTRLA_PINVEN1_Pos 21 /**< \brief (PDEC_CTRLA) IO Pin 1 Invert Enable */
#define PDEC_CTRLA_PINVEN1 (_U_(1) << PDEC_CTRLA_PINVEN1_Pos)
#define PDEC_CTRLA_PINVEN2_Pos 22 /**< \brief (PDEC_CTRLA) IO Pin 2 Invert Enable */
#define PDEC_CTRLA_PINVEN2 (_U_(1) << PDEC_CTRLA_PINVEN2_Pos)
#define PDEC_CTRLA_PINVEN_Pos 20 /**< \brief (PDEC_CTRLA) IO Pin x Invert Enable */
#define PDEC_CTRLA_PINVEN_Msk (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos)
#define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
#define PDEC_CTRLA_ANGULAR_Pos 24 /**< \brief (PDEC_CTRLA) Angular Counter Length */
#define PDEC_CTRLA_ANGULAR_Msk (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos)
#define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
#define PDEC_CTRLA_MAXCMP_Pos 28 /**< \brief (PDEC_CTRLA) Maximum Consecutive Missing Pulses */
#define PDEC_CTRLA_MAXCMP_Msk (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos)
#define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
#define PDEC_CTRLA_MASK _U_(0xF777CF4F) /**< \brief (PDEC_CTRLA) MASK Register */
/* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t LUPD:1; /*!< bit: 1 Lock Update */
uint8_t :3; /*!< bit: 2.. 4 Reserved */
uint8_t CMD:3; /*!< bit: 5.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PDEC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_CTRLBCLR_OFFSET 0x04 /**< \brief (PDEC_CTRLBCLR offset) Control B Clear */
#define PDEC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBCLR reset_value) Control B Clear */
#define PDEC_CTRLBCLR_LUPD_Pos 1 /**< \brief (PDEC_CTRLBCLR) Lock Update */
#define PDEC_CTRLBCLR_LUPD (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos)
#define PDEC_CTRLBCLR_CMD_Pos 5 /**< \brief (PDEC_CTRLBCLR) Command */
#define PDEC_CTRLBCLR_CMD_Msk (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos)
#define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
#define PDEC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBCLR) No action */
#define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBCLR) Force a counter restart or retrigger */
#define PDEC_CTRLBCLR_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBCLR) Force update of double buffered registers */
#define PDEC_CTRLBCLR_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
#define PDEC_CTRLBCLR_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBCLR) Start QDEC/HALL */
#define PDEC_CTRLBCLR_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBCLR) Stop QDEC/HALL */
#define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos)
#define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos)
#define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos)
#define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos)
#define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos)
#define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos)
#define PDEC_CTRLBCLR_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBCLR) MASK Register */
/* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t LUPD:1; /*!< bit: 1 Lock Update */
uint8_t :3; /*!< bit: 2.. 4 Reserved */
uint8_t CMD:3; /*!< bit: 5.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PDEC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_CTRLBSET_OFFSET 0x05 /**< \brief (PDEC_CTRLBSET offset) Control B Set */
#define PDEC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_CTRLBSET reset_value) Control B Set */
#define PDEC_CTRLBSET_LUPD_Pos 1 /**< \brief (PDEC_CTRLBSET) Lock Update */
#define PDEC_CTRLBSET_LUPD (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos)
#define PDEC_CTRLBSET_CMD_Pos 5 /**< \brief (PDEC_CTRLBSET) Command */
#define PDEC_CTRLBSET_CMD_Msk (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos)
#define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
#define PDEC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (PDEC_CTRLBSET) No action */
#define PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_CTRLBSET) Force a counter restart or retrigger */
#define PDEC_CTRLBSET_CMD_UPDATE_Val _U_(0x2) /**< \brief (PDEC_CTRLBSET) Force update of double buffered registers */
#define PDEC_CTRLBSET_CMD_READSYNC_Val _U_(0x3) /**< \brief (PDEC_CTRLBSET) Force a read synchronization of COUNT */
#define PDEC_CTRLBSET_CMD_START_Val _U_(0x4) /**< \brief (PDEC_CTRLBSET) Start QDEC/HALL */
#define PDEC_CTRLBSET_CMD_STOP_Val _U_(0x5) /**< \brief (PDEC_CTRLBSET) Stop QDEC/HALL */
#define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos)
#define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos)
#define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos)
#define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos)
#define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos)
#define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos)
#define PDEC_CTRLBSET_MASK _U_(0xE2) /**< \brief (PDEC_CTRLBSET) MASK Register */
/* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t EVACT:2; /*!< bit: 0.. 1 Event Action */
uint16_t EVINV:3; /*!< bit: 2.. 4 Inverted Event Input Enable */
uint16_t EVEI:3; /*!< bit: 5.. 7 Event Input Enable */
uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
uint16_t ERREO:1; /*!< bit: 9 Error Output Event Enable */
uint16_t DIREO:1; /*!< bit: 10 Direction Output Event Enable */
uint16_t VLCEO:1; /*!< bit: 11 Velocity Output Event Enable */
uint16_t MCEO0:1; /*!< bit: 12 Match Channel 0 Event Output Enable */
uint16_t MCEO1:1; /*!< bit: 13 Match Channel 1 Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t MCEO:2; /*!< bit: 12..13 Match Channel x Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} PDEC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_EVCTRL_OFFSET 0x06 /**< \brief (PDEC_EVCTRL offset) Event Control */
#define PDEC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (PDEC_EVCTRL reset_value) Event Control */
#define PDEC_EVCTRL_EVACT_Pos 0 /**< \brief (PDEC_EVCTRL) Event Action */
#define PDEC_EVCTRL_EVACT_Msk (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos)
#define PDEC_EVCTRL_EVACT(value) (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
#define PDEC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (PDEC_EVCTRL) Event action disabled */
#define PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (PDEC_EVCTRL) Start, restart or retrigger on event */
#define PDEC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (PDEC_EVCTRL) Count on event */
#define PDEC_EVCTRL_EVACT_OFF (PDEC_EVCTRL_EVACT_OFF_Val << PDEC_EVCTRL_EVACT_Pos)
#define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos)
#define PDEC_EVCTRL_EVACT_COUNT (PDEC_EVCTRL_EVACT_COUNT_Val << PDEC_EVCTRL_EVACT_Pos)
#define PDEC_EVCTRL_EVINV_Pos 2 /**< \brief (PDEC_EVCTRL) Inverted Event Input Enable */
#define PDEC_EVCTRL_EVINV_Msk (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos)
#define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
#define PDEC_EVCTRL_EVEI_Pos 5 /**< \brief (PDEC_EVCTRL) Event Input Enable */
#define PDEC_EVCTRL_EVEI_Msk (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos)
#define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
#define PDEC_EVCTRL_OVFEO_Pos 8 /**< \brief (PDEC_EVCTRL) Overflow/Underflow Output Event Enable */
#define PDEC_EVCTRL_OVFEO (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos)
#define PDEC_EVCTRL_ERREO_Pos 9 /**< \brief (PDEC_EVCTRL) Error Output Event Enable */
#define PDEC_EVCTRL_ERREO (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos)
#define PDEC_EVCTRL_DIREO_Pos 10 /**< \brief (PDEC_EVCTRL) Direction Output Event Enable */
#define PDEC_EVCTRL_DIREO (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos)
#define PDEC_EVCTRL_VLCEO_Pos 11 /**< \brief (PDEC_EVCTRL) Velocity Output Event Enable */
#define PDEC_EVCTRL_VLCEO (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos)
#define PDEC_EVCTRL_MCEO0_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel 0 Event Output Enable */
#define PDEC_EVCTRL_MCEO0 (_U_(1) << PDEC_EVCTRL_MCEO0_Pos)
#define PDEC_EVCTRL_MCEO1_Pos 13 /**< \brief (PDEC_EVCTRL) Match Channel 1 Event Output Enable */
#define PDEC_EVCTRL_MCEO1 (_U_(1) << PDEC_EVCTRL_MCEO1_Pos)
#define PDEC_EVCTRL_MCEO_Pos 12 /**< \brief (PDEC_EVCTRL) Match Channel x Event Output Enable */
#define PDEC_EVCTRL_MCEO_Msk (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos)
#define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
#define PDEC_EVCTRL_MASK _U_(0x3FFF) /**< \brief (PDEC_EVCTRL) MASK Register */
/* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Disable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Disable */
uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Disable */
uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Disable */
uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Disable */
uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Disable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Disable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} PDEC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_INTENCLR_OFFSET 0x08 /**< \brief (PDEC_INTENCLR offset) Interrupt Enable Clear */
#define PDEC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENCLR reset_value) Interrupt Enable Clear */
#define PDEC_INTENCLR_OVF_Pos 0 /**< \brief (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable */
#define PDEC_INTENCLR_OVF (_U_(0x1) << PDEC_INTENCLR_OVF_Pos)
#define PDEC_INTENCLR_ERR_Pos 1 /**< \brief (PDEC_INTENCLR) Error Interrupt Disable */
#define PDEC_INTENCLR_ERR (_U_(0x1) << PDEC_INTENCLR_ERR_Pos)
#define PDEC_INTENCLR_DIR_Pos 2 /**< \brief (PDEC_INTENCLR) Direction Interrupt Disable */
#define PDEC_INTENCLR_DIR (_U_(0x1) << PDEC_INTENCLR_DIR_Pos)
#define PDEC_INTENCLR_VLC_Pos 3 /**< \brief (PDEC_INTENCLR) Velocity Interrupt Disable */
#define PDEC_INTENCLR_VLC (_U_(0x1) << PDEC_INTENCLR_VLC_Pos)
#define PDEC_INTENCLR_MC0_Pos 4 /**< \brief (PDEC_INTENCLR) Channel 0 Compare Match Disable */
#define PDEC_INTENCLR_MC0 (_U_(1) << PDEC_INTENCLR_MC0_Pos)
#define PDEC_INTENCLR_MC1_Pos 5 /**< \brief (PDEC_INTENCLR) Channel 1 Compare Match Disable */
#define PDEC_INTENCLR_MC1 (_U_(1) << PDEC_INTENCLR_MC1_Pos)
#define PDEC_INTENCLR_MC_Pos 4 /**< \brief (PDEC_INTENCLR) Channel x Compare Match Disable */
#define PDEC_INTENCLR_MC_Msk (_U_(0x3) << PDEC_INTENCLR_MC_Pos)
#define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
#define PDEC_INTENCLR_MASK _U_(0x3F) /**< \brief (PDEC_INTENCLR) MASK Register */
/* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Enable */
uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Enable */
uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} PDEC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_INTENSET_OFFSET 0x09 /**< \brief (PDEC_INTENSET offset) Interrupt Enable Set */
#define PDEC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTENSET reset_value) Interrupt Enable Set */
#define PDEC_INTENSET_OVF_Pos 0 /**< \brief (PDEC_INTENSET) Overflow/Underflow Interrupt Enable */
#define PDEC_INTENSET_OVF (_U_(0x1) << PDEC_INTENSET_OVF_Pos)
#define PDEC_INTENSET_ERR_Pos 1 /**< \brief (PDEC_INTENSET) Error Interrupt Enable */
#define PDEC_INTENSET_ERR (_U_(0x1) << PDEC_INTENSET_ERR_Pos)
#define PDEC_INTENSET_DIR_Pos 2 /**< \brief (PDEC_INTENSET) Direction Interrupt Enable */
#define PDEC_INTENSET_DIR (_U_(0x1) << PDEC_INTENSET_DIR_Pos)
#define PDEC_INTENSET_VLC_Pos 3 /**< \brief (PDEC_INTENSET) Velocity Interrupt Enable */
#define PDEC_INTENSET_VLC (_U_(0x1) << PDEC_INTENSET_VLC_Pos)
#define PDEC_INTENSET_MC0_Pos 4 /**< \brief (PDEC_INTENSET) Channel 0 Compare Match Enable */
#define PDEC_INTENSET_MC0 (_U_(1) << PDEC_INTENSET_MC0_Pos)
#define PDEC_INTENSET_MC1_Pos 5 /**< \brief (PDEC_INTENSET) Channel 1 Compare Match Enable */
#define PDEC_INTENSET_MC1 (_U_(1) << PDEC_INTENSET_MC1_Pos)
#define PDEC_INTENSET_MC_Pos 4 /**< \brief (PDEC_INTENSET) Channel x Compare Match Enable */
#define PDEC_INTENSET_MC_Msk (_U_(0x3) << PDEC_INTENSET_MC_Pos)
#define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
#define PDEC_INTENSET_MASK _U_(0x3F) /**< \brief (PDEC_INTENSET) MASK Register */
/* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow */
__I uint8_t ERR:1; /*!< bit: 1 Error */
__I uint8_t DIR:1; /*!< bit: 2 Direction Change */
__I uint8_t VLC:1; /*!< bit: 3 Velocity */
__I uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match */
__I uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match */
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t :4; /*!< bit: 0.. 3 Reserved */
__I uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match */
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} PDEC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_INTFLAG_OFFSET 0x0A /**< \brief (PDEC_INTFLAG offset) Interrupt Flag Status and Clear */
#define PDEC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PDEC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define PDEC_INTFLAG_OVF_Pos 0 /**< \brief (PDEC_INTFLAG) Overflow/Underflow */
#define PDEC_INTFLAG_OVF (_U_(0x1) << PDEC_INTFLAG_OVF_Pos)
#define PDEC_INTFLAG_ERR_Pos 1 /**< \brief (PDEC_INTFLAG) Error */
#define PDEC_INTFLAG_ERR (_U_(0x1) << PDEC_INTFLAG_ERR_Pos)
#define PDEC_INTFLAG_DIR_Pos 2 /**< \brief (PDEC_INTFLAG) Direction Change */
#define PDEC_INTFLAG_DIR (_U_(0x1) << PDEC_INTFLAG_DIR_Pos)
#define PDEC_INTFLAG_VLC_Pos 3 /**< \brief (PDEC_INTFLAG) Velocity */
#define PDEC_INTFLAG_VLC (_U_(0x1) << PDEC_INTFLAG_VLC_Pos)
#define PDEC_INTFLAG_MC0_Pos 4 /**< \brief (PDEC_INTFLAG) Channel 0 Compare Match */
#define PDEC_INTFLAG_MC0 (_U_(1) << PDEC_INTFLAG_MC0_Pos)
#define PDEC_INTFLAG_MC1_Pos 5 /**< \brief (PDEC_INTFLAG) Channel 1 Compare Match */
#define PDEC_INTFLAG_MC1 (_U_(1) << PDEC_INTFLAG_MC1_Pos)
#define PDEC_INTFLAG_MC_Pos 4 /**< \brief (PDEC_INTFLAG) Channel x Compare Match */
#define PDEC_INTFLAG_MC_Msk (_U_(0x3) << PDEC_INTFLAG_MC_Pos)
#define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
#define PDEC_INTFLAG_MASK _U_(0x3F) /**< \brief (PDEC_INTFLAG) MASK Register */
/* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t QERR:1; /*!< bit: 0 Quadrature Error Flag */
uint16_t IDXERR:1; /*!< bit: 1 Index Error Flag */
uint16_t MPERR:1; /*!< bit: 2 Missing Pulse Error flag */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t WINERR:1; /*!< bit: 4 Window Error Flag */
uint16_t HERR:1; /*!< bit: 5 Hall Error Flag */
uint16_t STOP:1; /*!< bit: 6 Stop */
uint16_t DIR:1; /*!< bit: 7 Direction Status Flag */
uint16_t PRESCBUFV:1; /*!< bit: 8 Prescaler Buffer Valid */
uint16_t FILTERBUFV:1; /*!< bit: 9 Filter Buffer Valid */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t CCBUFV0:1; /*!< bit: 12 Compare Channel 0 Buffer Valid */
uint16_t CCBUFV1:1; /*!< bit: 13 Compare Channel 1 Buffer Valid */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t CCBUFV:2; /*!< bit: 12..13 Compare Channel x Buffer Valid */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} PDEC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_STATUS_OFFSET 0x0C /**< \brief (PDEC_STATUS offset) Status */
#define PDEC_STATUS_RESETVALUE _U_(0x0040) /**< \brief (PDEC_STATUS reset_value) Status */
#define PDEC_STATUS_QERR_Pos 0 /**< \brief (PDEC_STATUS) Quadrature Error Flag */
#define PDEC_STATUS_QERR (_U_(0x1) << PDEC_STATUS_QERR_Pos)
#define PDEC_STATUS_IDXERR_Pos 1 /**< \brief (PDEC_STATUS) Index Error Flag */
#define PDEC_STATUS_IDXERR (_U_(0x1) << PDEC_STATUS_IDXERR_Pos)
#define PDEC_STATUS_MPERR_Pos 2 /**< \brief (PDEC_STATUS) Missing Pulse Error flag */
#define PDEC_STATUS_MPERR (_U_(0x1) << PDEC_STATUS_MPERR_Pos)
#define PDEC_STATUS_WINERR_Pos 4 /**< \brief (PDEC_STATUS) Window Error Flag */
#define PDEC_STATUS_WINERR (_U_(0x1) << PDEC_STATUS_WINERR_Pos)
#define PDEC_STATUS_HERR_Pos 5 /**< \brief (PDEC_STATUS) Hall Error Flag */
#define PDEC_STATUS_HERR (_U_(0x1) << PDEC_STATUS_HERR_Pos)
#define PDEC_STATUS_STOP_Pos 6 /**< \brief (PDEC_STATUS) Stop */
#define PDEC_STATUS_STOP (_U_(0x1) << PDEC_STATUS_STOP_Pos)
#define PDEC_STATUS_DIR_Pos 7 /**< \brief (PDEC_STATUS) Direction Status Flag */
#define PDEC_STATUS_DIR (_U_(0x1) << PDEC_STATUS_DIR_Pos)
#define PDEC_STATUS_PRESCBUFV_Pos 8 /**< \brief (PDEC_STATUS) Prescaler Buffer Valid */
#define PDEC_STATUS_PRESCBUFV (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos)
#define PDEC_STATUS_FILTERBUFV_Pos 9 /**< \brief (PDEC_STATUS) Filter Buffer Valid */
#define PDEC_STATUS_FILTERBUFV (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos)
#define PDEC_STATUS_CCBUFV0_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel 0 Buffer Valid */
#define PDEC_STATUS_CCBUFV0 (_U_(1) << PDEC_STATUS_CCBUFV0_Pos)
#define PDEC_STATUS_CCBUFV1_Pos 13 /**< \brief (PDEC_STATUS) Compare Channel 1 Buffer Valid */
#define PDEC_STATUS_CCBUFV1 (_U_(1) << PDEC_STATUS_CCBUFV1_Pos)
#define PDEC_STATUS_CCBUFV_Pos 12 /**< \brief (PDEC_STATUS) Compare Channel x Buffer Valid */
#define PDEC_STATUS_CCBUFV_Msk (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos)
#define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
#define PDEC_STATUS_MASK _U_(0x33F7) /**< \brief (PDEC_STATUS) MASK Register */
/* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PDEC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_DBGCTRL_OFFSET 0x0F /**< \brief (PDEC_DBGCTRL offset) Debug Control */
#define PDEC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (PDEC_DBGCTRL reset_value) Debug Control */
#define PDEC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (PDEC_DBGCTRL) Debug Run Mode */
#define PDEC_DBGCTRL_DBGRUN (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos)
#define PDEC_DBGCTRL_MASK _U_(0x01) /**< \brief (PDEC_DBGCTRL) MASK Register */
/* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) (R/ 32) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
uint32_t CTRLB:1; /*!< bit: 2 Control B Synchronization Busy */
uint32_t STATUS:1; /*!< bit: 3 Status Synchronization Busy */
uint32_t PRESC:1; /*!< bit: 4 Prescaler Synchronization Busy */
uint32_t FILTER:1; /*!< bit: 5 Filter Synchronization Busy */
uint32_t COUNT:1; /*!< bit: 6 Count Synchronization Busy */
uint32_t CC0:1; /*!< bit: 7 Compare Channel 0 Synchronization Busy */
uint32_t CC1:1; /*!< bit: 8 Compare Channel 1 Synchronization Busy */
uint32_t :23; /*!< bit: 9..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :7; /*!< bit: 0.. 6 Reserved */
uint32_t CC:2; /*!< bit: 7.. 8 Compare Channel x Synchronization Busy */
uint32_t :23; /*!< bit: 9..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} PDEC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_SYNCBUSY_OFFSET 0x10 /**< \brief (PDEC_SYNCBUSY offset) Synchronization Status */
#define PDEC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_SYNCBUSY reset_value) Synchronization Status */
#define PDEC_SYNCBUSY_SWRST_Pos 0 /**< \brief (PDEC_SYNCBUSY) Software Reset Synchronization Busy */
#define PDEC_SYNCBUSY_SWRST (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos)
#define PDEC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (PDEC_SYNCBUSY) Enable Synchronization Busy */
#define PDEC_SYNCBUSY_ENABLE (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos)
#define PDEC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (PDEC_SYNCBUSY) Control B Synchronization Busy */
#define PDEC_SYNCBUSY_CTRLB (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos)
#define PDEC_SYNCBUSY_STATUS_Pos 3 /**< \brief (PDEC_SYNCBUSY) Status Synchronization Busy */
#define PDEC_SYNCBUSY_STATUS (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos)
#define PDEC_SYNCBUSY_PRESC_Pos 4 /**< \brief (PDEC_SYNCBUSY) Prescaler Synchronization Busy */
#define PDEC_SYNCBUSY_PRESC (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos)
#define PDEC_SYNCBUSY_FILTER_Pos 5 /**< \brief (PDEC_SYNCBUSY) Filter Synchronization Busy */
#define PDEC_SYNCBUSY_FILTER (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos)
#define PDEC_SYNCBUSY_COUNT_Pos 6 /**< \brief (PDEC_SYNCBUSY) Count Synchronization Busy */
#define PDEC_SYNCBUSY_COUNT (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos)
#define PDEC_SYNCBUSY_CC0_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy */
#define PDEC_SYNCBUSY_CC0 (_U_(1) << PDEC_SYNCBUSY_CC0_Pos)
#define PDEC_SYNCBUSY_CC1_Pos 8 /**< \brief (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy */
#define PDEC_SYNCBUSY_CC1 (_U_(1) << PDEC_SYNCBUSY_CC1_Pos)
#define PDEC_SYNCBUSY_CC_Pos 7 /**< \brief (PDEC_SYNCBUSY) Compare Channel x Synchronization Busy */
#define PDEC_SYNCBUSY_CC_Msk (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos)
#define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
#define PDEC_SYNCBUSY_MASK _U_(0x000001FF) /**< \brief (PDEC_SYNCBUSY) MASK Register */
/* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PRESC:4; /*!< bit: 0.. 3 Prescaler Value */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PDEC_PRESC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_PRESC_OFFSET 0x14 /**< \brief (PDEC_PRESC offset) Prescaler Value */
#define PDEC_PRESC_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESC reset_value) Prescaler Value */
#define PDEC_PRESC_PRESC_Pos 0 /**< \brief (PDEC_PRESC) Prescaler Value */
#define PDEC_PRESC_PRESC_Msk (_U_(0xF) << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
#define PDEC_PRESC_PRESC_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESC) No division */
#define PDEC_PRESC_PRESC_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESC) Divide by 2 */
#define PDEC_PRESC_PRESC_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESC) Divide by 4 */
#define PDEC_PRESC_PRESC_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESC) Divide by 8 */
#define PDEC_PRESC_PRESC_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESC) Divide by 16 */
#define PDEC_PRESC_PRESC_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESC) Divide by 32 */
#define PDEC_PRESC_PRESC_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESC) Divide by 64 */
#define PDEC_PRESC_PRESC_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESC) Divide by 128 */
#define PDEC_PRESC_PRESC_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESC) Divide by 256 */
#define PDEC_PRESC_PRESC_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESC) Divide by 512 */
#define PDEC_PRESC_PRESC_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESC) Divide by 1024 */
#define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos)
#define PDEC_PRESC_MASK _U_(0x0F) /**< \brief (PDEC_PRESC) MASK Register */
/* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FILTER:8; /*!< bit: 0.. 7 Filter Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PDEC_FILTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_FILTER_OFFSET 0x15 /**< \brief (PDEC_FILTER offset) Filter Value */
#define PDEC_FILTER_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTER reset_value) Filter Value */
#define PDEC_FILTER_FILTER_Pos 0 /**< \brief (PDEC_FILTER) Filter Value */
#define PDEC_FILTER_FILTER_Msk (_U_(0xFF) << PDEC_FILTER_FILTER_Pos)
#define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
#define PDEC_FILTER_MASK _U_(0xFF) /**< \brief (PDEC_FILTER) MASK Register */
/* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PRESCBUF:4; /*!< bit: 0.. 3 Prescaler Buffer Value */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PDEC_PRESCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_PRESCBUF_OFFSET 0x18 /**< \brief (PDEC_PRESCBUF offset) Prescaler Buffer Value */
#define PDEC_PRESCBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_PRESCBUF reset_value) Prescaler Buffer Value */
#define PDEC_PRESCBUF_PRESCBUF_Pos 0 /**< \brief (PDEC_PRESCBUF) Prescaler Buffer Value */
#define PDEC_PRESCBUF_PRESCBUF_Msk (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
#define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0) /**< \brief (PDEC_PRESCBUF) No division */
#define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1) /**< \brief (PDEC_PRESCBUF) Divide by 2 */
#define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2) /**< \brief (PDEC_PRESCBUF) Divide by 4 */
#define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3) /**< \brief (PDEC_PRESCBUF) Divide by 8 */
#define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4) /**< \brief (PDEC_PRESCBUF) Divide by 16 */
#define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5) /**< \brief (PDEC_PRESCBUF) Divide by 32 */
#define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6) /**< \brief (PDEC_PRESCBUF) Divide by 64 */
#define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7) /**< \brief (PDEC_PRESCBUF) Divide by 128 */
#define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8) /**< \brief (PDEC_PRESCBUF) Divide by 256 */
#define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9) /**< \brief (PDEC_PRESCBUF) Divide by 512 */
#define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA) /**< \brief (PDEC_PRESCBUF) Divide by 1024 */
#define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
#define PDEC_PRESCBUF_MASK _U_(0x0F) /**< \brief (PDEC_PRESCBUF) MASK Register */
/* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FILTERBUF:8; /*!< bit: 0.. 7 Filter Buffer Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PDEC_FILTERBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_FILTERBUF_OFFSET 0x19 /**< \brief (PDEC_FILTERBUF offset) Filter Buffer Value */
#define PDEC_FILTERBUF_RESETVALUE _U_(0x00) /**< \brief (PDEC_FILTERBUF reset_value) Filter Buffer Value */
#define PDEC_FILTERBUF_FILTERBUF_Pos 0 /**< \brief (PDEC_FILTERBUF) Filter Buffer Value */
#define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos)
#define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
#define PDEC_FILTERBUF_MASK _U_(0xFF) /**< \brief (PDEC_FILTERBUF) MASK Register */
/* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:16; /*!< bit: 0..15 Counter Value */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PDEC_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_COUNT_OFFSET 0x1C /**< \brief (PDEC_COUNT offset) Counter Value */
#define PDEC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_COUNT reset_value) Counter Value */
#define PDEC_COUNT_COUNT_Pos 0 /**< \brief (PDEC_COUNT) Counter Value */
#define PDEC_COUNT_COUNT_Msk (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos)
#define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
#define PDEC_COUNT_MASK _U_(0x0000FFFF) /**< \brief (PDEC_COUNT) MASK Register */
/* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CC:16; /*!< bit: 0..15 Channel Compare Value */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PDEC_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_CC_OFFSET 0x20 /**< \brief (PDEC_CC offset) Channel n Compare Value */
#define PDEC_CC_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CC reset_value) Channel n Compare Value */
#define PDEC_CC_CC_Pos 0 /**< \brief (PDEC_CC) Channel Compare Value */
#define PDEC_CC_CC_Msk (_U_(0xFFFF) << PDEC_CC_CC_Pos)
#define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
#define PDEC_CC_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CC) MASK Register */
/* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CCBUF:16; /*!< bit: 0..15 Channel Compare Buffer Value */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PDEC_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PDEC_CCBUF_OFFSET 0x30 /**< \brief (PDEC_CCBUF offset) Channel Compare Buffer Value */
#define PDEC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (PDEC_CCBUF reset_value) Channel Compare Buffer Value */
#define PDEC_CCBUF_CCBUF_Pos 0 /**< \brief (PDEC_CCBUF) Channel Compare Buffer Value */
#define PDEC_CCBUF_CCBUF_Msk (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos)
#define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
#define PDEC_CCBUF_MASK _U_(0x0000FFFF) /**< \brief (PDEC_CCBUF) MASK Register */
/** \brief PDEC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PDEC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO PDEC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO PDEC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO PDEC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
__IO PDEC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO PDEC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO PDEC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO PDEC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/W 16) Status */
RoReg8 Reserved2[0x1];
__IO PDEC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
__I PDEC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
__IO PDEC_PRESC_Type PRESC; /**< \brief Offset: 0x14 (R/W 8) Prescaler Value */
__IO PDEC_FILTER_Type FILTER; /**< \brief Offset: 0x15 (R/W 8) Filter Value */
RoReg8 Reserved3[0x2];
__IO PDEC_PRESCBUF_Type PRESCBUF; /**< \brief Offset: 0x18 (R/W 8) Prescaler Buffer Value */
__IO PDEC_FILTERBUF_Type FILTERBUF; /**< \brief Offset: 0x19 (R/W 8) Filter Buffer Value */
RoReg8 Reserved4[0x2];
__IO PDEC_COUNT_Type COUNT; /**< \brief Offset: 0x1C (R/W 32) Counter Value */
__IO PDEC_CC_Type CC[2]; /**< \brief Offset: 0x20 (R/W 32) Channel n Compare Value */
RoReg8 Reserved5[0x8];
__IO PDEC_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
} Pdec;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_PDEC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for PM
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PM_COMPONENT_
#define _SAMD51_PM_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PM */
/* ========================================================================== */
/** \addtogroup SAMD51_PM Power Manager */
/*@{*/
#define PM_U2406
#define REV_PM 0x100
/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t IORET:1; /*!< bit: 2 I/O Retention */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_CTRLA_OFFSET 0x00 /**< \brief (PM_CTRLA offset) Control A */
#define PM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (PM_CTRLA reset_value) Control A */
#define PM_CTRLA_IORET_Pos 2 /**< \brief (PM_CTRLA) I/O Retention */
#define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
#define PM_CTRLA_MASK _U_(0x04) /**< \brief (PM_CTRLA) MASK Register */
/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_SLEEPCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
#define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */
#define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */
#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5) /**< \brief (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6) /**< \brief (PM_SLEEPCFG) Only Backup domain is powered ON */
#define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7) /**< \brief (PM_SLEEPCFG) All power domains are powered OFF */
#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */
/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_INTENCLR_OFFSET 0x04 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
#define PM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
#define PM_INTENCLR_SLEEPRDY_Pos 0 /**< \brief (PM_INTENCLR) Sleep Mode Entry Ready Enable */
#define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
#define PM_INTENCLR_MASK _U_(0x01) /**< \brief (PM_INTENCLR) MASK Register */
/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_INTENSET_OFFSET 0x05 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
#define PM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
#define PM_INTENSET_SLEEPRDY_Pos 0 /**< \brief (PM_INTENSET) Sleep Mode Entry Ready Enable */
#define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
#define PM_INTENSET_MASK _U_(0x01) /**< \brief (PM_INTENSET) MASK Register */
/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_INTFLAG_OFFSET 0x06 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
#define PM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define PM_INTFLAG_SLEEPRDY_Pos 0 /**< \brief (PM_INTFLAG) Sleep Mode Entry Ready */
#define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
#define PM_INTFLAG_MASK _U_(0x01) /**< \brief (PM_INTFLAG) MASK Register */
/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t FASTWKUP:2; /*!< bit: 4.. 5 Fast Wakeup */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_STDBYCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */
#define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
#define PM_STDBYCFG_RAMCFG_Pos 0 /**< \brief (PM_STDBYCFG) Ram Configuration */
#define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
#define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
#define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0) /**< \brief (PM_STDBYCFG) All the RAMs are retained */
#define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Only the first 32K bytes are retained */
#define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2) /**< \brief (PM_STDBYCFG) All the RAMs are OFF */
#define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)
#define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
#define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)
#define PM_STDBYCFG_FASTWKUP_Pos 4 /**< \brief (PM_STDBYCFG) Fast Wakeup */
#define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
#define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
#define PM_STDBYCFG_MASK _U_(0x33) /**< \brief (PM_STDBYCFG) MASK Register */
/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
uint8_t BRAMCFG:2; /*!< bit: 2.. 3 Backup Ram Configuration */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_HIBCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_HIBCFG_OFFSET 0x09 /**< \brief (PM_HIBCFG offset) Hibernate Configuration */
#define PM_HIBCFG_RESETVALUE _U_(0x00) /**< \brief (PM_HIBCFG reset_value) Hibernate Configuration */
#define PM_HIBCFG_RAMCFG_Pos 0 /**< \brief (PM_HIBCFG) Ram Configuration */
#define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
#define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
#define PM_HIBCFG_BRAMCFG_Pos 2 /**< \brief (PM_HIBCFG) Backup Ram Configuration */
#define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
#define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
#define PM_HIBCFG_MASK _U_(0x0F) /**< \brief (PM_HIBCFG) MASK Register */
/* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t BRAMCFG:2; /*!< bit: 0.. 1 Ram Configuration */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_BKUPCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_BKUPCFG_OFFSET 0x0A /**< \brief (PM_BKUPCFG offset) Backup Configuration */
#define PM_BKUPCFG_RESETVALUE _U_(0x00) /**< \brief (PM_BKUPCFG reset_value) Backup Configuration */
#define PM_BKUPCFG_BRAMCFG_Pos 0 /**< \brief (PM_BKUPCFG) Ram Configuration */
#define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
#define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
#define PM_BKUPCFG_MASK _U_(0x03) /**< \brief (PM_BKUPCFG) MASK Register */
/* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DLYVAL:7; /*!< bit: 0.. 6 Delay Value */
uint8_t IGNACK:1; /*!< bit: 7 Ignore Acknowledge */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_PWSAKDLY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_PWSAKDLY_OFFSET 0x12 /**< \brief (PM_PWSAKDLY offset) Power Switch Acknowledge Delay */
#define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< \brief (PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay */
#define PM_PWSAKDLY_DLYVAL_Pos 0 /**< \brief (PM_PWSAKDLY) Delay Value */
#define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
#define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
#define PM_PWSAKDLY_IGNACK_Pos 7 /**< \brief (PM_PWSAKDLY) Ignore Acknowledge */
#define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
#define PM_PWSAKDLY_MASK _U_(0xFF) /**< \brief (PM_PWSAKDLY) MASK Register */
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */
RoReg8 Reserved1[0x2];
__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved2[0x1];
__IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 8) Standby Configuration */
__IO PM_HIBCFG_Type HIBCFG; /**< \brief Offset: 0x09 (R/W 8) Hibernate Configuration */
__IO PM_BKUPCFG_Type BKUPCFG; /**< \brief Offset: 0x0A (R/W 8) Backup Configuration */
RoReg8 Reserved3[0x7];
__IO PM_PWSAKDLY_Type PWSAKDLY; /**< \brief Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_PM_COMPONENT_ */

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/**
* \file
*
* \brief Component description for PORT
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PORT_COMPONENT_
#define _SAMD51_PORT_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PORT */
/* ========================================================================== */
/** \addtogroup SAMD51_PORT Port Module */
/*@{*/
#define PORT_U2210
#define REV_PORT 0x220
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
#define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
#define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
#define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
#define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
#define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
#define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
#define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
#define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
#define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
#define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
#define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
#define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUT:32; /*!< bit: 0..31 PORT Data Output Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
#define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) PORT Data Output Value */
#define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
#define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTCLR:32; /*!< bit: 0..31 PORT Data Output Value Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
#define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) PORT Data Output Value Clear */
#define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
#define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTSET:32; /*!< bit: 0..31 PORT Data Output Value Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
#define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) PORT Data Output Value Set */
#define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
#define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTTGL:32; /*!< bit: 0..31 PORT Data Output Value Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
#define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) PORT Data Output Value Toggle */
#define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
#define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IN:32; /*!< bit: 0..31 PORT Data Input Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
#define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) PORT Data Input Value */
#define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
#define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
#define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
#define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
#define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
#define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
#define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
#define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
#define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
#define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
#define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
#define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
#define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PID0:5; /*!< bit: 0.. 4 PORT Event Pin Identifier 0 */
uint32_t EVACT0:2; /*!< bit: 5.. 6 PORT Event Action 0 */
uint32_t PORTEI0:1; /*!< bit: 7 PORT Event Input Enable 0 */
uint32_t PID1:5; /*!< bit: 8..12 PORT Event Pin Identifier 1 */
uint32_t EVACT1:2; /*!< bit: 13..14 PORT Event Action 1 */
uint32_t PORTEI1:1; /*!< bit: 15 PORT Event Input Enable 1 */
uint32_t PID2:5; /*!< bit: 16..20 PORT Event Pin Identifier 2 */
uint32_t EVACT2:2; /*!< bit: 21..22 PORT Event Action 2 */
uint32_t PORTEI2:1; /*!< bit: 23 PORT Event Input Enable 2 */
uint32_t PID3:5; /*!< bit: 24..28 PORT Event Pin Identifier 3 */
uint32_t EVACT3:2; /*!< bit: 29..30 PORT Event Action 3 */
uint32_t PORTEI3:1; /*!< bit: 31 PORT Event Input Enable 3 */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */
#define PORT_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */
#define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 0 */
#define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
#define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
#define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) PORT Event Action 0 */
#define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
#define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< \brief (PORT_EVCTRL) Event output to pin */
#define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< \brief (PORT_EVCTRL) Set output register of pin on event */
#define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< \brief (PORT_EVCTRL) Clear output register of pin on event */
#define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */
#define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 0 */
#define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
#define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 1 */
#define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
#define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
#define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) PORT Event Action 1 */
#define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
#define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
#define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 1 */
#define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
#define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 2 */
#define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
#define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
#define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) PORT Event Action 2 */
#define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
#define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
#define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 2 */
#define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
#define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) PORT Event Pin Identifier 3 */
#define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
#define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
#define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) PORT Event Action 3 */
#define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
#define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
#define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) PORT Event Input Enable 3 */
#define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
#define PORT_EVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing */
#define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing */
#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */
#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */
#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
#define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration */
#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration */
#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
#define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
#define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
#define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
#define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
#define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
__IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration */
RoReg8 Reserved1[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
PortGroup Group[4]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_PORT_COMPONENT_ */

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lib/arm_atsam/packs/atmel/SAMD51_DFP/1.0.70/include/component/qspi.h Normal file
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/**
* \file
*
* \brief Component description for QSPI
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_QSPI_COMPONENT_
#define _SAMD51_QSPI_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR QSPI */
/* ========================================================================== */
/** \addtogroup SAMD51_QSPI Quad SPI interface */
/*@{*/
#define QSPI_U2008
#define REV_QSPI 0x163
/* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t :22; /*!< bit: 2..23 Reserved */
uint32_t LASTXFER:1; /*!< bit: 24 Last Transfer */
uint32_t :7; /*!< bit: 25..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_CTRLA_OFFSET 0x00 /**< \brief (QSPI_CTRLA offset) Control A */
#define QSPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLA reset_value) Control A */
#define QSPI_CTRLA_SWRST_Pos 0 /**< \brief (QSPI_CTRLA) Software Reset */
#define QSPI_CTRLA_SWRST (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
#define QSPI_CTRLA_ENABLE_Pos 1 /**< \brief (QSPI_CTRLA) Enable */
#define QSPI_CTRLA_ENABLE (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
#define QSPI_CTRLA_LASTXFER_Pos 24 /**< \brief (QSPI_CTRLA) Last Transfer */
#define QSPI_CTRLA_LASTXFER (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
#define QSPI_CTRLA_MASK _U_(0x01000003) /**< \brief (QSPI_CTRLA) MASK Register */
/* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MODE:1; /*!< bit: 0 Serial Memory Mode */
uint32_t LOOPEN:1; /*!< bit: 1 Local Loopback Enable */
uint32_t WDRBT:1; /*!< bit: 2 Wait Data Read Before Transfer */
uint32_t SMEMREG:1; /*!< bit: 3 Serial Memory reg */
uint32_t CSMODE:2; /*!< bit: 4.. 5 Chip Select Mode */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t DATALEN:4; /*!< bit: 8..11 Data Length */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t DLYBCT:8; /*!< bit: 16..23 Delay Between Consecutive Transfers */
uint32_t DLYCS:8; /*!< bit: 24..31 Minimum Inactive CS Delay */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_CTRLB_OFFSET 0x04 /**< \brief (QSPI_CTRLB offset) Control B */
#define QSPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_CTRLB reset_value) Control B */
#define QSPI_CTRLB_MODE_Pos 0 /**< \brief (QSPI_CTRLB) Serial Memory Mode */
#define QSPI_CTRLB_MODE (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
#define QSPI_CTRLB_MODE_SPI_Val _U_(0x0) /**< \brief (QSPI_CTRLB) SPI operating mode */
#define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1) /**< \brief (QSPI_CTRLB) Serial Memory operating mode */
#define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)
#define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)
#define QSPI_CTRLB_LOOPEN_Pos 1 /**< \brief (QSPI_CTRLB) Local Loopback Enable */
#define QSPI_CTRLB_LOOPEN (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
#define QSPI_CTRLB_WDRBT_Pos 2 /**< \brief (QSPI_CTRLB) Wait Data Read Before Transfer */
#define QSPI_CTRLB_WDRBT (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
#define QSPI_CTRLB_SMEMREG_Pos 3 /**< \brief (QSPI_CTRLB) Serial Memory reg */
#define QSPI_CTRLB_SMEMREG (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
#define QSPI_CTRLB_CSMODE_Pos 4 /**< \brief (QSPI_CTRLB) Chip Select Mode */
#define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
#define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
#define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0) /**< \brief (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
#define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1) /**< \brief (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< \brief (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */
#define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
#define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
#define QSPI_CTRLB_DATALEN_Pos 8 /**< \brief (QSPI_CTRLB) Data Length */
#define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
#define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0) /**< \brief (QSPI_CTRLB) 8-bits transfer */
#define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1) /**< \brief (QSPI_CTRLB) 9 bits transfer */
#define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2) /**< \brief (QSPI_CTRLB) 10-bits transfer */
#define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3) /**< \brief (QSPI_CTRLB) 11-bits transfer */
#define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4) /**< \brief (QSPI_CTRLB) 12-bits transfer */
#define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5) /**< \brief (QSPI_CTRLB) 13-bits transfer */
#define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6) /**< \brief (QSPI_CTRLB) 14-bits transfer */
#define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7) /**< \brief (QSPI_CTRLB) 15-bits transfer */
#define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8) /**< \brief (QSPI_CTRLB) 16-bits transfer */
#define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
#define QSPI_CTRLB_DLYBCT_Pos 16 /**< \brief (QSPI_CTRLB) Delay Between Consecutive Transfers */
#define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
#define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
#define QSPI_CTRLB_DLYCS_Pos 24 /**< \brief (QSPI_CTRLB) Minimum Inactive CS Delay */
#define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
#define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
#define QSPI_CTRLB_MASK _U_(0xFFFF0F3F) /**< \brief (QSPI_CTRLB) MASK Register */
/* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CPOL:1; /*!< bit: 0 Clock Polarity */
uint32_t CPHA:1; /*!< bit: 1 Clock Phase */
uint32_t :6; /*!< bit: 2.. 7 Reserved */
uint32_t BAUD:8; /*!< bit: 8..15 Serial Clock Baud Rate */
uint32_t DLYBS:8; /*!< bit: 16..23 Delay Before SCK */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_BAUD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_BAUD_OFFSET 0x08 /**< \brief (QSPI_BAUD offset) Baud Rate */
#define QSPI_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_BAUD reset_value) Baud Rate */
#define QSPI_BAUD_CPOL_Pos 0 /**< \brief (QSPI_BAUD) Clock Polarity */
#define QSPI_BAUD_CPOL (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
#define QSPI_BAUD_CPHA_Pos 1 /**< \brief (QSPI_BAUD) Clock Phase */
#define QSPI_BAUD_CPHA (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
#define QSPI_BAUD_BAUD_Pos 8 /**< \brief (QSPI_BAUD) Serial Clock Baud Rate */
#define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
#define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
#define QSPI_BAUD_DLYBS_Pos 16 /**< \brief (QSPI_BAUD) Delay Before SCK */
#define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
#define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
#define QSPI_BAUD_MASK _U_(0x00FFFF03) /**< \brief (QSPI_BAUD) MASK Register */
/* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/ 32) Receive Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:16; /*!< bit: 0..15 Receive Data */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_RXDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_RXDATA_OFFSET 0x0C /**< \brief (QSPI_RXDATA offset) Receive Data */
#define QSPI_RXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_RXDATA reset_value) Receive Data */
#define QSPI_RXDATA_DATA_Pos 0 /**< \brief (QSPI_RXDATA) Receive Data */
#define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
#define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
#define QSPI_RXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_RXDATA) MASK Register */
/* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:16; /*!< bit: 0..15 Transmit Data */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_TXDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_TXDATA_OFFSET 0x10 /**< \brief (QSPI_TXDATA offset) Transmit Data */
#define QSPI_TXDATA_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_TXDATA reset_value) Transmit Data */
#define QSPI_TXDATA_DATA_Pos 0 /**< \brief (QSPI_TXDATA) Transmit Data */
#define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
#define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
#define QSPI_TXDATA_MASK _U_(0x0000FFFF) /**< \brief (QSPI_TXDATA) MASK Register */
/* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Disable */
uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Disable */
uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Disable */
uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Disable */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Disable */
uint32_t :1; /*!< bit: 9 Reserved */
uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Disable */
uint32_t :21; /*!< bit: 11..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_INTENCLR_OFFSET 0x14 /**< \brief (QSPI_INTENCLR offset) Interrupt Enable Clear */
#define QSPI_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENCLR reset_value) Interrupt Enable Clear */
#define QSPI_INTENCLR_RXC_Pos 0 /**< \brief (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable */
#define QSPI_INTENCLR_RXC (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
#define QSPI_INTENCLR_DRE_Pos 1 /**< \brief (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable */
#define QSPI_INTENCLR_DRE (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
#define QSPI_INTENCLR_TXC_Pos 2 /**< \brief (QSPI_INTENCLR) Transmission Complete Interrupt Disable */
#define QSPI_INTENCLR_TXC (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
#define QSPI_INTENCLR_ERROR_Pos 3 /**< \brief (QSPI_INTENCLR) Overrun Error Interrupt Disable */
#define QSPI_INTENCLR_ERROR (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
#define QSPI_INTENCLR_CSRISE_Pos 8 /**< \brief (QSPI_INTENCLR) Chip Select Rise Interrupt Disable */
#define QSPI_INTENCLR_CSRISE (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
#define QSPI_INTENCLR_INSTREND_Pos 10 /**< \brief (QSPI_INTENCLR) Instruction End Interrupt Disable */
#define QSPI_INTENCLR_INSTREND (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
#define QSPI_INTENCLR_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENCLR) MASK Register */
/* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full Interrupt Enable */
uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty Interrupt Enable */
uint32_t TXC:1; /*!< bit: 2 Transmission Complete Interrupt Enable */
uint32_t ERROR:1; /*!< bit: 3 Overrun Error Interrupt Enable */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise Interrupt Enable */
uint32_t :1; /*!< bit: 9 Reserved */
uint32_t INSTREND:1; /*!< bit: 10 Instruction End Interrupt Enable */
uint32_t :21; /*!< bit: 11..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_INTENSET_OFFSET 0x18 /**< \brief (QSPI_INTENSET offset) Interrupt Enable Set */
#define QSPI_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTENSET reset_value) Interrupt Enable Set */
#define QSPI_INTENSET_RXC_Pos 0 /**< \brief (QSPI_INTENSET) Receive Data Register Full Interrupt Enable */
#define QSPI_INTENSET_RXC (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
#define QSPI_INTENSET_DRE_Pos 1 /**< \brief (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable */
#define QSPI_INTENSET_DRE (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
#define QSPI_INTENSET_TXC_Pos 2 /**< \brief (QSPI_INTENSET) Transmission Complete Interrupt Enable */
#define QSPI_INTENSET_TXC (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
#define QSPI_INTENSET_ERROR_Pos 3 /**< \brief (QSPI_INTENSET) Overrun Error Interrupt Enable */
#define QSPI_INTENSET_ERROR (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
#define QSPI_INTENSET_CSRISE_Pos 8 /**< \brief (QSPI_INTENSET) Chip Select Rise Interrupt Enable */
#define QSPI_INTENSET_CSRISE (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
#define QSPI_INTENSET_INSTREND_Pos 10 /**< \brief (QSPI_INTENSET) Instruction End Interrupt Enable */
#define QSPI_INTENSET_INSTREND (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
#define QSPI_INTENSET_MASK _U_(0x0000050F) /**< \brief (QSPI_INTENSET) MASK Register */
/* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full */
__I uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty */
__I uint32_t TXC:1; /*!< bit: 2 Transmission Complete */
__I uint32_t ERROR:1; /*!< bit: 3 Overrun Error */
__I uint32_t :4; /*!< bit: 4.. 7 Reserved */
__I uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise */
__I uint32_t :1; /*!< bit: 9 Reserved */
__I uint32_t INSTREND:1; /*!< bit: 10 Instruction End */
__I uint32_t :21; /*!< bit: 11..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_INTFLAG_OFFSET 0x1C /**< \brief (QSPI_INTFLAG offset) Interrupt Flag Status and Clear */
#define QSPI_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define QSPI_INTFLAG_RXC_Pos 0 /**< \brief (QSPI_INTFLAG) Receive Data Register Full */
#define QSPI_INTFLAG_RXC (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
#define QSPI_INTFLAG_DRE_Pos 1 /**< \brief (QSPI_INTFLAG) Transmit Data Register Empty */
#define QSPI_INTFLAG_DRE (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
#define QSPI_INTFLAG_TXC_Pos 2 /**< \brief (QSPI_INTFLAG) Transmission Complete */
#define QSPI_INTFLAG_TXC (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
#define QSPI_INTFLAG_ERROR_Pos 3 /**< \brief (QSPI_INTFLAG) Overrun Error */
#define QSPI_INTFLAG_ERROR (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
#define QSPI_INTFLAG_CSRISE_Pos 8 /**< \brief (QSPI_INTFLAG) Chip Select Rise */
#define QSPI_INTFLAG_CSRISE (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
#define QSPI_INTFLAG_INSTREND_Pos 10 /**< \brief (QSPI_INTFLAG) Instruction End */
#define QSPI_INTFLAG_INSTREND (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
#define QSPI_INTFLAG_MASK _U_(0x0000050F) /**< \brief (QSPI_INTFLAG) MASK Register */
/* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/ 32) Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t :7; /*!< bit: 2.. 8 Reserved */
uint32_t CSSTATUS:1; /*!< bit: 9 Chip Select */
uint32_t :22; /*!< bit: 10..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_STATUS_OFFSET 0x20 /**< \brief (QSPI_STATUS offset) Status Register */
#define QSPI_STATUS_RESETVALUE _U_(0x00000200) /**< \brief (QSPI_STATUS reset_value) Status Register */
#define QSPI_STATUS_ENABLE_Pos 1 /**< \brief (QSPI_STATUS) Enable */
#define QSPI_STATUS_ENABLE (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
#define QSPI_STATUS_CSSTATUS_Pos 9 /**< \brief (QSPI_STATUS) Chip Select */
#define QSPI_STATUS_CSSTATUS (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
#define QSPI_STATUS_MASK _U_(0x00000202) /**< \brief (QSPI_STATUS) MASK Register */
/* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:32; /*!< bit: 0..31 Instruction Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_INSTRADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_INSTRADDR_OFFSET 0x30 /**< \brief (QSPI_INSTRADDR offset) Instruction Address */
#define QSPI_INSTRADDR_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRADDR reset_value) Instruction Address */
#define QSPI_INSTRADDR_ADDR_Pos 0 /**< \brief (QSPI_INSTRADDR) Instruction Address */
#define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
#define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
#define QSPI_INSTRADDR_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_INSTRADDR) MASK Register */
/* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t INSTR:8; /*!< bit: 0.. 7 Instruction Code */
uint32_t :8; /*!< bit: 8..15 Reserved */
uint32_t OPTCODE:8; /*!< bit: 16..23 Option Code */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_INSTRCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_INSTRCTRL_OFFSET 0x34 /**< \brief (QSPI_INSTRCTRL offset) Instruction Code */
#define QSPI_INSTRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRCTRL reset_value) Instruction Code */
#define QSPI_INSTRCTRL_INSTR_Pos 0 /**< \brief (QSPI_INSTRCTRL) Instruction Code */
#define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
#define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
#define QSPI_INSTRCTRL_OPTCODE_Pos 16 /**< \brief (QSPI_INSTRCTRL) Option Code */
#define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
#define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
#define QSPI_INSTRCTRL_MASK _U_(0x00FF00FF) /**< \brief (QSPI_INSTRCTRL) MASK Register */
/* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WIDTH:3; /*!< bit: 0.. 2 Instruction Code, Address, Option Code and Data Width */
uint32_t :1; /*!< bit: 3 Reserved */
uint32_t INSTREN:1; /*!< bit: 4 Instruction Enable */
uint32_t ADDREN:1; /*!< bit: 5 Address Enable */
uint32_t OPTCODEEN:1; /*!< bit: 6 Option Enable */
uint32_t DATAEN:1; /*!< bit: 7 Data Enable */
uint32_t OPTCODELEN:2; /*!< bit: 8.. 9 Option Code Length */
uint32_t ADDRLEN:1; /*!< bit: 10 Address Length */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t TFRTYPE:2; /*!< bit: 12..13 Data Transfer Type */
uint32_t CRMODE:1; /*!< bit: 14 Continuous Read Mode */
uint32_t DDREN:1; /*!< bit: 15 Double Data Rate Enable */
uint32_t DUMMYLEN:5; /*!< bit: 16..20 Dummy Cycles Length */
uint32_t :11; /*!< bit: 21..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_INSTRFRAME_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_INSTRFRAME_OFFSET 0x38 /**< \brief (QSPI_INSTRFRAME offset) Instruction Frame */
#define QSPI_INSTRFRAME_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_INSTRFRAME reset_value) Instruction Frame */
#define QSPI_INSTRFRAME_WIDTH_Pos 0 /**< \brief (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width */
#define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
#define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
#define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
#define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4) /**< \brief (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5) /**< \brief (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6) /**< \brief (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
#define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
#define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
#define QSPI_INSTRFRAME_INSTREN_Pos 4 /**< \brief (QSPI_INSTRFRAME) Instruction Enable */
#define QSPI_INSTRFRAME_INSTREN (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
#define QSPI_INSTRFRAME_ADDREN_Pos 5 /**< \brief (QSPI_INSTRFRAME) Address Enable */
#define QSPI_INSTRFRAME_ADDREN (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
#define QSPI_INSTRFRAME_OPTCODEEN_Pos 6 /**< \brief (QSPI_INSTRFRAME) Option Enable */
#define QSPI_INSTRFRAME_OPTCODEEN (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
#define QSPI_INSTRFRAME_DATAEN_Pos 7 /**< \brief (QSPI_INSTRFRAME) Data Enable */
#define QSPI_INSTRFRAME_DATAEN (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
#define QSPI_INSTRFRAME_OPTCODELEN_Pos 8 /**< \brief (QSPI_INSTRFRAME) Option Code Length */
#define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
#define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
#define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 1-bit length option code */
#define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 2-bits length option code */
#define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) 4-bits length option code */
#define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) 8-bits length option code */
#define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
#define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
#define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
#define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
#define QSPI_INSTRFRAME_ADDRLEN_Pos 10 /**< \brief (QSPI_INSTRFRAME) Address Length */
#define QSPI_INSTRFRAME_ADDRLEN (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
#define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) 24-bits address length */
#define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) 32-bits address length */
#define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
#define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
#define QSPI_INSTRFRAME_TFRTYPE_Pos 12 /**< \brief (QSPI_INSTRFRAME) Data Transfer Type */
#define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
#define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
#define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0) /**< \brief (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */
#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1) /**< \brief (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */
#define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2) /**< \brief (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */
#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3) /**< \brief (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */
#define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
#define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
#define QSPI_INSTRFRAME_CRMODE_Pos 14 /**< \brief (QSPI_INSTRFRAME) Continuous Read Mode */
#define QSPI_INSTRFRAME_CRMODE (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
#define QSPI_INSTRFRAME_DDREN_Pos 15 /**< \brief (QSPI_INSTRFRAME) Double Data Rate Enable */
#define QSPI_INSTRFRAME_DDREN (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
#define QSPI_INSTRFRAME_DUMMYLEN_Pos 16 /**< \brief (QSPI_INSTRFRAME) Dummy Cycles Length */
#define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
#define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
#define QSPI_INSTRFRAME_MASK _U_(0x001FF7F7) /**< \brief (QSPI_INSTRFRAME) MASK Register */
/* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /*!< bit: 0 Scrambling/Unscrambling Enable */
uint32_t RANDOMDIS:1; /*!< bit: 1 Scrambling/Unscrambling Random Value Disable */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_SCRAMBCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_SCRAMBCTRL_OFFSET 0x40 /**< \brief (QSPI_SCRAMBCTRL offset) Scrambling Mode */
#define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBCTRL reset_value) Scrambling Mode */
#define QSPI_SCRAMBCTRL_ENABLE_Pos 0 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable */
#define QSPI_SCRAMBCTRL_ENABLE (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1 /**< \brief (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable */
#define QSPI_SCRAMBCTRL_RANDOMDIS (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
#define QSPI_SCRAMBCTRL_MASK _U_(0x00000003) /**< \brief (QSPI_SCRAMBCTRL) MASK Register */
/* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t KEY:32; /*!< bit: 0..31 Scrambling User Key */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} QSPI_SCRAMBKEY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define QSPI_SCRAMBKEY_OFFSET 0x44 /**< \brief (QSPI_SCRAMBKEY offset) Scrambling Key */
#define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00000000) /**< \brief (QSPI_SCRAMBKEY reset_value) Scrambling Key */
#define QSPI_SCRAMBKEY_KEY_Pos 0 /**< \brief (QSPI_SCRAMBKEY) Scrambling User Key */
#define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
#define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
#define QSPI_SCRAMBKEY_MASK _U_(0xFFFFFFFF) /**< \brief (QSPI_SCRAMBKEY) MASK Register */
/** \brief QSPI APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO QSPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO QSPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO QSPI_BAUD_Type BAUD; /**< \brief Offset: 0x08 (R/W 32) Baud Rate */
__I QSPI_RXDATA_Type RXDATA; /**< \brief Offset: 0x0C (R/ 32) Receive Data */
__O QSPI_TXDATA_Type TXDATA; /**< \brief Offset: 0x10 ( /W 32) Transmit Data */
__IO QSPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Clear */
__IO QSPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set */
__IO QSPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */
__I QSPI_STATUS_Type STATUS; /**< \brief Offset: 0x20 (R/ 32) Status Register */
RoReg8 Reserved1[0xC];
__IO QSPI_INSTRADDR_Type INSTRADDR; /**< \brief Offset: 0x30 (R/W 32) Instruction Address */
__IO QSPI_INSTRCTRL_Type INSTRCTRL; /**< \brief Offset: 0x34 (R/W 32) Instruction Code */
__IO QSPI_INSTRFRAME_Type INSTRFRAME; /**< \brief Offset: 0x38 (R/W 32) Instruction Frame */
RoReg8 Reserved2[0x4];
__IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL; /**< \brief Offset: 0x40 (R/W 32) Scrambling Mode */
__O QSPI_SCRAMBKEY_Type SCRAMBKEY; /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */
} Qspi;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_QSPI_COMPONENT_ */

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/**
* \file
*
* \brief Component description for RAMECC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_RAMECC_COMPONENT_
#define _SAMD51_RAMECC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR RAMECC */
/* ========================================================================== */
/** \addtogroup SAMD51_RAMECC RAM ECC */
/*@{*/
#define RAMECC_U2268
#define REV_RAMECC 0x100
/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Clear */
uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Clear */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RAMECC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RAMECC_INTENCLR_OFFSET 0x0 /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */
#define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */
#define RAMECC_INTENCLR_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */
#define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
#define RAMECC_INTENCLR_DUALE_Pos 1 /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */
#define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
#define RAMECC_INTENCLR_MASK _U_(0x03) /**< \brief (RAMECC_INTENCLR) MASK Register */
/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Set */
uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Set */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RAMECC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RAMECC_INTENSET_OFFSET 0x1 /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */
#define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */
#define RAMECC_INTENSET_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */
#define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
#define RAMECC_INTENSET_DUALE_Pos 1 /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */
#define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
#define RAMECC_INTENSET_MASK _U_(0x03) /**< \brief (RAMECC_INTENSET) MASK Register */
/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt */
__I uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RAMECC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RAMECC_INTFLAG_OFFSET 0x2 /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */
#define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */
#define RAMECC_INTFLAG_SINGLEE_Pos 0 /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */
#define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
#define RAMECC_INTFLAG_DUALE_Pos 1 /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */
#define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
#define RAMECC_INTFLAG_MASK _U_(0x03) /**< \brief (RAMECC_INTFLAG) MASK Register */
/* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RAMECC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RAMECC_STATUS_OFFSET 0x3 /**< \brief (RAMECC_STATUS offset) Status */
#define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RAMECC_STATUS reset_value) Status */
#define RAMECC_STATUS_ECCDIS_Pos 0 /**< \brief (RAMECC_STATUS) ECC Disable */
#define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
#define RAMECC_STATUS_MASK _U_(0x01) /**< \brief (RAMECC_STATUS) MASK Register */
/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ERRADDR:17; /*!< bit: 0..16 Error Address */
uint32_t :15; /*!< bit: 17..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RAMECC_ERRADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RAMECC_ERRADDR_OFFSET 0x4 /**< \brief (RAMECC_ERRADDR offset) Error Address */
#define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */
#define RAMECC_ERRADDR_ERRADDR_Pos 0 /**< \brief (RAMECC_ERRADDR) Error Address */
#define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
#define RAMECC_ERRADDR_MASK _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */
/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
uint8_t ECCELOG:1; /*!< bit: 1 ECC Error Log */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RAMECC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RAMECC_DBGCTRL_OFFSET 0xF /**< \brief (RAMECC_DBGCTRL offset) Debug Control */
#define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */
#define RAMECC_DBGCTRL_ECCDIS_Pos 0 /**< \brief (RAMECC_DBGCTRL) ECC Disable */
#define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
#define RAMECC_DBGCTRL_ECCELOG_Pos 1 /**< \brief (RAMECC_DBGCTRL) ECC Error Log */
#define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
#define RAMECC_DBGCTRL_MASK _U_(0x03) /**< \brief (RAMECC_DBGCTRL) MASK Register */
/** \brief RAMECC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO RAMECC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0 (R/W 8) Interrupt Enable Clear */
__IO RAMECC_INTENSET_Type INTENSET; /**< \brief Offset: 0x1 (R/W 8) Interrupt Enable Set */
__IO RAMECC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2 (R/W 8) Interrupt Flag */
__I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */
__I RAMECC_ERRADDR_Type ERRADDR; /**< \brief Offset: 0x4 (R/ 32) Error Address */
RoReg8 Reserved1[0x7];
__IO RAMECC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0xF (R/W 8) Debug Control */
} Ramecc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_RAMECC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for RSTC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_RSTC_COMPONENT_
#define _SAMD51_RSTC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR RSTC */
/* ========================================================================== */
/** \addtogroup SAMD51_RSTC Reset Controller */
/*@{*/
#define RSTC_U2239
#define REV_RSTC 0x400
/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */
uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */
uint8_t NVM:1; /*!< bit: 3 NVM Reset */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t BACKUP:1; /*!< bit: 7 Backup Reset */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RSTC_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */
#define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */
#define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos)
#define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
#define RSTC_RCAUSE_BODCORE (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos)
#define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
#define RSTC_RCAUSE_BODVDD (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos)
#define RSTC_RCAUSE_NVM_Pos 3 /**< \brief (RSTC_RCAUSE) NVM Reset */
#define RSTC_RCAUSE_NVM (_U_(0x1) << RSTC_RCAUSE_NVM_Pos)
#define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */
#define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos)
#define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */
#define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos)
#define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */
#define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos)
#define RSTC_RCAUSE_BACKUP_Pos 7 /**< \brief (RSTC_RCAUSE) Backup Reset */
#define RSTC_RCAUSE_BACKUP (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos)
#define RSTC_RCAUSE_MASK _U_(0xFF) /**< \brief (RSTC_RCAUSE) MASK Register */
/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) (R/ 8) Backup Exit Source -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t RTC:1; /*!< bit: 1 Real Timer Counter Interrupt */
uint8_t BBPS:1; /*!< bit: 2 Battery Backup Power Switch */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t HIB:1; /*!< bit: 7 Hibernate */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RSTC_BKUPEXIT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSTC_BKUPEXIT_OFFSET 0x02 /**< \brief (RSTC_BKUPEXIT offset) Backup Exit Source */
#define RSTC_BKUPEXIT_RESETVALUE _U_(0x00) /**< \brief (RSTC_BKUPEXIT reset_value) Backup Exit Source */
#define RSTC_BKUPEXIT_RTC_Pos 1 /**< \brief (RSTC_BKUPEXIT) Real Timer Counter Interrupt */
#define RSTC_BKUPEXIT_RTC (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos)
#define RSTC_BKUPEXIT_BBPS_Pos 2 /**< \brief (RSTC_BKUPEXIT) Battery Backup Power Switch */
#define RSTC_BKUPEXIT_BBPS (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos)
#define RSTC_BKUPEXIT_HIB_Pos 7 /**< \brief (RSTC_BKUPEXIT) Hibernate */
#define RSTC_BKUPEXIT_HIB (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos)
#define RSTC_BKUPEXIT_MASK _U_(0x86) /**< \brief (RSTC_BKUPEXIT) MASK Register */
/** \brief RSTC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */
RoReg8 Reserved1[0x1];
__I RSTC_BKUPEXIT_Type BKUPEXIT; /**< \brief Offset: 0x02 (R/ 8) Backup Exit Source */
} Rstc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_RSTC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for SUPC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_SUPC_COMPONENT_
#define _SAMD51_SUPC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SUPC */
/* ========================================================================== */
/** \addtogroup SAMD51_SUPC Supply Controller */
/*@{*/
#define SUPC_U2407
#define REV_SUPC 0x100
/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
uint32_t :1; /*!< bit: 9 Reserved */
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
uint32_t :21; /*!< bit: 11..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */
#define SUPC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */
#define SUPC_INTENCLR_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENCLR) BOD33 Ready */
#define SUPC_INTENCLR_BOD33RDY (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos)
#define SUPC_INTENCLR_BOD33DET_Pos 1 /**< \brief (SUPC_INTENCLR) BOD33 Detection */
#define SUPC_INTENCLR_BOD33DET (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos)
#define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */
#define SUPC_INTENCLR_B33SRDY (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos)
#define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */
#define SUPC_INTENCLR_BOD12RDY (_U_(0x1) << SUPC_INTENCLR_BOD12RDY_Pos)
#define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */
#define SUPC_INTENCLR_BOD12DET (_U_(0x1) << SUPC_INTENCLR_BOD12DET_Pos)
#define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */
#define SUPC_INTENCLR_B12SRDY (_U_(0x1) << SUPC_INTENCLR_B12SRDY_Pos)
#define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */
#define SUPC_INTENCLR_VREGRDY (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos)
#define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */
#define SUPC_INTENCLR_VCORERDY (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos)
#define SUPC_INTENCLR_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENCLR) MASK Register */
/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
uint32_t :1; /*!< bit: 9 Reserved */
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
uint32_t :21; /*!< bit: 11..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */
#define SUPC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */
#define SUPC_INTENSET_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENSET) BOD33 Ready */
#define SUPC_INTENSET_BOD33RDY (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos)
#define SUPC_INTENSET_BOD33DET_Pos 1 /**< \brief (SUPC_INTENSET) BOD33 Detection */
#define SUPC_INTENSET_BOD33DET (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos)
#define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */
#define SUPC_INTENSET_B33SRDY (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos)
#define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */
#define SUPC_INTENSET_BOD12RDY (_U_(0x1) << SUPC_INTENSET_BOD12RDY_Pos)
#define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */
#define SUPC_INTENSET_BOD12DET (_U_(0x1) << SUPC_INTENSET_BOD12DET_Pos)
#define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */
#define SUPC_INTENSET_B12SRDY (_U_(0x1) << SUPC_INTENSET_B12SRDY_Pos)
#define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */
#define SUPC_INTENSET_VREGRDY (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos)
#define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */
#define SUPC_INTENSET_VCORERDY (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos)
#define SUPC_INTENSET_MASK _U_(0x0000053F) /**< \brief (SUPC_INTENSET) MASK Register */
/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
__I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
__I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
__I uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
__I uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
__I uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
__I uint32_t :2; /*!< bit: 6.. 7 Reserved */
__I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
__I uint32_t :1; /*!< bit: 9 Reserved */
__I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
__I uint32_t :21; /*!< bit: 11..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */
#define SUPC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define SUPC_INTFLAG_BOD33RDY_Pos 0 /**< \brief (SUPC_INTFLAG) BOD33 Ready */
#define SUPC_INTFLAG_BOD33RDY (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos)
#define SUPC_INTFLAG_BOD33DET_Pos 1 /**< \brief (SUPC_INTFLAG) BOD33 Detection */
#define SUPC_INTFLAG_BOD33DET (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos)
#define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */
#define SUPC_INTFLAG_B33SRDY (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos)
#define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */
#define SUPC_INTFLAG_BOD12RDY (_U_(0x1) << SUPC_INTFLAG_BOD12RDY_Pos)
#define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */
#define SUPC_INTFLAG_BOD12DET (_U_(0x1) << SUPC_INTFLAG_BOD12DET_Pos)
#define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */
#define SUPC_INTFLAG_B12SRDY (_U_(0x1) << SUPC_INTFLAG_B12SRDY_Pos)
#define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */
#define SUPC_INTFLAG_VREGRDY (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos)
#define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */
#define SUPC_INTFLAG_VCORERDY (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos)
#define SUPC_INTFLAG_MASK _U_(0x0000053F) /**< \brief (SUPC_INTFLAG) MASK Register */
/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */
uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */
uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
uint32_t :1; /*!< bit: 9 Reserved */
uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
uint32_t :21; /*!< bit: 11..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */
#define SUPC_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */
#define SUPC_STATUS_BOD33RDY_Pos 0 /**< \brief (SUPC_STATUS) BOD33 Ready */
#define SUPC_STATUS_BOD33RDY (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos)
#define SUPC_STATUS_BOD33DET_Pos 1 /**< \brief (SUPC_STATUS) BOD33 Detection */
#define SUPC_STATUS_BOD33DET (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos)
#define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */
#define SUPC_STATUS_B33SRDY (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos)
#define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */
#define SUPC_STATUS_BOD12RDY (_U_(0x1) << SUPC_STATUS_BOD12RDY_Pos)
#define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */
#define SUPC_STATUS_BOD12DET (_U_(0x1) << SUPC_STATUS_BOD12DET_Pos)
#define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */
#define SUPC_STATUS_B12SRDY (_U_(0x1) << SUPC_STATUS_B12SRDY_Pos)
#define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */
#define SUPC_STATUS_VREGRDY (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos)
#define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */
#define SUPC_STATUS_VCORERDY (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos)
#define SUPC_STATUS_MASK _U_(0x0000053F) /**< \brief (SUPC_STATUS) MASK Register */
/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t ACTION:2; /*!< bit: 2.. 3 Action when Threshold Crossed */
uint32_t STDBYCFG:1; /*!< bit: 4 Configuration in Standby mode */
uint32_t RUNSTDBY:1; /*!< bit: 5 Run in Standby mode */
uint32_t RUNHIB:1; /*!< bit: 6 Run in Hibernate mode */
uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */
uint32_t HYST:4; /*!< bit: 8..11 Hysteresis value */
uint32_t PSEL:3; /*!< bit: 12..14 Prescaler Select */
uint32_t :1; /*!< bit: 15 Reserved */
uint32_t LEVEL:8; /*!< bit: 16..23 Threshold Level for VDD */
uint32_t VBATLEVEL:8; /*!< bit: 24..31 Threshold Level in battery backup sleep mode for VBAT */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_BOD33_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_BOD33_OFFSET 0x10 /**< \brief (SUPC_BOD33 offset) BOD33 Control */
#define SUPC_BOD33_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */
#define SUPC_BOD33_ENABLE_Pos 1 /**< \brief (SUPC_BOD33) Enable */
#define SUPC_BOD33_ENABLE (_U_(0x1) << SUPC_BOD33_ENABLE_Pos)
#define SUPC_BOD33_ACTION_Pos 2 /**< \brief (SUPC_BOD33) Action when Threshold Crossed */
#define SUPC_BOD33_ACTION_Msk (_U_(0x3) << SUPC_BOD33_ACTION_Pos)
#define SUPC_BOD33_ACTION(value) (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))
#define SUPC_BOD33_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD33) No action */
#define SUPC_BOD33_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD33) The BOD33 generates a reset */
#define SUPC_BOD33_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */
#define SUPC_BOD33_ACTION_BKUP_Val _U_(0x3) /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode */
#define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos)
#define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos)
#define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos)
#define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos)
#define SUPC_BOD33_STDBYCFG_Pos 4 /**< \brief (SUPC_BOD33) Configuration in Standby mode */
#define SUPC_BOD33_STDBYCFG (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos)
#define SUPC_BOD33_RUNSTDBY_Pos 5 /**< \brief (SUPC_BOD33) Run in Standby mode */
#define SUPC_BOD33_RUNSTDBY (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos)
#define SUPC_BOD33_RUNHIB_Pos 6 /**< \brief (SUPC_BOD33) Run in Hibernate mode */
#define SUPC_BOD33_RUNHIB (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos)
#define SUPC_BOD33_RUNBKUP_Pos 7 /**< \brief (SUPC_BOD33) Run in Backup mode */
#define SUPC_BOD33_RUNBKUP (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos)
#define SUPC_BOD33_HYST_Pos 8 /**< \brief (SUPC_BOD33) Hysteresis value */
#define SUPC_BOD33_HYST_Msk (_U_(0xF) << SUPC_BOD33_HYST_Pos)
#define SUPC_BOD33_HYST(value) (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos))
#define SUPC_BOD33_PSEL_Pos 12 /**< \brief (SUPC_BOD33) Prescaler Select */
#define SUPC_BOD33_PSEL_Msk (_U_(0x7) << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_PSEL(value) (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))
#define SUPC_BOD33_PSEL_NODIV_Val _U_(0x0) /**< \brief (SUPC_BOD33) Not divided */
#define SUPC_BOD33_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD33) Divide clock by 4 */
#define SUPC_BOD33_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD33) Divide clock by 8 */
#define SUPC_BOD33_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD33) Divide clock by 16 */
#define SUPC_BOD33_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD33) Divide clock by 32 */
#define SUPC_BOD33_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD33) Divide clock by 64 */
#define SUPC_BOD33_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD33) Divide clock by 128 */
#define SUPC_BOD33_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD33) Divide clock by 256 */
#define SUPC_BOD33_PSEL_NODIV (SUPC_BOD33_PSEL_NODIV_Val << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos)
#define SUPC_BOD33_LEVEL_Pos 16 /**< \brief (SUPC_BOD33) Threshold Level for VDD */
#define SUPC_BOD33_LEVEL_Msk (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos)
#define SUPC_BOD33_LEVEL(value) (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))
#define SUPC_BOD33_VBATLEVEL_Pos 24 /**< \brief (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT */
#define SUPC_BOD33_VBATLEVEL_Msk (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos)
#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))
#define SUPC_BOD33_MASK _U_(0xFFFF7FFE) /**< \brief (SUPC_BOD33) MASK Register */
/* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */
uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */
uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */
uint32_t :3; /*!< bit: 9..11 Reserved */
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_BOD12_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */
#define SUPC_BOD12_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */
#define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */
#define SUPC_BOD12_ENABLE (_U_(0x1) << SUPC_BOD12_ENABLE_Pos)
#define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */
#define SUPC_BOD12_HYST (_U_(0x1) << SUPC_BOD12_HYST_Pos)
#define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */
#define SUPC_BOD12_ACTION_Msk (_U_(0x3) << SUPC_BOD12_ACTION_Pos)
#define SUPC_BOD12_ACTION(value) (SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))
#define SUPC_BOD12_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BOD12) No action */
#define SUPC_BOD12_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BOD12) The BOD12 generates a reset */
#define SUPC_BOD12_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */
#define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos)
#define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos)
#define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos)
#define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */
#define SUPC_BOD12_STDBYCFG (_U_(0x1) << SUPC_BOD12_STDBYCFG_Pos)
#define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */
#define SUPC_BOD12_RUNSTDBY (_U_(0x1) << SUPC_BOD12_RUNSTDBY_Pos)
#define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */
#define SUPC_BOD12_ACTCFG (_U_(0x1) << SUPC_BOD12_ACTCFG_Pos)
#define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */
#define SUPC_BOD12_PSEL_Msk (_U_(0xF) << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL(value) (SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))
#define SUPC_BOD12_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BOD12) Divide clock by 2 */
#define SUPC_BOD12_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BOD12) Divide clock by 4 */
#define SUPC_BOD12_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BOD12) Divide clock by 8 */
#define SUPC_BOD12_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BOD12) Divide clock by 16 */
#define SUPC_BOD12_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BOD12) Divide clock by 32 */
#define SUPC_BOD12_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BOD12) Divide clock by 64 */
#define SUPC_BOD12_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BOD12) Divide clock by 128 */
#define SUPC_BOD12_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BOD12) Divide clock by 256 */
#define SUPC_BOD12_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BOD12) Divide clock by 512 */
#define SUPC_BOD12_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BOD12) Divide clock by 1024 */
#define SUPC_BOD12_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BOD12) Divide clock by 2048 */
#define SUPC_BOD12_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BOD12) Divide clock by 4096 */
#define SUPC_BOD12_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BOD12) Divide clock by 8192 */
#define SUPC_BOD12_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BOD12) Divide clock by 16384 */
#define SUPC_BOD12_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BOD12) Divide clock by 32768 */
#define SUPC_BOD12_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BOD12) Divide clock by 65536 */
#define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos)
#define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */
#define SUPC_BOD12_LEVEL_Msk (_U_(0x3F) << SUPC_BOD12_LEVEL_Pos)
#define SUPC_BOD12_LEVEL(value) (SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))
#define SUPC_BOD12_MASK _U_(0x003FF17E) /**< \brief (SUPC_BOD12) MASK Register */
/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t SEL:1; /*!< bit: 2 Voltage Regulator Selection */
uint32_t :4; /*!< bit: 3.. 6 Reserved */
uint32_t RUNBKUP:1; /*!< bit: 7 Run in Backup mode */
uint32_t :8; /*!< bit: 8..15 Reserved */
uint32_t VSEN:1; /*!< bit: 16 Voltage Scaling Enable */
uint32_t :7; /*!< bit: 17..23 Reserved */
uint32_t VSPER:3; /*!< bit: 24..26 Voltage Scaling Period */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */
#define SUPC_VREG_RESETVALUE _U_(0x00000002) /**< \brief (SUPC_VREG reset_value) VREG Control */
#define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */
#define SUPC_VREG_ENABLE (_U_(0x1) << SUPC_VREG_ENABLE_Pos)
#define SUPC_VREG_SEL_Pos 2 /**< \brief (SUPC_VREG) Voltage Regulator Selection */
#define SUPC_VREG_SEL (_U_(0x1) << SUPC_VREG_SEL_Pos)
#define SUPC_VREG_SEL_LDO_Val _U_(0x0) /**< \brief (SUPC_VREG) LDO selection */
#define SUPC_VREG_SEL_BUCK_Val _U_(0x1) /**< \brief (SUPC_VREG) Buck selection */
#define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos)
#define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos)
#define SUPC_VREG_RUNBKUP_Pos 7 /**< \brief (SUPC_VREG) Run in Backup mode */
#define SUPC_VREG_RUNBKUP (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos)
#define SUPC_VREG_VSEN_Pos 16 /**< \brief (SUPC_VREG) Voltage Scaling Enable */
#define SUPC_VREG_VSEN (_U_(0x1) << SUPC_VREG_VSEN_Pos)
#define SUPC_VREG_VSPER_Pos 24 /**< \brief (SUPC_VREG) Voltage Scaling Period */
#define SUPC_VREG_VSPER_Msk (_U_(0x7) << SUPC_VREG_VSPER_Pos)
#define SUPC_VREG_VSPER(value) (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))
#define SUPC_VREG_MASK _U_(0x07010086) /**< \brief (SUPC_VREG) MASK Register */
/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */
uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */
uint32_t TSSEL:1; /*!< bit: 3 Temperature Sensor Selection */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */
uint32_t :8; /*!< bit: 8..15 Reserved */
uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */
#define SUPC_VREF_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */
#define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */
#define SUPC_VREF_TSEN (_U_(0x1) << SUPC_VREF_TSEN_Pos)
#define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */
#define SUPC_VREF_VREFOE (_U_(0x1) << SUPC_VREF_VREFOE_Pos)
#define SUPC_VREF_TSSEL_Pos 3 /**< \brief (SUPC_VREF) Temperature Sensor Selection */
#define SUPC_VREF_TSSEL (_U_(0x1) << SUPC_VREF_TSSEL_Pos)
#define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */
#define SUPC_VREF_RUNSTDBY (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos)
#define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */
#define SUPC_VREF_ONDEMAND (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos)
#define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */
#define SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))
#define SUPC_VREF_SEL_1V0_Val _U_(0x0) /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */
#define SUPC_VREF_SEL_1V1_Val _U_(0x1) /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */
#define SUPC_VREF_SEL_1V2_Val _U_(0x2) /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */
#define SUPC_VREF_SEL_1V25_Val _U_(0x3) /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */
#define SUPC_VREF_SEL_2V0_Val _U_(0x4) /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */
#define SUPC_VREF_SEL_2V2_Val _U_(0x5) /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */
#define SUPC_VREF_SEL_2V4_Val _U_(0x6) /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */
#define SUPC_VREF_SEL_2V5_Val _U_(0x7) /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */
#define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_MASK _U_(0x000F00CE) /**< \brief (SUPC_VREF) MASK Register */
/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CONF:1; /*!< bit: 0 Battery Backup Configuration */
uint32_t :1; /*!< bit: 1 Reserved */
uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_BBPS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_BBPS_OFFSET 0x20 /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */
#define SUPC_BBPS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */
#define SUPC_BBPS_CONF_Pos 0 /**< \brief (SUPC_BBPS) Battery Backup Configuration */
#define SUPC_BBPS_CONF (_U_(0x1) << SUPC_BBPS_CONF_Pos)
#define SUPC_BBPS_CONF_BOD33_Val _U_(0x0) /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */
#define SUPC_BBPS_CONF_FORCED_Val _U_(0x1) /**< \brief (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power */
#define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos)
#define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos)
#define SUPC_BBPS_WAKEEN_Pos 2 /**< \brief (SUPC_BBPS) Wake Enable */
#define SUPC_BBPS_WAKEEN (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos)
#define SUPC_BBPS_MASK _U_(0x00000005) /**< \brief (SUPC_BBPS) MASK Register */
/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */
uint32_t :6; /*!< bit: 2.. 7 Reserved */
uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t SET:2; /*!< bit: 16..17 Set Output */
uint32_t :6; /*!< bit: 18..23 Reserved */
uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */
uint32_t :6; /*!< bit: 26..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_BKOUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_BKOUT_OFFSET 0x24 /**< \brief (SUPC_BKOUT offset) Backup Output Control */
#define SUPC_BKOUT_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */
#define SUPC_BKOUT_EN_Pos 0 /**< \brief (SUPC_BKOUT) Enable Output */
#define SUPC_BKOUT_EN_Msk (_U_(0x3) << SUPC_BKOUT_EN_Pos)
#define SUPC_BKOUT_EN(value) (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))
#define SUPC_BKOUT_CLR_Pos 8 /**< \brief (SUPC_BKOUT) Clear Output */
#define SUPC_BKOUT_CLR_Msk (_U_(0x3) << SUPC_BKOUT_CLR_Pos)
#define SUPC_BKOUT_CLR(value) (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))
#define SUPC_BKOUT_SET_Pos 16 /**< \brief (SUPC_BKOUT) Set Output */
#define SUPC_BKOUT_SET_Msk (_U_(0x3) << SUPC_BKOUT_SET_Pos)
#define SUPC_BKOUT_SET(value) (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))
#define SUPC_BKOUT_RTCTGL_Pos 24 /**< \brief (SUPC_BKOUT) RTC Toggle Output */
#define SUPC_BKOUT_RTCTGL_Msk (_U_(0x3) << SUPC_BKOUT_RTCTGL_Pos)
#define SUPC_BKOUT_RTCTGL(value) (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))
#define SUPC_BKOUT_MASK _U_(0x03030303) /**< \brief (SUPC_BKOUT) MASK Register */
/* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/ 32) Backup Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_BKIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_BKIN_OFFSET 0x28 /**< \brief (SUPC_BKIN offset) Backup Input Control */
#define SUPC_BKIN_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BKIN reset_value) Backup Input Control */
#define SUPC_BKIN_BKIN_Pos 0 /**< \brief (SUPC_BKIN) Backup Input Value */
#define SUPC_BKIN_BKIN_Msk (_U_(0xFF) << SUPC_BKIN_BKIN_Pos)
#define SUPC_BKIN_BKIN(value) (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))
#define SUPC_BKIN_MASK _U_(0x000000FF) /**< \brief (SUPC_BKIN) MASK Register */
/** \brief SUPC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */
__IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */
__IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */
__IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */
__IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */
__IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */
__I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */
} Supc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_SUPC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for TC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_TC_COMPONENT_
#define _SAMD51_TC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR TC */
/* ========================================================================== */
/** \addtogroup SAMD51_TC Basic Timer Counter */
/*@{*/
#define TC_U2249
#define REV_TC 0x300
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */
uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */
uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */
uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */
uint32_t :2; /*!< bit: 18..19 Reserved */
uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */
uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */
uint32_t :2; /*!< bit: 22..23 Reserved */
uint32_t CAPTMODE0:2; /*!< bit: 24..25 Capture Mode Channel 0 */
uint32_t :1; /*!< bit: 26 Reserved */
uint32_t CAPTMODE1:2; /*!< bit: 27..28 Capture mode Channel 1 */
uint32_t :3; /*!< bit: 29..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */
uint32_t :2; /*!< bit: 18..19 Reserved */
uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */
uint32_t :10; /*!< bit: 22..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
#define TC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */
#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
#define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos)
#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
#define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */
#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */
#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */
#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */
#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */
#define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
#define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */
#define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */
#define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
#define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */
#define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
#define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */
#define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
#define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */
#define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
#define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
#define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */
#define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos)
#define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */
#define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos)
#define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */
#define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos)
#define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
#define TC_CTRLA_CAPTMODE0_Pos 24 /**< \brief (TC_CTRLA) Capture Mode Channel 0 */
#define TC_CTRLA_CAPTMODE0_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
#define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
#define TC_CTRLA_CAPTMODE0_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
#define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
#define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
#define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
#define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
#define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
#define TC_CTRLA_CAPTMODE1_Pos 27 /**< \brief (TC_CTRLA) Capture mode Channel 1 */
#define TC_CTRLA_CAPTMODE1_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
#define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
#define TC_CTRLA_CAPTMODE1_DEFAULT_Val _U_(0x0) /**< \brief (TC_CTRLA) Default capture */
#define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _U_(0x1) /**< \brief (TC_CTRLA) Minimum capture */
#define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _U_(0x2) /**< \brief (TC_CTRLA) Maximum capture */
#define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
#define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
#define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
#define TC_CTRLA_MASK _U_(0x1B330FFF) /**< \brief (TC_CTRLA) MASK Register */
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t LUPD:1; /*!< bit: 1 Lock Update */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
uint8_t :2; /*!< bit: 3.. 4 Reserved */
uint8_t CMD:3; /*!< bit: 5.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
#define TC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
#define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
#define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */
#define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */
#define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
#define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */
#define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBCLR) No action */
#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBCLR) Force a stop */
#define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */
#define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */
#define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */
#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_MASK _U_(0xE7) /**< \brief (TC_CTRLBCLR) MASK Register */
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t LUPD:1; /*!< bit: 1 Lock Update */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
uint8_t :2; /*!< bit: 3.. 4 Reserved */
uint8_t CMD:3; /*!< bit: 5.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
#define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */
#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
#define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
#define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */
#define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */
#define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
#define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */
#define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBSET) No action */
#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBSET) Force a stop */
#define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBSET) Force update of double-buffered register */
#define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */
#define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBSET) One-shot DMA trigger */
#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_MASK _U_(0xE7) /**< \brief (TC_CTRLBSET) MASK Register */
/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */
uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */
uint16_t :3; /*!< bit: 9..11 Reserved */
uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */
uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */
#define TC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */
#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (TC_EVCTRL) Event action disabled */
#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (TC_EVCTRL) Count on event */
#define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< \brief (TC_EVCTRL) Start TC on event */
#define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4) /**< \brief (TC_EVCTRL) Time stamp capture */
#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
#define TC_EVCTRL_EVACT_PW_Val _U_(0x7) /**< \brief (TC_EVCTRL) Pulse width capture */
#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */
#define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */
#define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */
#define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */
#define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos)
#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */
#define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos)
#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */
#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
#define TC_EVCTRL_MASK _U_(0x3137) /**< \brief (TC_EVCTRL) MASK Register */
/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */
uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */
uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
#define TC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */
#define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos)
#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */
#define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos)
#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */
#define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos)
#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */
#define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos)
#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */
#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos)
#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
#define TC_INTENCLR_MASK _U_(0x33) /**< \brief (TC_INTENCLR) MASK Register */
/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */
uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
#define TC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */
#define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos)
#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */
#define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos)
#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */
#define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos)
#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */
#define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos)
#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */
#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos)
#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
#define TC_INTENSET_MASK _U_(0x33) /**< \brief (TC_INTENSET) MASK Register */
/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */
__I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
__I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */
__I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t :4; /*!< bit: 0.. 3 Reserved */
__I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
#define TC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */
#define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos)
#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */
#define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos)
#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */
#define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos)
#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */
#define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos)
#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */
#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos)
#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
#define TC_INTFLAG_MASK _U_(0x33) /**< \brief (TC_INTFLAG) MASK Register */
/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */
uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */
uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */
uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */
#define TC_STATUS_RESETVALUE _U_(0x01) /**< \brief (TC_STATUS reset_value) Status */
#define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */
#define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos)
#define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */
#define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos)
#define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */
#define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
#define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */
#define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos)
#define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */
#define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos)
#define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */
#define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
#define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
#define TC_STATUS_MASK _U_(0x3B) /**< \brief (TC_STATUS) MASK Register */
/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */
#define TC_WAVE_RESETVALUE _U_(0x00) /**< \brief (TC_WAVE reset_value) Waveform Generation Control */
#define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */
#define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
#define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TC_WAVE) Normal frequency */
#define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TC_WAVE) Match frequency */
#define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TC_WAVE) Normal PWM */
#define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3) /**< \brief (TC_WAVE) Match PWM */
#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_MASK _U_(0x03) /**< \brief (TC_WAVE) MASK Register */
/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */
uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */
#define TC_DRVCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DRVCTRL reset_value) Control C */
#define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */
#define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
#define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */
#define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
#define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */
#define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
#define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
#define TC_DRVCTRL_MASK _U_(0x03) /**< \brief (TC_DRVCTRL) MASK Register */
/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */
#define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */
#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */
#define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
#define TC_DBGCTRL_MASK _U_(0x01) /**< \brief (TC_DBGCTRL) MASK Register */
/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 swrst */
uint32_t ENABLE:1; /*!< bit: 1 enable */
uint32_t CTRLB:1; /*!< bit: 2 CTRLB */
uint32_t STATUS:1; /*!< bit: 3 STATUS */
uint32_t COUNT:1; /*!< bit: 4 Counter */
uint32_t PER:1; /*!< bit: 5 Period */
uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */
uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :6; /*!< bit: 0.. 5 Reserved */
uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */
uint32_t :24; /*!< bit: 8..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} TC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */
#define TC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */
#define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */
#define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
#define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */
#define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
#define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */
#define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
#define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */
#define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
#define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */
#define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
#define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */
#define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
#define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */
#define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos)
#define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */
#define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos)
#define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */
#define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
#define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
#define TC_SYNCBUSY_MASK _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */
#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */
#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */
#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
#define TC_COUNT16_COUNT_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */
#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */
#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */
#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
#define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */
#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */
#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
#define TC_COUNT8_COUNT_MASK _U_(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */
/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */
#define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */
#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
#define TC_COUNT8_PER_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */
/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */
#define TC_COUNT16_CC_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */
#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */
#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
#define TC_COUNT16_CC_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */
/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */
#define TC_COUNT32_CC_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */
#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */
#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
#define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */
#define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */
#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */
#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
#define TC_COUNT8_CC_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */
/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PERBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */
#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */
#define TC_COUNT8_PERBUF_PERBUF_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */
#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
#define TC_COUNT8_PERBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF) MASK Register */
/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */
#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */
#define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */
#define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
#define TC_COUNT16_CCBUF_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CCBUF) MASK Register */
/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */
#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */
#define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */
#define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
#define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */
/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */
#define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */
#define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */
#define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
#define TC_COUNT8_CCBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CCBUF) MASK Register */
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
__IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
__I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
__IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */
RoReg8 Reserved2[0x6];
__IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */
__IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */
RoReg8 Reserved3[0x11];
__IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */
__IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
__IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
__I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
__IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */
RoReg8 Reserved2[0x6];
__IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
RoReg8 Reserved3[0x10];
__IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
__IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
__I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
__IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */
RoReg8 Reserved2[0x4];
__IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
RoReg8 Reserved3[0xC];
__IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_TC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for TRNG
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_TRNG_COMPONENT_
#define _SAMD51_TRNG_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR TRNG */
/* ========================================================================== */
/** \addtogroup SAMD51_TRNG True Random Generator */
/*@{*/
#define TRNG_U2242
#define REV_TRNG 0x110
/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TRNG_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */
#define TRNG_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TRNG_CTRLA reset_value) Control A */
#define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */
#define TRNG_CTRLA_ENABLE (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos)
#define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */
#define TRNG_CTRLA_RUNSTDBY (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos)
#define TRNG_CTRLA_MASK _U_(0x42) /**< \brief (TRNG_CTRLA) MASK Register */
/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TRNG_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */
#define TRNG_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (TRNG_EVCTRL reset_value) Event Control */
#define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */
#define TRNG_EVCTRL_DATARDYEO (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos)
#define TRNG_EVCTRL_MASK _U_(0x01) /**< \brief (TRNG_EVCTRL) MASK Register */
/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TRNG_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */
#define TRNG_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */
#define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */
#define TRNG_INTENCLR_DATARDY (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos)
#define TRNG_INTENCLR_MASK _U_(0x01) /**< \brief (TRNG_INTENCLR) MASK Register */
/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TRNG_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */
#define TRNG_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */
#define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */
#define TRNG_INTENSET_DATARDY (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos)
#define TRNG_INTENSET_MASK _U_(0x01) /**< \brief (TRNG_INTENSET) MASK Register */
/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TRNG_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */
#define TRNG_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */
#define TRNG_INTFLAG_DATARDY (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos)
#define TRNG_INTFLAG_MASK _U_(0x01) /**< \brief (TRNG_INTFLAG) MASK Register */
/* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Output Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TRNG_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */
#define TRNG_DATA_RESETVALUE _U_(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */
#define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */
#define TRNG_DATA_DATA_Msk (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos)
#define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
#define TRNG_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */
/** \brief TRNG hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
RoReg8 Reserved1[0x3];
__IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */
RoReg8 Reserved2[0x3];
__IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved3[0x15];
__I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */
} Trng;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_TRNG_COMPONENT_ */

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/**
* \file
*
* \brief Component description for WDT
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_WDT_COMPONENT_
#define _SAMD51_WDT_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR WDT */
/* ========================================================================== */
/** \addtogroup SAMD51_WDT Watchdog Timer */
/*@{*/
#define WDT_U2251
#define REV_WDT 0x110
/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */
#define WDT_CTRLA_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRLA reset_value) Control */
#define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */
#define WDT_CTRLA_ENABLE (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
#define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */
#define WDT_CTRLA_WEN (_U_(0x1) << WDT_CTRLA_WEN_Pos)
#define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */
#define WDT_CTRLA_ALWAYSON (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
#define WDT_CTRLA_MASK _U_(0x86) /**< \brief (WDT_CTRLA) MASK Register */
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
#define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */
#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
#define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
#define WDT_CONFIG_PER_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
#define WDT_CONFIG_PER_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
#define WDT_CONFIG_PER_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
#define WDT_CONFIG_PER_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
#define WDT_CONFIG_PER_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
#define WDT_CONFIG_PER_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
#define WDT_CONFIG_PER_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
#define WDT_CONFIG_PER_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
#define WDT_CONFIG_PER_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
#define WDT_CONFIG_PER_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
#define WDT_CONFIG_PER_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
#define WDT_CONFIG_PER_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
#define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
#define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
#define WDT_CONFIG_WINDOW_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
#define WDT_CONFIG_WINDOW_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
#define WDT_CONFIG_WINDOW_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
#define WDT_CONFIG_WINDOW_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
#define WDT_CONFIG_WINDOW_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
#define WDT_CONFIG_WINDOW_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
#define WDT_CONFIG_WINDOW_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
#define WDT_CONFIG_WINDOW_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
#define WDT_CONFIG_WINDOW_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
#define WDT_CONFIG_WINDOW_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
#define WDT_CONFIG_WINDOW_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
#define WDT_CONFIG_WINDOW_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
#define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
#define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
#define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
#define WDT_EWCTRL_EWOFFSET_CYC8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
#define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
#define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
#define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
#define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
#define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
#define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t EW:1; /*!< bit: 0 Early Warning */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
#define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
#define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
#define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */
/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
uint32_t WEN:1; /*!< bit: 2 Window Enable Synchronization Busy */
uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Synchronization Busy */
uint32_t CLEAR:1; /*!< bit: 4 Clear Synchronization Busy */
uint32_t :27; /*!< bit: 5..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} WDT_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */
#define WDT_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */
#define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Synchronization Busy */
#define WDT_SYNCBUSY_ENABLE (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
#define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Synchronization Busy */
#define WDT_SYNCBUSY_WEN (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
#define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Synchronization Busy */
#define WDT_SYNCBUSY_ALWAYSON (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
#define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Synchronization Busy */
#define WDT_SYNCBUSY_CLEAR (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
#define WDT_SYNCBUSY_MASK _U_(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */
/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */
#define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */
#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
#define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
#define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */
#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
#define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
RoReg8 Reserved1[0x1];
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved2[0x1];
__I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD51_WDT_COMPONENT_ */

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/**
* \file
*
* \brief Instance description for AC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_AC_INSTANCE_
#define _SAMD51_AC_INSTANCE_
/* ========== Register definition for AC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AC_CTRLA (0x42002000) /**< \brief (AC) Control A */
#define REG_AC_CTRLB (0x42002001) /**< \brief (AC) Control B */
#define REG_AC_EVCTRL (0x42002002) /**< \brief (AC) Event Control */
#define REG_AC_INTENCLR (0x42002004) /**< \brief (AC) Interrupt Enable Clear */
#define REG_AC_INTENSET (0x42002005) /**< \brief (AC) Interrupt Enable Set */
#define REG_AC_INTFLAG (0x42002006) /**< \brief (AC) Interrupt Flag Status and Clear */
#define REG_AC_STATUSA (0x42002007) /**< \brief (AC) Status A */
#define REG_AC_STATUSB (0x42002008) /**< \brief (AC) Status B */
#define REG_AC_DBGCTRL (0x42002009) /**< \brief (AC) Debug Control */
#define REG_AC_WINCTRL (0x4200200A) /**< \brief (AC) Window Control */
#define REG_AC_SCALER0 (0x4200200C) /**< \brief (AC) Scaler 0 */
#define REG_AC_SCALER1 (0x4200200D) /**< \brief (AC) Scaler 1 */
#define REG_AC_COMPCTRL0 (0x42002010) /**< \brief (AC) Comparator Control 0 */
#define REG_AC_COMPCTRL1 (0x42002014) /**< \brief (AC) Comparator Control 1 */
#define REG_AC_SYNCBUSY (0x42002020) /**< \brief (AC) Synchronization Busy */
#define REG_AC_CALIB (0x42002024) /**< \brief (AC) Calibration */
#else
#define REG_AC_CTRLA (*(RwReg8 *)0x42002000UL) /**< \brief (AC) Control A */
#define REG_AC_CTRLB (*(WoReg8 *)0x42002001UL) /**< \brief (AC) Control B */
#define REG_AC_EVCTRL (*(RwReg16*)0x42002002UL) /**< \brief (AC) Event Control */
#define REG_AC_INTENCLR (*(RwReg8 *)0x42002004UL) /**< \brief (AC) Interrupt Enable Clear */
#define REG_AC_INTENSET (*(RwReg8 *)0x42002005UL) /**< \brief (AC) Interrupt Enable Set */
#define REG_AC_INTFLAG (*(RwReg8 *)0x42002006UL) /**< \brief (AC) Interrupt Flag Status and Clear */
#define REG_AC_STATUSA (*(RoReg8 *)0x42002007UL) /**< \brief (AC) Status A */
#define REG_AC_STATUSB (*(RoReg8 *)0x42002008UL) /**< \brief (AC) Status B */
#define REG_AC_DBGCTRL (*(RwReg8 *)0x42002009UL) /**< \brief (AC) Debug Control */
#define REG_AC_WINCTRL (*(RwReg8 *)0x4200200AUL) /**< \brief (AC) Window Control */
#define REG_AC_SCALER0 (*(RwReg8 *)0x4200200CUL) /**< \brief (AC) Scaler 0 */
#define REG_AC_SCALER1 (*(RwReg8 *)0x4200200DUL) /**< \brief (AC) Scaler 1 */
#define REG_AC_COMPCTRL0 (*(RwReg *)0x42002010UL) /**< \brief (AC) Comparator Control 0 */
#define REG_AC_COMPCTRL1 (*(RwReg *)0x42002014UL) /**< \brief (AC) Comparator Control 1 */
#define REG_AC_SYNCBUSY (*(RoReg *)0x42002020UL) /**< \brief (AC) Synchronization Busy */
#define REG_AC_CALIB (*(RwReg16*)0x42002024UL) /**< \brief (AC) Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for AC peripheral ========== */
#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG
#define AC_FUSES_BIAS1 // PAIR1 Bias Calibration
#define AC_GCLK_ID 32 // Index of Generic Clock
#define AC_IMPLEMENTS_VDBLR 0 // VDoubler implemented ?
#define AC_NUM_CMP 2 // Number of comparators
#define AC_PAIRS 1 // Number of pairs of comparators
#define AC_SPEED_LEVELS 2 // Number of speed values
#endif /* _SAMD51_AC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for ADC0
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_ADC0_INSTANCE_
#define _SAMD51_ADC0_INSTANCE_
/* ========== Register definition for ADC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ADC0_CTRLA (0x43001C00) /**< \brief (ADC0) Control A */
#define REG_ADC0_EVCTRL (0x43001C02) /**< \brief (ADC0) Event Control */
#define REG_ADC0_DBGCTRL (0x43001C03) /**< \brief (ADC0) Debug Control */
#define REG_ADC0_INPUTCTRL (0x43001C04) /**< \brief (ADC0) Input Control */
#define REG_ADC0_CTRLB (0x43001C06) /**< \brief (ADC0) Control B */
#define REG_ADC0_REFCTRL (0x43001C08) /**< \brief (ADC0) Reference Control */
#define REG_ADC0_AVGCTRL (0x43001C0A) /**< \brief (ADC0) Average Control */
#define REG_ADC0_SAMPCTRL (0x43001C0B) /**< \brief (ADC0) Sample Time Control */
#define REG_ADC0_WINLT (0x43001C0C) /**< \brief (ADC0) Window Monitor Lower Threshold */
#define REG_ADC0_WINUT (0x43001C0E) /**< \brief (ADC0) Window Monitor Upper Threshold */
#define REG_ADC0_GAINCORR (0x43001C10) /**< \brief (ADC0) Gain Correction */
#define REG_ADC0_OFFSETCORR (0x43001C12) /**< \brief (ADC0) Offset Correction */
#define REG_ADC0_SWTRIG (0x43001C14) /**< \brief (ADC0) Software Trigger */
#define REG_ADC0_INTENCLR (0x43001C2C) /**< \brief (ADC0) Interrupt Enable Clear */
#define REG_ADC0_INTENSET (0x43001C2D) /**< \brief (ADC0) Interrupt Enable Set */
#define REG_ADC0_INTFLAG (0x43001C2E) /**< \brief (ADC0) Interrupt Flag Status and Clear */
#define REG_ADC0_STATUS (0x43001C2F) /**< \brief (ADC0) Status */
#define REG_ADC0_SYNCBUSY (0x43001C30) /**< \brief (ADC0) Synchronization Busy */
#define REG_ADC0_DSEQDATA (0x43001C34) /**< \brief (ADC0) DMA Sequencial Data */
#define REG_ADC0_DSEQCTRL (0x43001C38) /**< \brief (ADC0) DMA Sequential Control */
#define REG_ADC0_DSEQSTAT (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */
#define REG_ADC0_RESULT (0x43001C40) /**< \brief (ADC0) Result Conversion Value */
#define REG_ADC0_RESS (0x43001C44) /**< \brief (ADC0) Last Sample Result */
#define REG_ADC0_CALIB (0x43001C48) /**< \brief (ADC0) Calibration */
#else
#define REG_ADC0_CTRLA (*(RwReg16*)0x43001C00UL) /**< \brief (ADC0) Control A */
#define REG_ADC0_EVCTRL (*(RwReg8 *)0x43001C02UL) /**< \brief (ADC0) Event Control */
#define REG_ADC0_DBGCTRL (*(RwReg8 *)0x43001C03UL) /**< \brief (ADC0) Debug Control */
#define REG_ADC0_INPUTCTRL (*(RwReg16*)0x43001C04UL) /**< \brief (ADC0) Input Control */
#define REG_ADC0_CTRLB (*(RwReg16*)0x43001C06UL) /**< \brief (ADC0) Control B */
#define REG_ADC0_REFCTRL (*(RwReg8 *)0x43001C08UL) /**< \brief (ADC0) Reference Control */
#define REG_ADC0_AVGCTRL (*(RwReg8 *)0x43001C0AUL) /**< \brief (ADC0) Average Control */
#define REG_ADC0_SAMPCTRL (*(RwReg8 *)0x43001C0BUL) /**< \brief (ADC0) Sample Time Control */
#define REG_ADC0_WINLT (*(RwReg16*)0x43001C0CUL) /**< \brief (ADC0) Window Monitor Lower Threshold */
#define REG_ADC0_WINUT (*(RwReg16*)0x43001C0EUL) /**< \brief (ADC0) Window Monitor Upper Threshold */
#define REG_ADC0_GAINCORR (*(RwReg16*)0x43001C10UL) /**< \brief (ADC0) Gain Correction */
#define REG_ADC0_OFFSETCORR (*(RwReg16*)0x43001C12UL) /**< \brief (ADC0) Offset Correction */
#define REG_ADC0_SWTRIG (*(RwReg8 *)0x43001C14UL) /**< \brief (ADC0) Software Trigger */
#define REG_ADC0_INTENCLR (*(RwReg8 *)0x43001C2CUL) /**< \brief (ADC0) Interrupt Enable Clear */
#define REG_ADC0_INTENSET (*(RwReg8 *)0x43001C2DUL) /**< \brief (ADC0) Interrupt Enable Set */
#define REG_ADC0_INTFLAG (*(RwReg8 *)0x43001C2EUL) /**< \brief (ADC0) Interrupt Flag Status and Clear */
#define REG_ADC0_STATUS (*(RoReg8 *)0x43001C2FUL) /**< \brief (ADC0) Status */
#define REG_ADC0_SYNCBUSY (*(RoReg *)0x43001C30UL) /**< \brief (ADC0) Synchronization Busy */
#define REG_ADC0_DSEQDATA (*(WoReg *)0x43001C34UL) /**< \brief (ADC0) DMA Sequencial Data */
#define REG_ADC0_DSEQCTRL (*(RwReg *)0x43001C38UL) /**< \brief (ADC0) DMA Sequential Control */
#define REG_ADC0_DSEQSTAT (*(RoReg *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Status */
#define REG_ADC0_RESULT (*(RoReg16*)0x43001C40UL) /**< \brief (ADC0) Result Conversion Value */
#define REG_ADC0_RESS (*(RoReg16*)0x43001C44UL) /**< \brief (ADC0) Last Sample Result */
#define REG_ADC0_CALIB (*(RwReg16*)0x43001C48UL) /**< \brief (ADC0) Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for ADC0 peripheral ========== */
#define ADC0_BANDGAP 27 // MUXPOS value to select BANDGAP
#define ADC0_CTAT 29 // MUXPOS value to select CTAT
#define ADC0_DMAC_ID_RESRDY 68 // index of DMA RESRDY trigger
#define ADC0_DMAC_ID_SEQ 69 // Index of DMA SEQ trigger
#define ADC0_EXTCHANNEL_MSB 15 // Number of external channels
#define ADC0_GCLK_ID 40 // index of Generic Clock
#define ADC0_MASTER_SLAVE_MODE 1 // ADC Master/Slave Mode
#define ADC0_OPAMP2 0 // MUXPOS value to select OPAMP2
#define ADC0_OPAMP01 0 // MUXPOS value to select OPAMP01
#define ADC0_PTAT 28 // MUXPOS value to select PTAT
#define ADC0_TOUCH_IMPLEMENTED 1 // TOUCH implemented or not
#endif /* _SAMD51_ADC0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for ADC1
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_ADC1_INSTANCE_
#define _SAMD51_ADC1_INSTANCE_
/* ========== Register definition for ADC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ADC1_CTRLA (0x43002000) /**< \brief (ADC1) Control A */
#define REG_ADC1_EVCTRL (0x43002002) /**< \brief (ADC1) Event Control */
#define REG_ADC1_DBGCTRL (0x43002003) /**< \brief (ADC1) Debug Control */
#define REG_ADC1_INPUTCTRL (0x43002004) /**< \brief (ADC1) Input Control */
#define REG_ADC1_CTRLB (0x43002006) /**< \brief (ADC1) Control B */
#define REG_ADC1_REFCTRL (0x43002008) /**< \brief (ADC1) Reference Control */
#define REG_ADC1_AVGCTRL (0x4300200A) /**< \brief (ADC1) Average Control */
#define REG_ADC1_SAMPCTRL (0x4300200B) /**< \brief (ADC1) Sample Time Control */
#define REG_ADC1_WINLT (0x4300200C) /**< \brief (ADC1) Window Monitor Lower Threshold */
#define REG_ADC1_WINUT (0x4300200E) /**< \brief (ADC1) Window Monitor Upper Threshold */
#define REG_ADC1_GAINCORR (0x43002010) /**< \brief (ADC1) Gain Correction */
#define REG_ADC1_OFFSETCORR (0x43002012) /**< \brief (ADC1) Offset Correction */
#define REG_ADC1_SWTRIG (0x43002014) /**< \brief (ADC1) Software Trigger */
#define REG_ADC1_INTENCLR (0x4300202C) /**< \brief (ADC1) Interrupt Enable Clear */
#define REG_ADC1_INTENSET (0x4300202D) /**< \brief (ADC1) Interrupt Enable Set */
#define REG_ADC1_INTFLAG (0x4300202E) /**< \brief (ADC1) Interrupt Flag Status and Clear */
#define REG_ADC1_STATUS (0x4300202F) /**< \brief (ADC1) Status */
#define REG_ADC1_SYNCBUSY (0x43002030) /**< \brief (ADC1) Synchronization Busy */
#define REG_ADC1_DSEQDATA (0x43002034) /**< \brief (ADC1) DMA Sequencial Data */
#define REG_ADC1_DSEQCTRL (0x43002038) /**< \brief (ADC1) DMA Sequential Control */
#define REG_ADC1_DSEQSTAT (0x4300203C) /**< \brief (ADC1) DMA Sequencial Status */
#define REG_ADC1_RESULT (0x43002040) /**< \brief (ADC1) Result Conversion Value */
#define REG_ADC1_RESS (0x43002044) /**< \brief (ADC1) Last Sample Result */
#define REG_ADC1_CALIB (0x43002048) /**< \brief (ADC1) Calibration */
#else
#define REG_ADC1_CTRLA (*(RwReg16*)0x43002000UL) /**< \brief (ADC1) Control A */
#define REG_ADC1_EVCTRL (*(RwReg8 *)0x43002002UL) /**< \brief (ADC1) Event Control */
#define REG_ADC1_DBGCTRL (*(RwReg8 *)0x43002003UL) /**< \brief (ADC1) Debug Control */
#define REG_ADC1_INPUTCTRL (*(RwReg16*)0x43002004UL) /**< \brief (ADC1) Input Control */
#define REG_ADC1_CTRLB (*(RwReg16*)0x43002006UL) /**< \brief (ADC1) Control B */
#define REG_ADC1_REFCTRL (*(RwReg8 *)0x43002008UL) /**< \brief (ADC1) Reference Control */
#define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4300200AUL) /**< \brief (ADC1) Average Control */
#define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4300200BUL) /**< \brief (ADC1) Sample Time Control */
#define REG_ADC1_WINLT (*(RwReg16*)0x4300200CUL) /**< \brief (ADC1) Window Monitor Lower Threshold */
#define REG_ADC1_WINUT (*(RwReg16*)0x4300200EUL) /**< \brief (ADC1) Window Monitor Upper Threshold */
#define REG_ADC1_GAINCORR (*(RwReg16*)0x43002010UL) /**< \brief (ADC1) Gain Correction */
#define REG_ADC1_OFFSETCORR (*(RwReg16*)0x43002012UL) /**< \brief (ADC1) Offset Correction */
#define REG_ADC1_SWTRIG (*(RwReg8 *)0x43002014UL) /**< \brief (ADC1) Software Trigger */
#define REG_ADC1_INTENCLR (*(RwReg8 *)0x4300202CUL) /**< \brief (ADC1) Interrupt Enable Clear */
#define REG_ADC1_INTENSET (*(RwReg8 *)0x4300202DUL) /**< \brief (ADC1) Interrupt Enable Set */
#define REG_ADC1_INTFLAG (*(RwReg8 *)0x4300202EUL) /**< \brief (ADC1) Interrupt Flag Status and Clear */
#define REG_ADC1_STATUS (*(RoReg8 *)0x4300202FUL) /**< \brief (ADC1) Status */
#define REG_ADC1_SYNCBUSY (*(RoReg *)0x43002030UL) /**< \brief (ADC1) Synchronization Busy */
#define REG_ADC1_DSEQDATA (*(WoReg *)0x43002034UL) /**< \brief (ADC1) DMA Sequencial Data */
#define REG_ADC1_DSEQCTRL (*(RwReg *)0x43002038UL) /**< \brief (ADC1) DMA Sequential Control */
#define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) /**< \brief (ADC1) DMA Sequencial Status */
#define REG_ADC1_RESULT (*(RoReg16*)0x43002040UL) /**< \brief (ADC1) Result Conversion Value */
#define REG_ADC1_RESS (*(RoReg16*)0x43002044UL) /**< \brief (ADC1) Last Sample Result */
#define REG_ADC1_CALIB (*(RwReg16*)0x43002048UL) /**< \brief (ADC1) Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for ADC1 peripheral ========== */
#define ADC1_BANDGAP 27 // MUXPOS value to select BANDGAP
#define ADC1_CTAT 29 // MUXPOS value to select CTAT
#define ADC1_DMAC_ID_RESRDY 70 // Index of DMA RESRDY trigger
#define ADC1_DMAC_ID_SEQ 71 // Index of DMA SEQ trigger
#define ADC1_EXTCHANNEL_MSB 15 // Number of external channels
#define ADC1_GCLK_ID 41 // Index of Generic Clock
#define ADC1_MASTER_SLAVE_MODE 2 // ADC Master/Slave Mode
#define ADC1_OPAMP2 0 // MUXPOS value to select OPAMP2
#define ADC1_OPAMP01 0 // MUXPOS value to select OPAMP01
#define ADC1_PTAT 28 // MUXPOS value to select PTAT
#define ADC1_TOUCH_IMPLEMENTED 0 // TOUCH implemented or not
#define ADC1_TOUCH_LINES_NUM 1 // Number of touch lines
#endif /* _SAMD51_ADC1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for AES
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_AES_INSTANCE_
#define _SAMD51_AES_INSTANCE_
/* ========== Register definition for AES peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AES_CTRLA (0x42002400) /**< \brief (AES) Control A */
#define REG_AES_CTRLB (0x42002404) /**< \brief (AES) Control B */
#define REG_AES_INTENCLR (0x42002405) /**< \brief (AES) Interrupt Enable Clear */
#define REG_AES_INTENSET (0x42002406) /**< \brief (AES) Interrupt Enable Set */
#define REG_AES_INTFLAG (0x42002407) /**< \brief (AES) Interrupt Flag Status */
#define REG_AES_DATABUFPTR (0x42002408) /**< \brief (AES) Data buffer pointer */
#define REG_AES_DBGCTRL (0x42002409) /**< \brief (AES) Debug control */
#define REG_AES_KEYWORD0 (0x4200240C) /**< \brief (AES) Keyword 0 */
#define REG_AES_KEYWORD1 (0x42002410) /**< \brief (AES) Keyword 1 */
#define REG_AES_KEYWORD2 (0x42002414) /**< \brief (AES) Keyword 2 */
#define REG_AES_KEYWORD3 (0x42002418) /**< \brief (AES) Keyword 3 */
#define REG_AES_KEYWORD4 (0x4200241C) /**< \brief (AES) Keyword 4 */
#define REG_AES_KEYWORD5 (0x42002420) /**< \brief (AES) Keyword 5 */
#define REG_AES_KEYWORD6 (0x42002424) /**< \brief (AES) Keyword 6 */
#define REG_AES_KEYWORD7 (0x42002428) /**< \brief (AES) Keyword 7 */
#define REG_AES_INDATA (0x42002438) /**< \brief (AES) Indata */
#define REG_AES_INTVECTV0 (0x4200243C) /**< \brief (AES) Initialisation Vector 0 */
#define REG_AES_INTVECTV1 (0x42002440) /**< \brief (AES) Initialisation Vector 1 */
#define REG_AES_INTVECTV2 (0x42002444) /**< \brief (AES) Initialisation Vector 2 */
#define REG_AES_INTVECTV3 (0x42002448) /**< \brief (AES) Initialisation Vector 3 */
#define REG_AES_HASHKEY0 (0x4200245C) /**< \brief (AES) Hash key 0 */
#define REG_AES_HASHKEY1 (0x42002460) /**< \brief (AES) Hash key 1 */
#define REG_AES_HASHKEY2 (0x42002464) /**< \brief (AES) Hash key 2 */
#define REG_AES_HASHKEY3 (0x42002468) /**< \brief (AES) Hash key 3 */
#define REG_AES_GHASH0 (0x4200246C) /**< \brief (AES) Galois Hash 0 */
#define REG_AES_GHASH1 (0x42002470) /**< \brief (AES) Galois Hash 1 */
#define REG_AES_GHASH2 (0x42002474) /**< \brief (AES) Galois Hash 2 */
#define REG_AES_GHASH3 (0x42002478) /**< \brief (AES) Galois Hash 3 */
#define REG_AES_CIPLEN (0x42002480) /**< \brief (AES) Cipher Length */
#define REG_AES_RANDSEED (0x42002484) /**< \brief (AES) Random Seed */
#else
#define REG_AES_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (AES) Control A */
#define REG_AES_CTRLB (*(RwReg8 *)0x42002404UL) /**< \brief (AES) Control B */
#define REG_AES_INTENCLR (*(RwReg8 *)0x42002405UL) /**< \brief (AES) Interrupt Enable Clear */
#define REG_AES_INTENSET (*(RwReg8 *)0x42002406UL) /**< \brief (AES) Interrupt Enable Set */
#define REG_AES_INTFLAG (*(RwReg8 *)0x42002407UL) /**< \brief (AES) Interrupt Flag Status */
#define REG_AES_DATABUFPTR (*(RwReg8 *)0x42002408UL) /**< \brief (AES) Data buffer pointer */
#define REG_AES_DBGCTRL (*(RwReg8 *)0x42002409UL) /**< \brief (AES) Debug control */
#define REG_AES_KEYWORD0 (*(WoReg *)0x4200240CUL) /**< \brief (AES) Keyword 0 */
#define REG_AES_KEYWORD1 (*(WoReg *)0x42002410UL) /**< \brief (AES) Keyword 1 */
#define REG_AES_KEYWORD2 (*(WoReg *)0x42002414UL) /**< \brief (AES) Keyword 2 */
#define REG_AES_KEYWORD3 (*(WoReg *)0x42002418UL) /**< \brief (AES) Keyword 3 */
#define REG_AES_KEYWORD4 (*(WoReg *)0x4200241CUL) /**< \brief (AES) Keyword 4 */
#define REG_AES_KEYWORD5 (*(WoReg *)0x42002420UL) /**< \brief (AES) Keyword 5 */
#define REG_AES_KEYWORD6 (*(WoReg *)0x42002424UL) /**< \brief (AES) Keyword 6 */
#define REG_AES_KEYWORD7 (*(WoReg *)0x42002428UL) /**< \brief (AES) Keyword 7 */
#define REG_AES_INDATA (*(RwReg *)0x42002438UL) /**< \brief (AES) Indata */
#define REG_AES_INTVECTV0 (*(WoReg *)0x4200243CUL) /**< \brief (AES) Initialisation Vector 0 */
#define REG_AES_INTVECTV1 (*(WoReg *)0x42002440UL) /**< \brief (AES) Initialisation Vector 1 */
#define REG_AES_INTVECTV2 (*(WoReg *)0x42002444UL) /**< \brief (AES) Initialisation Vector 2 */
#define REG_AES_INTVECTV3 (*(WoReg *)0x42002448UL) /**< \brief (AES) Initialisation Vector 3 */
#define REG_AES_HASHKEY0 (*(RwReg *)0x4200245CUL) /**< \brief (AES) Hash key 0 */
#define REG_AES_HASHKEY1 (*(RwReg *)0x42002460UL) /**< \brief (AES) Hash key 1 */
#define REG_AES_HASHKEY2 (*(RwReg *)0x42002464UL) /**< \brief (AES) Hash key 2 */
#define REG_AES_HASHKEY3 (*(RwReg *)0x42002468UL) /**< \brief (AES) Hash key 3 */
#define REG_AES_GHASH0 (*(RwReg *)0x4200246CUL) /**< \brief (AES) Galois Hash 0 */
#define REG_AES_GHASH1 (*(RwReg *)0x42002470UL) /**< \brief (AES) Galois Hash 1 */
#define REG_AES_GHASH2 (*(RwReg *)0x42002474UL) /**< \brief (AES) Galois Hash 2 */
#define REG_AES_GHASH3 (*(RwReg *)0x42002478UL) /**< \brief (AES) Galois Hash 3 */
#define REG_AES_CIPLEN (*(RwReg *)0x42002480UL) /**< \brief (AES) Cipher Length */
#define REG_AES_RANDSEED (*(RwReg *)0x42002484UL) /**< \brief (AES) Random Seed */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for AES peripheral ========== */
#define AES_DMAC_ID_RD 82 // DMA DATA Read trigger
#define AES_DMAC_ID_WR 81 // DMA DATA Write trigger
#define AES_FOUR_BYTE_OPERATION 1 // Byte Operation
#define AES_GCM 1 // GCM
#define AES_KEYLEN 2 // Key Length
#endif /* _SAMD51_AES_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for CAN0
*
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_CAN0_INSTANCE_
#define _SAMD51_CAN0_INSTANCE_
/* ========== Register definition for CAN0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CAN0_CREL (0x42000000U) /**< \brief (CAN0) Core Release */
#define REG_CAN0_ENDN (0x42000004U) /**< \brief (CAN0) Endian */
#define REG_CAN0_MRCFG (0x42000008U) /**< \brief (CAN0) Message RAM Configuration */
#define REG_CAN0_DBTP (0x4200000CU) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
#define REG_CAN0_TEST (0x42000010U) /**< \brief (CAN0) Test */
#define REG_CAN0_RWD (0x42000014U) /**< \brief (CAN0) RAM Watchdog */
#define REG_CAN0_CCCR (0x42000018U) /**< \brief (CAN0) CC Control */
#define REG_CAN0_NBTP (0x4200001CU) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
#define REG_CAN0_TSCC (0x42000020U) /**< \brief (CAN0) Timestamp Counter Configuration */
#define REG_CAN0_TSCV (0x42000024U) /**< \brief (CAN0) Timestamp Counter Value */
#define REG_CAN0_TOCC (0x42000028U) /**< \brief (CAN0) Timeout Counter Configuration */
#define REG_CAN0_TOCV (0x4200002CU) /**< \brief (CAN0) Timeout Counter Value */
#define REG_CAN0_ECR (0x42000040U) /**< \brief (CAN0) Error Counter */
#define REG_CAN0_PSR (0x42000044U) /**< \brief (CAN0) Protocol Status */
#define REG_CAN0_TDCR (0x42000048U) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_IR (0x42000050U) /**< \brief (CAN0) Interrupt */
#define REG_CAN0_IE (0x42000054U) /**< \brief (CAN0) Interrupt Enable */
#define REG_CAN0_ILS (0x42000058U) /**< \brief (CAN0) Interrupt Line Select */
#define REG_CAN0_ILE (0x4200005CU) /**< \brief (CAN0) Interrupt Line Enable */
#define REG_CAN0_GFC (0x42000080U) /**< \brief (CAN0) Global Filter Configuration */
#define REG_CAN0_SIDFC (0x42000084U) /**< \brief (CAN0) Standard ID Filter Configuration */
#define REG_CAN0_XIDFC (0x42000088U) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_XIDAM (0x42000090U) /**< \brief (CAN0) Extended ID AND Mask */
#define REG_CAN0_HPMS (0x42000094U) /**< \brief (CAN0) High Priority Message Status */
#define REG_CAN0_NDAT1 (0x42000098U) /**< \brief (CAN0) New Data 1 */
#define REG_CAN0_NDAT2 (0x4200009CU) /**< \brief (CAN0) New Data 2 */
#define REG_CAN0_RXF0C (0x420000A0U) /**< \brief (CAN0) Rx FIFO 0 Configuration */
#define REG_CAN0_RXF0S (0x420000A4U) /**< \brief (CAN0) Rx FIFO 0 Status */
#define REG_CAN0_RXF0A (0x420000A8U) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
#define REG_CAN0_RXBC (0x420000ACU) /**< \brief (CAN0) Rx Buffer Configuration */
#define REG_CAN0_RXF1C (0x420000B0U) /**< \brief (CAN0) Rx FIFO 1 Configuration */
#define REG_CAN0_RXF1S (0x420000B4U) /**< \brief (CAN0) Rx FIFO 1 Status */
#define REG_CAN0_RXF1A (0x420000B8U) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
#define REG_CAN0_RXESC (0x420000BCU) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN0_TXBC (0x420000C0U) /**< \brief (CAN0) Tx Buffer Configuration */
#define REG_CAN0_TXFQS (0x420000C4U) /**< \brief (CAN0) Tx FIFO / Queue Status */
#define REG_CAN0_TXESC (0x420000C8U) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
#define REG_CAN0_TXBRP (0x420000CCU) /**< \brief (CAN0) Tx Buffer Request Pending */
#define REG_CAN0_TXBAR (0x420000D0U) /**< \brief (CAN0) Tx Buffer Add Request */
#define REG_CAN0_TXBCR (0x420000D4U) /**< \brief (CAN0) Tx Buffer Cancellation Request */
#define REG_CAN0_TXBTO (0x420000D8U) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
#define REG_CAN0_TXBCF (0x420000DCU) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
#define REG_CAN0_TXBTIE (0x420000E0U) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN0_TXBCIE (0x420000E4U) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN0_TXEFC (0x420000F0U) /**< \brief (CAN0) Tx Event FIFO Configuration */
#define REG_CAN0_TXEFS (0x420000F4U) /**< \brief (CAN0) Tx Event FIFO Status */
#define REG_CAN0_TXEFA (0x420000F8U) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
#else
#define REG_CAN0_CREL (*(RoReg *)0x42000000U) /**< \brief (CAN0) Core Release */
#define REG_CAN0_ENDN (*(RoReg *)0x42000004U) /**< \brief (CAN0) Endian */
#define REG_CAN0_MRCFG (*(RwReg *)0x42000008U) /**< \brief (CAN0) Message RAM Configuration */
#define REG_CAN0_DBTP (*(RwReg *)0x4200000CU) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
#define REG_CAN0_TEST (*(RwReg *)0x42000010U) /**< \brief (CAN0) Test */
#define REG_CAN0_RWD (*(RwReg *)0x42000014U) /**< \brief (CAN0) RAM Watchdog */
#define REG_CAN0_CCCR (*(RwReg *)0x42000018U) /**< \brief (CAN0) CC Control */
#define REG_CAN0_NBTP (*(RwReg *)0x4200001CU) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
#define REG_CAN0_TSCC (*(RwReg *)0x42000020U) /**< \brief (CAN0) Timestamp Counter Configuration */
#define REG_CAN0_TSCV (*(RoReg *)0x42000024U) /**< \brief (CAN0) Timestamp Counter Value */
#define REG_CAN0_TOCC (*(RwReg *)0x42000028U) /**< \brief (CAN0) Timeout Counter Configuration */
#define REG_CAN0_TOCV (*(RwReg *)0x4200002CU) /**< \brief (CAN0) Timeout Counter Value */
#define REG_CAN0_ECR (*(RoReg *)0x42000040U) /**< \brief (CAN0) Error Counter */
#define REG_CAN0_PSR (*(RoReg *)0x42000044U) /**< \brief (CAN0) Protocol Status */
#define REG_CAN0_TDCR (*(RwReg *)0x42000048U) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_IR (*(RwReg *)0x42000050U) /**< \brief (CAN0) Interrupt */
#define REG_CAN0_IE (*(RwReg *)0x42000054U) /**< \brief (CAN0) Interrupt Enable */
#define REG_CAN0_ILS (*(RwReg *)0x42000058U) /**< \brief (CAN0) Interrupt Line Select */
#define REG_CAN0_ILE (*(RwReg *)0x4200005CU) /**< \brief (CAN0) Interrupt Line Enable */
#define REG_CAN0_GFC (*(RwReg *)0x42000080U) /**< \brief (CAN0) Global Filter Configuration */
#define REG_CAN0_SIDFC (*(RwReg *)0x42000084U) /**< \brief (CAN0) Standard ID Filter Configuration */
#define REG_CAN0_XIDFC (*(RwReg *)0x42000088U) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_XIDAM (*(RwReg *)0x42000090U) /**< \brief (CAN0) Extended ID AND Mask */
#define REG_CAN0_HPMS (*(RoReg *)0x42000094U) /**< \brief (CAN0) High Priority Message Status */
#define REG_CAN0_NDAT1 (*(RwReg *)0x42000098U) /**< \brief (CAN0) New Data 1 */
#define REG_CAN0_NDAT2 (*(RwReg *)0x4200009CU) /**< \brief (CAN0) New Data 2 */
#define REG_CAN0_RXF0C (*(RwReg *)0x420000A0U) /**< \brief (CAN0) Rx FIFO 0 Configuration */
#define REG_CAN0_RXF0S (*(RoReg *)0x420000A4U) /**< \brief (CAN0) Rx FIFO 0 Status */
#define REG_CAN0_RXF0A (*(RwReg *)0x420000A8U) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
#define REG_CAN0_RXBC (*(RwReg *)0x420000ACU) /**< \brief (CAN0) Rx Buffer Configuration */
#define REG_CAN0_RXF1C (*(RwReg *)0x420000B0U) /**< \brief (CAN0) Rx FIFO 1 Configuration */
#define REG_CAN0_RXF1S (*(RoReg *)0x420000B4U) /**< \brief (CAN0) Rx FIFO 1 Status */
#define REG_CAN0_RXF1A (*(RwReg *)0x420000B8U) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
#define REG_CAN0_RXESC (*(RwReg *)0x420000BCU) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN0_TXBC (*(RwReg *)0x420000C0U) /**< \brief (CAN0) Tx Buffer Configuration */
#define REG_CAN0_TXFQS (*(RoReg *)0x420000C4U) /**< \brief (CAN0) Tx FIFO / Queue Status */
#define REG_CAN0_TXESC (*(RwReg *)0x420000C8U) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
#define REG_CAN0_TXBRP (*(RoReg *)0x420000CCU) /**< \brief (CAN0) Tx Buffer Request Pending */
#define REG_CAN0_TXBAR (*(RwReg *)0x420000D0U) /**< \brief (CAN0) Tx Buffer Add Request */
#define REG_CAN0_TXBCR (*(RwReg *)0x420000D4U) /**< \brief (CAN0) Tx Buffer Cancellation Request */
#define REG_CAN0_TXBTO (*(RoReg *)0x420000D8U) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
#define REG_CAN0_TXBCF (*(RoReg *)0x420000DCU) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
#define REG_CAN0_TXBTIE (*(RwReg *)0x420000E0U) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN0_TXBCIE (*(RwReg *)0x420000E4U) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN0_TXEFC (*(RwReg *)0x420000F0U) /**< \brief (CAN0) Tx Event FIFO Configuration */
#define REG_CAN0_TXEFS (*(RoReg *)0x420000F4U) /**< \brief (CAN0) Tx Event FIFO Status */
#define REG_CAN0_TXEFA (*(RwReg *)0x420000F8U) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CAN0 peripheral ========== */
#define CAN0_CLK_AHB_ID 17 // Index of AHB clock
#define CAN0_DMAC_ID_DEBUG 20 // DMA CAN Debug Req
#define CAN0_GCLK_ID 27 // Index of Generic Clock
#define CAN0_MSG_RAM_ADDR 0x20000000
#define CAN0_QOS_RESET_VAL 1 // QOS reset value
#endif /* _SAMD51_CAN0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for CAN1
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_CAN1_INSTANCE_
#define _SAMD51_CAN1_INSTANCE_
/* ========== Register definition for CAN1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CAN1_CREL (0x42003800U) /**< \brief (CAN1) Core Release */
#define REG_CAN1_ENDN (0x42003804U) /**< \brief (CAN1) Endian */
#define REG_CAN1_MRCFG (0x42003808U) /**< \brief (CAN1) Message RAM Configuration */
#define REG_CAN1_DBTP (0x4200380CU) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
#define REG_CAN1_TEST (0x42003810U) /**< \brief (CAN1) Test */
#define REG_CAN1_RWD (0x42003814U) /**< \brief (CAN1) RAM Watchdog */
#define REG_CAN1_CCCR (0x42003818U) /**< \brief (CAN1) CC Control */
#define REG_CAN1_NBTP (0x4200381CU) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
#define REG_CAN1_TSCC (0x42003820U) /**< \brief (CAN1) Timestamp Counter Configuration */
#define REG_CAN1_TSCV (0x42003824U) /**< \brief (CAN1) Timestamp Counter Value */
#define REG_CAN1_TOCC (0x42003828U) /**< \brief (CAN1) Timeout Counter Configuration */
#define REG_CAN1_TOCV (0x4200382CU) /**< \brief (CAN1) Timeout Counter Value */
#define REG_CAN1_ECR (0x42003840U) /**< \brief (CAN1) Error Counter */
#define REG_CAN1_PSR (0x42003844U) /**< \brief (CAN1) Protocol Status */
#define REG_CAN1_TDCR (0x42003848U) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_IR (0x42003850U) /**< \brief (CAN1) Interrupt */
#define REG_CAN1_IE (0x42003854U) /**< \brief (CAN1) Interrupt Enable */
#define REG_CAN1_ILS (0x42003858U) /**< \brief (CAN1) Interrupt Line Select */
#define REG_CAN1_ILE (0x4200385CU) /**< \brief (CAN1) Interrupt Line Enable */
#define REG_CAN1_GFC (0x42003880U) /**< \brief (CAN1) Global Filter Configuration */
#define REG_CAN1_SIDFC (0x42003884U) /**< \brief (CAN1) Standard ID Filter Configuration */
#define REG_CAN1_XIDFC (0x42003888U) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_XIDAM (0x42003890U) /**< \brief (CAN1) Extended ID AND Mask */
#define REG_CAN1_HPMS (0x42003894U) /**< \brief (CAN1) High Priority Message Status */
#define REG_CAN1_NDAT1 (0x42003898U) /**< \brief (CAN1) New Data 1 */
#define REG_CAN1_NDAT2 (0x4200389CU) /**< \brief (CAN1) New Data 2 */
#define REG_CAN1_RXF0C (0x420038A0U) /**< \brief (CAN1) Rx FIFO 0 Configuration */
#define REG_CAN1_RXF0S (0x420038A4U) /**< \brief (CAN1) Rx FIFO 0 Status */
#define REG_CAN1_RXF0A (0x420038A8U) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
#define REG_CAN1_RXBC (0x420038ACU) /**< \brief (CAN1) Rx Buffer Configuration */
#define REG_CAN1_RXF1C (0x420038B0U) /**< \brief (CAN1) Rx FIFO 1 Configuration */
#define REG_CAN1_RXF1S (0x420038B4U) /**< \brief (CAN1) Rx FIFO 1 Status */
#define REG_CAN1_RXF1A (0x420038B8U) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
#define REG_CAN1_RXESC (0x420038BCU) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN1_TXBC (0x420038C0U) /**< \brief (CAN1) Tx Buffer Configuration */
#define REG_CAN1_TXFQS (0x420038C4U) /**< \brief (CAN1) Tx FIFO / Queue Status */
#define REG_CAN1_TXESC (0x420038C8U) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
#define REG_CAN1_TXBRP (0x420038CCU) /**< \brief (CAN1) Tx Buffer Request Pending */
#define REG_CAN1_TXBAR (0x420038D0U) /**< \brief (CAN1) Tx Buffer Add Request */
#define REG_CAN1_TXBCR (0x420038D4U) /**< \brief (CAN1) Tx Buffer Cancellation Request */
#define REG_CAN1_TXBTO (0x420038D8U) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
#define REG_CAN1_TXBCF (0x420038DCU) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
#define REG_CAN1_TXBTIE (0x420038E0U) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN1_TXBCIE (0x420038E4U) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN1_TXEFC (0x420038F0U) /**< \brief (CAN1) Tx Event FIFO Configuration */
#define REG_CAN1_TXEFS (0x420038F4U) /**< \brief (CAN1) Tx Event FIFO Status */
#define REG_CAN1_TXEFA (0x420038F8U) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
#else
#define REG_CAN1_CREL (*(RoReg *)0x42003800U) /**< \brief (CAN1) Core Release */
#define REG_CAN1_ENDN (*(RoReg *)0x42003804U) /**< \brief (CAN1) Endian */
#define REG_CAN1_MRCFG (*(RwReg *)0x42003808U) /**< \brief (CAN1) Message RAM Configuration */
#define REG_CAN1_DBTP (*(RwReg *)0x4200380CU) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
#define REG_CAN1_TEST (*(RwReg *)0x42003810U) /**< \brief (CAN1) Test */
#define REG_CAN1_RWD (*(RwReg *)0x42003814U) /**< \brief (CAN1) RAM Watchdog */
#define REG_CAN1_CCCR (*(RwReg *)0x42003818U) /**< \brief (CAN1) CC Control */
#define REG_CAN1_NBTP (*(RwReg *)0x4200381CU) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
#define REG_CAN1_TSCC (*(RwReg *)0x42003820U) /**< \brief (CAN1) Timestamp Counter Configuration */
#define REG_CAN1_TSCV (*(RoReg *)0x42003824U) /**< \brief (CAN1) Timestamp Counter Value */
#define REG_CAN1_TOCC (*(RwReg *)0x42003828U) /**< \brief (CAN1) Timeout Counter Configuration */
#define REG_CAN1_TOCV (*(RwReg *)0x4200382CU) /**< \brief (CAN1) Timeout Counter Value */
#define REG_CAN1_ECR (*(RoReg *)0x42003840U) /**< \brief (CAN1) Error Counter */
#define REG_CAN1_PSR (*(RoReg *)0x42003844U) /**< \brief (CAN1) Protocol Status */
#define REG_CAN1_TDCR (*(RwReg *)0x42003848U) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_IR (*(RwReg *)0x42003850U) /**< \brief (CAN1) Interrupt */
#define REG_CAN1_IE (*(RwReg *)0x42003854U) /**< \brief (CAN1) Interrupt Enable */
#define REG_CAN1_ILS (*(RwReg *)0x42003858U) /**< \brief (CAN1) Interrupt Line Select */
#define REG_CAN1_ILE (*(RwReg *)0x4200385CU) /**< \brief (CAN1) Interrupt Line Enable */
#define REG_CAN1_GFC (*(RwReg *)0x42003880U) /**< \brief (CAN1) Global Filter Configuration */
#define REG_CAN1_SIDFC (*(RwReg *)0x42003884U) /**< \brief (CAN1) Standard ID Filter Configuration */
#define REG_CAN1_XIDFC (*(RwReg *)0x42003888U) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_XIDAM (*(RwReg *)0x42003890U) /**< \brief (CAN1) Extended ID AND Mask */
#define REG_CAN1_HPMS (*(RoReg *)0x42003894U) /**< \brief (CAN1) High Priority Message Status */
#define REG_CAN1_NDAT1 (*(RwReg *)0x42003898U) /**< \brief (CAN1) New Data 1 */
#define REG_CAN1_NDAT2 (*(RwReg *)0x4200389CU) /**< \brief (CAN1) New Data 2 */
#define REG_CAN1_RXF0C (*(RwReg *)0x420038A0U) /**< \brief (CAN1) Rx FIFO 0 Configuration */
#define REG_CAN1_RXF0S (*(RoReg *)0x420038A4U) /**< \brief (CAN1) Rx FIFO 0 Status */
#define REG_CAN1_RXF0A (*(RwReg *)0x420038A8U) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
#define REG_CAN1_RXBC (*(RwReg *)0x420038ACU) /**< \brief (CAN1) Rx Buffer Configuration */
#define REG_CAN1_RXF1C (*(RwReg *)0x420038B0U) /**< \brief (CAN1) Rx FIFO 1 Configuration */
#define REG_CAN1_RXF1S (*(RoReg *)0x420038B4U) /**< \brief (CAN1) Rx FIFO 1 Status */
#define REG_CAN1_RXF1A (*(RwReg *)0x420038B8U) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
#define REG_CAN1_RXESC (*(RwReg *)0x420038BCU) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN1_TXBC (*(RwReg *)0x420038C0U) /**< \brief (CAN1) Tx Buffer Configuration */
#define REG_CAN1_TXFQS (*(RoReg *)0x420038C4U) /**< \brief (CAN1) Tx FIFO / Queue Status */
#define REG_CAN1_TXESC (*(RwReg *)0x420038C8U) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
#define REG_CAN1_TXBRP (*(RoReg *)0x420038CCU) /**< \brief (CAN1) Tx Buffer Request Pending */
#define REG_CAN1_TXBAR (*(RwReg *)0x420038D0U) /**< \brief (CAN1) Tx Buffer Add Request */
#define REG_CAN1_TXBCR (*(RwReg *)0x420038D4U) /**< \brief (CAN1) Tx Buffer Cancellation Request */
#define REG_CAN1_TXBTO (*(RoReg *)0x420038D8U) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
#define REG_CAN1_TXBCF (*(RoReg *)0x420038DCU) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
#define REG_CAN1_TXBTIE (*(RwReg *)0x420038E0U) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN1_TXBCIE (*(RwReg *)0x420038E4U) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN1_TXEFC (*(RwReg *)0x420038F0U) /**< \brief (CAN1) Tx Event FIFO Configuration */
#define REG_CAN1_TXEFS (*(RoReg *)0x420038F4U) /**< \brief (CAN1) Tx Event FIFO Status */
#define REG_CAN1_TXEFA (*(RwReg *)0x420038F8U) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CAN1 peripheral ========== */
#define CAN1_CLK_AHB_ID 22 // Index of AHB clock
#define CAN1_DMAC_ID_DEBUG 38 // DMA CAN Debug Req
#define CAN1_GCLK_ID 36 // Index of Generic Clock
#endif /* _SAMD51_CAN1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for CCL
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_CCL_INSTANCE_
#define _SAMD51_CCL_INSTANCE_
/* ========== Register definition for CCL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CCL_CTRL (0x42003800) /**< \brief (CCL) Control */
#define REG_CCL_SEQCTRL0 (0x42003804) /**< \brief (CCL) SEQ Control x 0 */
#define REG_CCL_SEQCTRL1 (0x42003805) /**< \brief (CCL) SEQ Control x 1 */
#define REG_CCL_LUTCTRL0 (0x42003808) /**< \brief (CCL) LUT Control x 0 */
#define REG_CCL_LUTCTRL1 (0x4200380C) /**< \brief (CCL) LUT Control x 1 */
#define REG_CCL_LUTCTRL2 (0x42003810) /**< \brief (CCL) LUT Control x 2 */
#define REG_CCL_LUTCTRL3 (0x42003814) /**< \brief (CCL) LUT Control x 3 */
#else
#define REG_CCL_CTRL (*(RwReg8 *)0x42003800UL) /**< \brief (CCL) Control */
#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42003804UL) /**< \brief (CCL) SEQ Control x 0 */
#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42003805UL) /**< \brief (CCL) SEQ Control x 1 */
#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42003808UL) /**< \brief (CCL) LUT Control x 0 */
#define REG_CCL_LUTCTRL1 (*(RwReg *)0x4200380CUL) /**< \brief (CCL) LUT Control x 1 */
#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42003810UL) /**< \brief (CCL) LUT Control x 2 */
#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42003814UL) /**< \brief (CCL) LUT Control x 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CCL peripheral ========== */
#define CCL_GCLK_ID 33 // GCLK index for CCL
#define CCL_LUT_NUM 4 // Number of LUT in a CCL
#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL
#endif /* _SAMD51_CCL_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for CMCC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_CMCC_INSTANCE_
#define _SAMD51_CMCC_INSTANCE_
/* ========== Register definition for CMCC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CMCC_TYPE (0x41006000) /**< \brief (CMCC) Cache Type Register */
#define REG_CMCC_CFG (0x41006004) /**< \brief (CMCC) Cache Configuration Register */
#define REG_CMCC_CTRL (0x41006008) /**< \brief (CMCC) Cache Control Register */
#define REG_CMCC_SR (0x4100600C) /**< \brief (CMCC) Cache Status Register */
#define REG_CMCC_LCKWAY (0x41006010) /**< \brief (CMCC) Cache Lock per Way Register */
#define REG_CMCC_MAINT0 (0x41006020) /**< \brief (CMCC) Cache Maintenance Register 0 */
#define REG_CMCC_MAINT1 (0x41006024) /**< \brief (CMCC) Cache Maintenance Register 1 */
#define REG_CMCC_MCFG (0x41006028) /**< \brief (CMCC) Cache Monitor Configuration Register */
#define REG_CMCC_MEN (0x4100602C) /**< \brief (CMCC) Cache Monitor Enable Register */
#define REG_CMCC_MCTRL (0x41006030) /**< \brief (CMCC) Cache Monitor Control Register */
#define REG_CMCC_MSR (0x41006034) /**< \brief (CMCC) Cache Monitor Status Register */
#else
#define REG_CMCC_TYPE (*(RoReg *)0x41006000UL) /**< \brief (CMCC) Cache Type Register */
#define REG_CMCC_CFG (*(RwReg *)0x41006004UL) /**< \brief (CMCC) Cache Configuration Register */
#define REG_CMCC_CTRL (*(WoReg *)0x41006008UL) /**< \brief (CMCC) Cache Control Register */
#define REG_CMCC_SR (*(RoReg *)0x4100600CUL) /**< \brief (CMCC) Cache Status Register */
#define REG_CMCC_LCKWAY (*(RwReg *)0x41006010UL) /**< \brief (CMCC) Cache Lock per Way Register */
#define REG_CMCC_MAINT0 (*(WoReg *)0x41006020UL) /**< \brief (CMCC) Cache Maintenance Register 0 */
#define REG_CMCC_MAINT1 (*(WoReg *)0x41006024UL) /**< \brief (CMCC) Cache Maintenance Register 1 */
#define REG_CMCC_MCFG (*(RwReg *)0x41006028UL) /**< \brief (CMCC) Cache Monitor Configuration Register */
#define REG_CMCC_MEN (*(RwReg *)0x4100602CUL) /**< \brief (CMCC) Cache Monitor Enable Register */
#define REG_CMCC_MCTRL (*(WoReg *)0x41006030UL) /**< \brief (CMCC) Cache Monitor Control Register */
#define REG_CMCC_MSR (*(RoReg *)0x41006034UL) /**< \brief (CMCC) Cache Monitor Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_CMCC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for DAC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_DAC_INSTANCE_
#define _SAMD51_DAC_INSTANCE_
/* ========== Register definition for DAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DAC_CTRLA (0x43002400) /**< \brief (DAC) Control A */
#define REG_DAC_CTRLB (0x43002401) /**< \brief (DAC) Control B */
#define REG_DAC_EVCTRL (0x43002402) /**< \brief (DAC) Event Control */
#define REG_DAC_INTENCLR (0x43002404) /**< \brief (DAC) Interrupt Enable Clear */
#define REG_DAC_INTENSET (0x43002405) /**< \brief (DAC) Interrupt Enable Set */
#define REG_DAC_INTFLAG (0x43002406) /**< \brief (DAC) Interrupt Flag Status and Clear */
#define REG_DAC_STATUS (0x43002407) /**< \brief (DAC) Status */
#define REG_DAC_SYNCBUSY (0x43002408) /**< \brief (DAC) Synchronization Busy */
#define REG_DAC_DACCTRL0 (0x4300240C) /**< \brief (DAC) DAC 0 Control */
#define REG_DAC_DACCTRL1 (0x4300240E) /**< \brief (DAC) DAC 1 Control */
#define REG_DAC_DATA0 (0x43002410) /**< \brief (DAC) DAC 0 Data */
#define REG_DAC_DATA1 (0x43002412) /**< \brief (DAC) DAC 1 Data */
#define REG_DAC_DATABUF0 (0x43002414) /**< \brief (DAC) DAC 0 Data Buffer */
#define REG_DAC_DATABUF1 (0x43002416) /**< \brief (DAC) DAC 1 Data Buffer */
#define REG_DAC_DBGCTRL (0x43002418) /**< \brief (DAC) Debug Control */
#define REG_DAC_RESULT0 (0x4300241C) /**< \brief (DAC) Filter Result 0 */
#define REG_DAC_RESULT1 (0x4300241E) /**< \brief (DAC) Filter Result 1 */
#else
#define REG_DAC_CTRLA (*(RwReg8 *)0x43002400UL) /**< \brief (DAC) Control A */
#define REG_DAC_CTRLB (*(RwReg8 *)0x43002401UL) /**< \brief (DAC) Control B */
#define REG_DAC_EVCTRL (*(RwReg8 *)0x43002402UL) /**< \brief (DAC) Event Control */
#define REG_DAC_INTENCLR (*(RwReg8 *)0x43002404UL) /**< \brief (DAC) Interrupt Enable Clear */
#define REG_DAC_INTENSET (*(RwReg8 *)0x43002405UL) /**< \brief (DAC) Interrupt Enable Set */
#define REG_DAC_INTFLAG (*(RwReg8 *)0x43002406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
#define REG_DAC_STATUS (*(RoReg8 *)0x43002407UL) /**< \brief (DAC) Status */
#define REG_DAC_SYNCBUSY (*(RoReg *)0x43002408UL) /**< \brief (DAC) Synchronization Busy */
#define REG_DAC_DACCTRL0 (*(RwReg16*)0x4300240CUL) /**< \brief (DAC) DAC 0 Control */
#define REG_DAC_DACCTRL1 (*(RwReg16*)0x4300240EUL) /**< \brief (DAC) DAC 1 Control */
#define REG_DAC_DATA0 (*(WoReg16*)0x43002410UL) /**< \brief (DAC) DAC 0 Data */
#define REG_DAC_DATA1 (*(WoReg16*)0x43002412UL) /**< \brief (DAC) DAC 1 Data */
#define REG_DAC_DATABUF0 (*(WoReg16*)0x43002414UL) /**< \brief (DAC) DAC 0 Data Buffer */
#define REG_DAC_DATABUF1 (*(WoReg16*)0x43002416UL) /**< \brief (DAC) DAC 1 Data Buffer */
#define REG_DAC_DBGCTRL (*(RwReg8 *)0x43002418UL) /**< \brief (DAC) Debug Control */
#define REG_DAC_RESULT0 (*(RoReg16*)0x4300241CUL) /**< \brief (DAC) Filter Result 0 */
#define REG_DAC_RESULT1 (*(RoReg16*)0x4300241EUL) /**< \brief (DAC) Filter Result 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DAC peripheral ========== */
#define DAC_CHANNEL_SIZE 2 // Number of DACs
#define DAC_DATA_SIZE 12 // Number of bits in data
#define DAC_DMAC_ID_EMPTY_0 72
#define DAC_DMAC_ID_EMPTY_1 73
#define DAC_DMAC_ID_EMPTY_LSB 72
#define DAC_DMAC_ID_EMPTY_MSB 73
#define DAC_DMAC_ID_EMPTY_SIZE 2
#define DAC_DMAC_ID_RESRDY_0 74
#define DAC_DMAC_ID_RESRDY_1 75
#define DAC_DMAC_ID_RESRDY_LSB 74
#define DAC_DMAC_ID_RESRDY_MSB 75
#define DAC_DMAC_ID_RESRDY_SIZE 2
#define DAC_GCLK_ID 42 // Index of Generic Clock
#define DAC_STEP 7 // Number of steps to reach full scale
#endif /* _SAMD51_DAC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for DMAC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_DMAC_INSTANCE_
#define _SAMD51_DMAC_INSTANCE_
/* ========== Register definition for DMAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DMAC_CTRL (0x4100A000) /**< \brief (DMAC) Control */
#define REG_DMAC_CRCCTRL (0x4100A002) /**< \brief (DMAC) CRC Control */
#define REG_DMAC_CRCDATAIN (0x4100A004) /**< \brief (DMAC) CRC Data Input */
#define REG_DMAC_CRCCHKSUM (0x4100A008) /**< \brief (DMAC) CRC Checksum */
#define REG_DMAC_CRCSTATUS (0x4100A00C) /**< \brief (DMAC) CRC Status */
#define REG_DMAC_DBGCTRL (0x4100A00D) /**< \brief (DMAC) Debug Control */
#define REG_DMAC_SWTRIGCTRL (0x4100A010) /**< \brief (DMAC) Software Trigger Control */
#define REG_DMAC_PRICTRL0 (0x4100A014) /**< \brief (DMAC) Priority Control 0 */
#define REG_DMAC_INTPEND (0x4100A020) /**< \brief (DMAC) Interrupt Pending */
#define REG_DMAC_INTSTATUS (0x4100A024) /**< \brief (DMAC) Interrupt Status */
#define REG_DMAC_BUSYCH (0x4100A028) /**< \brief (DMAC) Busy Channels */
#define REG_DMAC_PENDCH (0x4100A02C) /**< \brief (DMAC) Pending Channels */
#define REG_DMAC_ACTIVE (0x4100A030) /**< \brief (DMAC) Active Channel and Levels */
#define REG_DMAC_BASEADDR (0x4100A034) /**< \brief (DMAC) Descriptor Memory Section Base Address */
#define REG_DMAC_WRBADDR (0x4100A038) /**< \brief (DMAC) Write-Back Memory Section Base Address */
#define REG_DMAC_CHCTRLA0 (0x4100A040) /**< \brief (DMAC) Channel 0 Control A */
#define REG_DMAC_CHCTRLB0 (0x4100A044) /**< \brief (DMAC) Channel 0 Control B */
#define REG_DMAC_CHPRILVL0 (0x4100A045) /**< \brief (DMAC) Channel 0 Priority Level */
#define REG_DMAC_CHEVCTRL0 (0x4100A046) /**< \brief (DMAC) Channel 0 Event Control */
#define REG_DMAC_CHINTENCLR0 (0x4100A04C) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET0 (0x4100A04D) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG0 (0x4100A04E) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS0 (0x4100A04F) /**< \brief (DMAC) Channel 0 Status */
#define REG_DMAC_CHCTRLA1 (0x4100A050) /**< \brief (DMAC) Channel 1 Control A */
#define REG_DMAC_CHCTRLB1 (0x4100A054) /**< \brief (DMAC) Channel 1 Control B */
#define REG_DMAC_CHPRILVL1 (0x4100A055) /**< \brief (DMAC) Channel 1 Priority Level */
#define REG_DMAC_CHEVCTRL1 (0x4100A056) /**< \brief (DMAC) Channel 1 Event Control */
#define REG_DMAC_CHINTENCLR1 (0x4100A05C) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET1 (0x4100A05D) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG1 (0x4100A05E) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS1 (0x4100A05F) /**< \brief (DMAC) Channel 1 Status */
#define REG_DMAC_CHCTRLA2 (0x4100A060) /**< \brief (DMAC) Channel 2 Control A */
#define REG_DMAC_CHCTRLB2 (0x4100A064) /**< \brief (DMAC) Channel 2 Control B */
#define REG_DMAC_CHPRILVL2 (0x4100A065) /**< \brief (DMAC) Channel 2 Priority Level */
#define REG_DMAC_CHEVCTRL2 (0x4100A066) /**< \brief (DMAC) Channel 2 Event Control */
#define REG_DMAC_CHINTENCLR2 (0x4100A06C) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET2 (0x4100A06D) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG2 (0x4100A06E) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS2 (0x4100A06F) /**< \brief (DMAC) Channel 2 Status */
#define REG_DMAC_CHCTRLA3 (0x4100A070) /**< \brief (DMAC) Channel 3 Control A */
#define REG_DMAC_CHCTRLB3 (0x4100A074) /**< \brief (DMAC) Channel 3 Control B */
#define REG_DMAC_CHPRILVL3 (0x4100A075) /**< \brief (DMAC) Channel 3 Priority Level */
#define REG_DMAC_CHEVCTRL3 (0x4100A076) /**< \brief (DMAC) Channel 3 Event Control */
#define REG_DMAC_CHINTENCLR3 (0x4100A07C) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET3 (0x4100A07D) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG3 (0x4100A07E) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS3 (0x4100A07F) /**< \brief (DMAC) Channel 3 Status */
#define REG_DMAC_CHCTRLA4 (0x4100A080) /**< \brief (DMAC) Channel 4 Control A */
#define REG_DMAC_CHCTRLB4 (0x4100A084) /**< \brief (DMAC) Channel 4 Control B */
#define REG_DMAC_CHPRILVL4 (0x4100A085) /**< \brief (DMAC) Channel 4 Priority Level */
#define REG_DMAC_CHEVCTRL4 (0x4100A086) /**< \brief (DMAC) Channel 4 Event Control */
#define REG_DMAC_CHINTENCLR4 (0x4100A08C) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET4 (0x4100A08D) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG4 (0x4100A08E) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS4 (0x4100A08F) /**< \brief (DMAC) Channel 4 Status */
#define REG_DMAC_CHCTRLA5 (0x4100A090) /**< \brief (DMAC) Channel 5 Control A */
#define REG_DMAC_CHCTRLB5 (0x4100A094) /**< \brief (DMAC) Channel 5 Control B */
#define REG_DMAC_CHPRILVL5 (0x4100A095) /**< \brief (DMAC) Channel 5 Priority Level */
#define REG_DMAC_CHEVCTRL5 (0x4100A096) /**< \brief (DMAC) Channel 5 Event Control */
#define REG_DMAC_CHINTENCLR5 (0x4100A09C) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET5 (0x4100A09D) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG5 (0x4100A09E) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS5 (0x4100A09F) /**< \brief (DMAC) Channel 5 Status */
#define REG_DMAC_CHCTRLA6 (0x4100A0A0) /**< \brief (DMAC) Channel 6 Control A */
#define REG_DMAC_CHCTRLB6 (0x4100A0A4) /**< \brief (DMAC) Channel 6 Control B */
#define REG_DMAC_CHPRILVL6 (0x4100A0A5) /**< \brief (DMAC) Channel 6 Priority Level */
#define REG_DMAC_CHEVCTRL6 (0x4100A0A6) /**< \brief (DMAC) Channel 6 Event Control */
#define REG_DMAC_CHINTENCLR6 (0x4100A0AC) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET6 (0x4100A0AD) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG6 (0x4100A0AE) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS6 (0x4100A0AF) /**< \brief (DMAC) Channel 6 Status */
#define REG_DMAC_CHCTRLA7 (0x4100A0B0) /**< \brief (DMAC) Channel 7 Control A */
#define REG_DMAC_CHCTRLB7 (0x4100A0B4) /**< \brief (DMAC) Channel 7 Control B */
#define REG_DMAC_CHPRILVL7 (0x4100A0B5) /**< \brief (DMAC) Channel 7 Priority Level */
#define REG_DMAC_CHEVCTRL7 (0x4100A0B6) /**< \brief (DMAC) Channel 7 Event Control */
#define REG_DMAC_CHINTENCLR7 (0x4100A0BC) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET7 (0x4100A0BD) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG7 (0x4100A0BE) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS7 (0x4100A0BF) /**< \brief (DMAC) Channel 7 Status */
#define REG_DMAC_CHCTRLA8 (0x4100A0C0) /**< \brief (DMAC) Channel 8 Control A */
#define REG_DMAC_CHCTRLB8 (0x4100A0C4) /**< \brief (DMAC) Channel 8 Control B */
#define REG_DMAC_CHPRILVL8 (0x4100A0C5) /**< \brief (DMAC) Channel 8 Priority Level */
#define REG_DMAC_CHEVCTRL8 (0x4100A0C6) /**< \brief (DMAC) Channel 8 Event Control */
#define REG_DMAC_CHINTENCLR8 (0x4100A0CC) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET8 (0x4100A0CD) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG8 (0x4100A0CE) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS8 (0x4100A0CF) /**< \brief (DMAC) Channel 8 Status */
#define REG_DMAC_CHCTRLA9 (0x4100A0D0) /**< \brief (DMAC) Channel 9 Control A */
#define REG_DMAC_CHCTRLB9 (0x4100A0D4) /**< \brief (DMAC) Channel 9 Control B */
#define REG_DMAC_CHPRILVL9 (0x4100A0D5) /**< \brief (DMAC) Channel 9 Priority Level */
#define REG_DMAC_CHEVCTRL9 (0x4100A0D6) /**< \brief (DMAC) Channel 9 Event Control */
#define REG_DMAC_CHINTENCLR9 (0x4100A0DC) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET9 (0x4100A0DD) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG9 (0x4100A0DE) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS9 (0x4100A0DF) /**< \brief (DMAC) Channel 9 Status */
#define REG_DMAC_CHCTRLA10 (0x4100A0E0) /**< \brief (DMAC) Channel 10 Control A */
#define REG_DMAC_CHCTRLB10 (0x4100A0E4) /**< \brief (DMAC) Channel 10 Control B */
#define REG_DMAC_CHPRILVL10 (0x4100A0E5) /**< \brief (DMAC) Channel 10 Priority Level */
#define REG_DMAC_CHEVCTRL10 (0x4100A0E6) /**< \brief (DMAC) Channel 10 Event Control */
#define REG_DMAC_CHINTENCLR10 (0x4100A0EC) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET10 (0x4100A0ED) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG10 (0x4100A0EE) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS10 (0x4100A0EF) /**< \brief (DMAC) Channel 10 Status */
#define REG_DMAC_CHCTRLA11 (0x4100A0F0) /**< \brief (DMAC) Channel 11 Control A */
#define REG_DMAC_CHCTRLB11 (0x4100A0F4) /**< \brief (DMAC) Channel 11 Control B */
#define REG_DMAC_CHPRILVL11 (0x4100A0F5) /**< \brief (DMAC) Channel 11 Priority Level */
#define REG_DMAC_CHEVCTRL11 (0x4100A0F6) /**< \brief (DMAC) Channel 11 Event Control */
#define REG_DMAC_CHINTENCLR11 (0x4100A0FC) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET11 (0x4100A0FD) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG11 (0x4100A0FE) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS11 (0x4100A0FF) /**< \brief (DMAC) Channel 11 Status */
#define REG_DMAC_CHCTRLA12 (0x4100A100) /**< \brief (DMAC) Channel 12 Control A */
#define REG_DMAC_CHCTRLB12 (0x4100A104) /**< \brief (DMAC) Channel 12 Control B */
#define REG_DMAC_CHPRILVL12 (0x4100A105) /**< \brief (DMAC) Channel 12 Priority Level */
#define REG_DMAC_CHEVCTRL12 (0x4100A106) /**< \brief (DMAC) Channel 12 Event Control */
#define REG_DMAC_CHINTENCLR12 (0x4100A10C) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET12 (0x4100A10D) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG12 (0x4100A10E) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS12 (0x4100A10F) /**< \brief (DMAC) Channel 12 Status */
#define REG_DMAC_CHCTRLA13 (0x4100A110) /**< \brief (DMAC) Channel 13 Control A */
#define REG_DMAC_CHCTRLB13 (0x4100A114) /**< \brief (DMAC) Channel 13 Control B */
#define REG_DMAC_CHPRILVL13 (0x4100A115) /**< \brief (DMAC) Channel 13 Priority Level */
#define REG_DMAC_CHEVCTRL13 (0x4100A116) /**< \brief (DMAC) Channel 13 Event Control */
#define REG_DMAC_CHINTENCLR13 (0x4100A11C) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET13 (0x4100A11D) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG13 (0x4100A11E) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS13 (0x4100A11F) /**< \brief (DMAC) Channel 13 Status */
#define REG_DMAC_CHCTRLA14 (0x4100A120) /**< \brief (DMAC) Channel 14 Control A */
#define REG_DMAC_CHCTRLB14 (0x4100A124) /**< \brief (DMAC) Channel 14 Control B */
#define REG_DMAC_CHPRILVL14 (0x4100A125) /**< \brief (DMAC) Channel 14 Priority Level */
#define REG_DMAC_CHEVCTRL14 (0x4100A126) /**< \brief (DMAC) Channel 14 Event Control */
#define REG_DMAC_CHINTENCLR14 (0x4100A12C) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET14 (0x4100A12D) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG14 (0x4100A12E) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS14 (0x4100A12F) /**< \brief (DMAC) Channel 14 Status */
#define REG_DMAC_CHCTRLA15 (0x4100A130) /**< \brief (DMAC) Channel 15 Control A */
#define REG_DMAC_CHCTRLB15 (0x4100A134) /**< \brief (DMAC) Channel 15 Control B */
#define REG_DMAC_CHPRILVL15 (0x4100A135) /**< \brief (DMAC) Channel 15 Priority Level */
#define REG_DMAC_CHEVCTRL15 (0x4100A136) /**< \brief (DMAC) Channel 15 Event Control */
#define REG_DMAC_CHINTENCLR15 (0x4100A13C) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET15 (0x4100A13D) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG15 (0x4100A13E) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS15 (0x4100A13F) /**< \brief (DMAC) Channel 15 Status */
#define REG_DMAC_CHCTRLA16 (0x4100A140) /**< \brief (DMAC) Channel 16 Control A */
#define REG_DMAC_CHCTRLB16 (0x4100A144) /**< \brief (DMAC) Channel 16 Control B */
#define REG_DMAC_CHPRILVL16 (0x4100A145) /**< \brief (DMAC) Channel 16 Priority Level */
#define REG_DMAC_CHEVCTRL16 (0x4100A146) /**< \brief (DMAC) Channel 16 Event Control */
#define REG_DMAC_CHINTENCLR16 (0x4100A14C) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET16 (0x4100A14D) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG16 (0x4100A14E) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS16 (0x4100A14F) /**< \brief (DMAC) Channel 16 Status */
#define REG_DMAC_CHCTRLA17 (0x4100A150) /**< \brief (DMAC) Channel 17 Control A */
#define REG_DMAC_CHCTRLB17 (0x4100A154) /**< \brief (DMAC) Channel 17 Control B */
#define REG_DMAC_CHPRILVL17 (0x4100A155) /**< \brief (DMAC) Channel 17 Priority Level */
#define REG_DMAC_CHEVCTRL17 (0x4100A156) /**< \brief (DMAC) Channel 17 Event Control */
#define REG_DMAC_CHINTENCLR17 (0x4100A15C) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET17 (0x4100A15D) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG17 (0x4100A15E) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS17 (0x4100A15F) /**< \brief (DMAC) Channel 17 Status */
#define REG_DMAC_CHCTRLA18 (0x4100A160) /**< \brief (DMAC) Channel 18 Control A */
#define REG_DMAC_CHCTRLB18 (0x4100A164) /**< \brief (DMAC) Channel 18 Control B */
#define REG_DMAC_CHPRILVL18 (0x4100A165) /**< \brief (DMAC) Channel 18 Priority Level */
#define REG_DMAC_CHEVCTRL18 (0x4100A166) /**< \brief (DMAC) Channel 18 Event Control */
#define REG_DMAC_CHINTENCLR18 (0x4100A16C) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET18 (0x4100A16D) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG18 (0x4100A16E) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS18 (0x4100A16F) /**< \brief (DMAC) Channel 18 Status */
#define REG_DMAC_CHCTRLA19 (0x4100A170) /**< \brief (DMAC) Channel 19 Control A */
#define REG_DMAC_CHCTRLB19 (0x4100A174) /**< \brief (DMAC) Channel 19 Control B */
#define REG_DMAC_CHPRILVL19 (0x4100A175) /**< \brief (DMAC) Channel 19 Priority Level */
#define REG_DMAC_CHEVCTRL19 (0x4100A176) /**< \brief (DMAC) Channel 19 Event Control */
#define REG_DMAC_CHINTENCLR19 (0x4100A17C) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET19 (0x4100A17D) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG19 (0x4100A17E) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS19 (0x4100A17F) /**< \brief (DMAC) Channel 19 Status */
#define REG_DMAC_CHCTRLA20 (0x4100A180) /**< \brief (DMAC) Channel 20 Control A */
#define REG_DMAC_CHCTRLB20 (0x4100A184) /**< \brief (DMAC) Channel 20 Control B */
#define REG_DMAC_CHPRILVL20 (0x4100A185) /**< \brief (DMAC) Channel 20 Priority Level */
#define REG_DMAC_CHEVCTRL20 (0x4100A186) /**< \brief (DMAC) Channel 20 Event Control */
#define REG_DMAC_CHINTENCLR20 (0x4100A18C) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET20 (0x4100A18D) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG20 (0x4100A18E) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS20 (0x4100A18F) /**< \brief (DMAC) Channel 20 Status */
#define REG_DMAC_CHCTRLA21 (0x4100A190) /**< \brief (DMAC) Channel 21 Control A */
#define REG_DMAC_CHCTRLB21 (0x4100A194) /**< \brief (DMAC) Channel 21 Control B */
#define REG_DMAC_CHPRILVL21 (0x4100A195) /**< \brief (DMAC) Channel 21 Priority Level */
#define REG_DMAC_CHEVCTRL21 (0x4100A196) /**< \brief (DMAC) Channel 21 Event Control */
#define REG_DMAC_CHINTENCLR21 (0x4100A19C) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET21 (0x4100A19D) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG21 (0x4100A19E) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS21 (0x4100A19F) /**< \brief (DMAC) Channel 21 Status */
#define REG_DMAC_CHCTRLA22 (0x4100A1A0) /**< \brief (DMAC) Channel 22 Control A */
#define REG_DMAC_CHCTRLB22 (0x4100A1A4) /**< \brief (DMAC) Channel 22 Control B */
#define REG_DMAC_CHPRILVL22 (0x4100A1A5) /**< \brief (DMAC) Channel 22 Priority Level */
#define REG_DMAC_CHEVCTRL22 (0x4100A1A6) /**< \brief (DMAC) Channel 22 Event Control */
#define REG_DMAC_CHINTENCLR22 (0x4100A1AC) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET22 (0x4100A1AD) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG22 (0x4100A1AE) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS22 (0x4100A1AF) /**< \brief (DMAC) Channel 22 Status */
#define REG_DMAC_CHCTRLA23 (0x4100A1B0) /**< \brief (DMAC) Channel 23 Control A */
#define REG_DMAC_CHCTRLB23 (0x4100A1B4) /**< \brief (DMAC) Channel 23 Control B */
#define REG_DMAC_CHPRILVL23 (0x4100A1B5) /**< \brief (DMAC) Channel 23 Priority Level */
#define REG_DMAC_CHEVCTRL23 (0x4100A1B6) /**< \brief (DMAC) Channel 23 Event Control */
#define REG_DMAC_CHINTENCLR23 (0x4100A1BC) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET23 (0x4100A1BD) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG23 (0x4100A1BE) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS23 (0x4100A1BF) /**< \brief (DMAC) Channel 23 Status */
#define REG_DMAC_CHCTRLA24 (0x4100A1C0) /**< \brief (DMAC) Channel 24 Control A */
#define REG_DMAC_CHCTRLB24 (0x4100A1C4) /**< \brief (DMAC) Channel 24 Control B */
#define REG_DMAC_CHPRILVL24 (0x4100A1C5) /**< \brief (DMAC) Channel 24 Priority Level */
#define REG_DMAC_CHEVCTRL24 (0x4100A1C6) /**< \brief (DMAC) Channel 24 Event Control */
#define REG_DMAC_CHINTENCLR24 (0x4100A1CC) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET24 (0x4100A1CD) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG24 (0x4100A1CE) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS24 (0x4100A1CF) /**< \brief (DMAC) Channel 24 Status */
#define REG_DMAC_CHCTRLA25 (0x4100A1D0) /**< \brief (DMAC) Channel 25 Control A */
#define REG_DMAC_CHCTRLB25 (0x4100A1D4) /**< \brief (DMAC) Channel 25 Control B */
#define REG_DMAC_CHPRILVL25 (0x4100A1D5) /**< \brief (DMAC) Channel 25 Priority Level */
#define REG_DMAC_CHEVCTRL25 (0x4100A1D6) /**< \brief (DMAC) Channel 25 Event Control */
#define REG_DMAC_CHINTENCLR25 (0x4100A1DC) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET25 (0x4100A1DD) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG25 (0x4100A1DE) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS25 (0x4100A1DF) /**< \brief (DMAC) Channel 25 Status */
#define REG_DMAC_CHCTRLA26 (0x4100A1E0) /**< \brief (DMAC) Channel 26 Control A */
#define REG_DMAC_CHCTRLB26 (0x4100A1E4) /**< \brief (DMAC) Channel 26 Control B */
#define REG_DMAC_CHPRILVL26 (0x4100A1E5) /**< \brief (DMAC) Channel 26 Priority Level */
#define REG_DMAC_CHEVCTRL26 (0x4100A1E6) /**< \brief (DMAC) Channel 26 Event Control */
#define REG_DMAC_CHINTENCLR26 (0x4100A1EC) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET26 (0x4100A1ED) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG26 (0x4100A1EE) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS26 (0x4100A1EF) /**< \brief (DMAC) Channel 26 Status */
#define REG_DMAC_CHCTRLA27 (0x4100A1F0) /**< \brief (DMAC) Channel 27 Control A */
#define REG_DMAC_CHCTRLB27 (0x4100A1F4) /**< \brief (DMAC) Channel 27 Control B */
#define REG_DMAC_CHPRILVL27 (0x4100A1F5) /**< \brief (DMAC) Channel 27 Priority Level */
#define REG_DMAC_CHEVCTRL27 (0x4100A1F6) /**< \brief (DMAC) Channel 27 Event Control */
#define REG_DMAC_CHINTENCLR27 (0x4100A1FC) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET27 (0x4100A1FD) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG27 (0x4100A1FE) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS27 (0x4100A1FF) /**< \brief (DMAC) Channel 27 Status */
#define REG_DMAC_CHCTRLA28 (0x4100A200) /**< \brief (DMAC) Channel 28 Control A */
#define REG_DMAC_CHCTRLB28 (0x4100A204) /**< \brief (DMAC) Channel 28 Control B */
#define REG_DMAC_CHPRILVL28 (0x4100A205) /**< \brief (DMAC) Channel 28 Priority Level */
#define REG_DMAC_CHEVCTRL28 (0x4100A206) /**< \brief (DMAC) Channel 28 Event Control */
#define REG_DMAC_CHINTENCLR28 (0x4100A20C) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET28 (0x4100A20D) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG28 (0x4100A20E) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS28 (0x4100A20F) /**< \brief (DMAC) Channel 28 Status */
#define REG_DMAC_CHCTRLA29 (0x4100A210) /**< \brief (DMAC) Channel 29 Control A */
#define REG_DMAC_CHCTRLB29 (0x4100A214) /**< \brief (DMAC) Channel 29 Control B */
#define REG_DMAC_CHPRILVL29 (0x4100A215) /**< \brief (DMAC) Channel 29 Priority Level */
#define REG_DMAC_CHEVCTRL29 (0x4100A216) /**< \brief (DMAC) Channel 29 Event Control */
#define REG_DMAC_CHINTENCLR29 (0x4100A21C) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET29 (0x4100A21D) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG29 (0x4100A21E) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS29 (0x4100A21F) /**< \brief (DMAC) Channel 29 Status */
#define REG_DMAC_CHCTRLA30 (0x4100A220) /**< \brief (DMAC) Channel 30 Control A */
#define REG_DMAC_CHCTRLB30 (0x4100A224) /**< \brief (DMAC) Channel 30 Control B */
#define REG_DMAC_CHPRILVL30 (0x4100A225) /**< \brief (DMAC) Channel 30 Priority Level */
#define REG_DMAC_CHEVCTRL30 (0x4100A226) /**< \brief (DMAC) Channel 30 Event Control */
#define REG_DMAC_CHINTENCLR30 (0x4100A22C) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET30 (0x4100A22D) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG30 (0x4100A22E) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS30 (0x4100A22F) /**< \brief (DMAC) Channel 30 Status */
#define REG_DMAC_CHCTRLA31 (0x4100A230) /**< \brief (DMAC) Channel 31 Control A */
#define REG_DMAC_CHCTRLB31 (0x4100A234) /**< \brief (DMAC) Channel 31 Control B */
#define REG_DMAC_CHPRILVL31 (0x4100A235) /**< \brief (DMAC) Channel 31 Priority Level */
#define REG_DMAC_CHEVCTRL31 (0x4100A236) /**< \brief (DMAC) Channel 31 Event Control */
#define REG_DMAC_CHINTENCLR31 (0x4100A23C) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET31 (0x4100A23D) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG31 (0x4100A23E) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS31 (0x4100A23F) /**< \brief (DMAC) Channel 31 Status */
#else
#define REG_DMAC_CTRL (*(RwReg16*)0x4100A000UL) /**< \brief (DMAC) Control */
#define REG_DMAC_CRCCTRL (*(RwReg16*)0x4100A002UL) /**< \brief (DMAC) CRC Control */
#define REG_DMAC_CRCDATAIN (*(RwReg *)0x4100A004UL) /**< \brief (DMAC) CRC Data Input */
#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x4100A008UL) /**< \brief (DMAC) CRC Checksum */
#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100A00CUL) /**< \brief (DMAC) CRC Status */
#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100A00DUL) /**< \brief (DMAC) Debug Control */
#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x4100A010UL) /**< \brief (DMAC) Software Trigger Control */
#define REG_DMAC_PRICTRL0 (*(RwReg *)0x4100A014UL) /**< \brief (DMAC) Priority Control 0 */
#define REG_DMAC_INTPEND (*(RwReg16*)0x4100A020UL) /**< \brief (DMAC) Interrupt Pending */
#define REG_DMAC_INTSTATUS (*(RoReg *)0x4100A024UL) /**< \brief (DMAC) Interrupt Status */
#define REG_DMAC_BUSYCH (*(RoReg *)0x4100A028UL) /**< \brief (DMAC) Busy Channels */
#define REG_DMAC_PENDCH (*(RoReg *)0x4100A02CUL) /**< \brief (DMAC) Pending Channels */
#define REG_DMAC_ACTIVE (*(RoReg *)0x4100A030UL) /**< \brief (DMAC) Active Channel and Levels */
#define REG_DMAC_BASEADDR (*(RwReg *)0x4100A034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
#define REG_DMAC_WRBADDR (*(RwReg *)0x4100A038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
#define REG_DMAC_CHCTRLA0 (*(RwReg *)0x4100A040UL) /**< \brief (DMAC) Channel 0 Control A */
#define REG_DMAC_CHCTRLB0 (*(RwReg *)0x4100A044UL) /**< \brief (DMAC) Channel 0 Control B */
#define REG_DMAC_CHPRILVL0 (*(RwReg *)0x4100A045UL) /**< \brief (DMAC) Channel 0 Priority Level */
#define REG_DMAC_CHEVCTRL0 (*(RwReg *)0x4100A046UL) /**< \brief (DMAC) Channel 0 Event Control */
#define REG_DMAC_CHINTENCLR0 (*(RwReg *)0x4100A04CUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET0 (*(RwReg *)0x4100A04DUL) /**< \brief (DMAC) Channel 0 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG0 (*(RwReg *)0x4100A04EUL) /**< \brief (DMAC) Channel 0 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS0 (*(RwReg *)0x4100A04FUL) /**< \brief (DMAC) Channel 0 Status */
#define REG_DMAC_CHCTRLA1 (*(RwReg *)0x4100A050UL) /**< \brief (DMAC) Channel 1 Control A */
#define REG_DMAC_CHCTRLB1 (*(RwReg *)0x4100A054UL) /**< \brief (DMAC) Channel 1 Control B */
#define REG_DMAC_CHPRILVL1 (*(RwReg *)0x4100A055UL) /**< \brief (DMAC) Channel 1 Priority Level */
#define REG_DMAC_CHEVCTRL1 (*(RwReg *)0x4100A056UL) /**< \brief (DMAC) Channel 1 Event Control */
#define REG_DMAC_CHINTENCLR1 (*(RwReg *)0x4100A05CUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET1 (*(RwReg *)0x4100A05DUL) /**< \brief (DMAC) Channel 1 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG1 (*(RwReg *)0x4100A05EUL) /**< \brief (DMAC) Channel 1 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS1 (*(RwReg *)0x4100A05FUL) /**< \brief (DMAC) Channel 1 Status */
#define REG_DMAC_CHCTRLA2 (*(RwReg *)0x4100A060UL) /**< \brief (DMAC) Channel 2 Control A */
#define REG_DMAC_CHCTRLB2 (*(RwReg *)0x4100A064UL) /**< \brief (DMAC) Channel 2 Control B */
#define REG_DMAC_CHPRILVL2 (*(RwReg *)0x4100A065UL) /**< \brief (DMAC) Channel 2 Priority Level */
#define REG_DMAC_CHEVCTRL2 (*(RwReg *)0x4100A066UL) /**< \brief (DMAC) Channel 2 Event Control */
#define REG_DMAC_CHINTENCLR2 (*(RwReg *)0x4100A06CUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET2 (*(RwReg *)0x4100A06DUL) /**< \brief (DMAC) Channel 2 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG2 (*(RwReg *)0x4100A06EUL) /**< \brief (DMAC) Channel 2 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS2 (*(RwReg *)0x4100A06FUL) /**< \brief (DMAC) Channel 2 Status */
#define REG_DMAC_CHCTRLA3 (*(RwReg *)0x4100A070UL) /**< \brief (DMAC) Channel 3 Control A */
#define REG_DMAC_CHCTRLB3 (*(RwReg *)0x4100A074UL) /**< \brief (DMAC) Channel 3 Control B */
#define REG_DMAC_CHPRILVL3 (*(RwReg *)0x4100A075UL) /**< \brief (DMAC) Channel 3 Priority Level */
#define REG_DMAC_CHEVCTRL3 (*(RwReg *)0x4100A076UL) /**< \brief (DMAC) Channel 3 Event Control */
#define REG_DMAC_CHINTENCLR3 (*(RwReg *)0x4100A07CUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET3 (*(RwReg *)0x4100A07DUL) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG3 (*(RwReg *)0x4100A07EUL) /**< \brief (DMAC) Channel 3 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS3 (*(RwReg *)0x4100A07FUL) /**< \brief (DMAC) Channel 3 Status */
#define REG_DMAC_CHCTRLA4 (*(RwReg *)0x4100A080UL) /**< \brief (DMAC) Channel 4 Control A */
#define REG_DMAC_CHCTRLB4 (*(RwReg *)0x4100A084UL) /**< \brief (DMAC) Channel 4 Control B */
#define REG_DMAC_CHPRILVL4 (*(RwReg *)0x4100A085UL) /**< \brief (DMAC) Channel 4 Priority Level */
#define REG_DMAC_CHEVCTRL4 (*(RwReg *)0x4100A086UL) /**< \brief (DMAC) Channel 4 Event Control */
#define REG_DMAC_CHINTENCLR4 (*(RwReg *)0x4100A08CUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET4 (*(RwReg *)0x4100A08DUL) /**< \brief (DMAC) Channel 4 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG4 (*(RwReg *)0x4100A08EUL) /**< \brief (DMAC) Channel 4 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS4 (*(RwReg *)0x4100A08FUL) /**< \brief (DMAC) Channel 4 Status */
#define REG_DMAC_CHCTRLA5 (*(RwReg *)0x4100A090UL) /**< \brief (DMAC) Channel 5 Control A */
#define REG_DMAC_CHCTRLB5 (*(RwReg *)0x4100A094UL) /**< \brief (DMAC) Channel 5 Control B */
#define REG_DMAC_CHPRILVL5 (*(RwReg *)0x4100A095UL) /**< \brief (DMAC) Channel 5 Priority Level */
#define REG_DMAC_CHEVCTRL5 (*(RwReg *)0x4100A096UL) /**< \brief (DMAC) Channel 5 Event Control */
#define REG_DMAC_CHINTENCLR5 (*(RwReg *)0x4100A09CUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET5 (*(RwReg *)0x4100A09DUL) /**< \brief (DMAC) Channel 5 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG5 (*(RwReg *)0x4100A09EUL) /**< \brief (DMAC) Channel 5 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS5 (*(RwReg *)0x4100A09FUL) /**< \brief (DMAC) Channel 5 Status */
#define REG_DMAC_CHCTRLA6 (*(RwReg *)0x4100A0A0UL) /**< \brief (DMAC) Channel 6 Control A */
#define REG_DMAC_CHCTRLB6 (*(RwReg *)0x4100A0A4UL) /**< \brief (DMAC) Channel 6 Control B */
#define REG_DMAC_CHPRILVL6 (*(RwReg *)0x4100A0A5UL) /**< \brief (DMAC) Channel 6 Priority Level */
#define REG_DMAC_CHEVCTRL6 (*(RwReg *)0x4100A0A6UL) /**< \brief (DMAC) Channel 6 Event Control */
#define REG_DMAC_CHINTENCLR6 (*(RwReg *)0x4100A0ACUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET6 (*(RwReg *)0x4100A0ADUL) /**< \brief (DMAC) Channel 6 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG6 (*(RwReg *)0x4100A0AEUL) /**< \brief (DMAC) Channel 6 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS6 (*(RwReg *)0x4100A0AFUL) /**< \brief (DMAC) Channel 6 Status */
#define REG_DMAC_CHCTRLA7 (*(RwReg *)0x4100A0B0UL) /**< \brief (DMAC) Channel 7 Control A */
#define REG_DMAC_CHCTRLB7 (*(RwReg *)0x4100A0B4UL) /**< \brief (DMAC) Channel 7 Control B */
#define REG_DMAC_CHPRILVL7 (*(RwReg *)0x4100A0B5UL) /**< \brief (DMAC) Channel 7 Priority Level */
#define REG_DMAC_CHEVCTRL7 (*(RwReg *)0x4100A0B6UL) /**< \brief (DMAC) Channel 7 Event Control */
#define REG_DMAC_CHINTENCLR7 (*(RwReg *)0x4100A0BCUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET7 (*(RwReg *)0x4100A0BDUL) /**< \brief (DMAC) Channel 7 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG7 (*(RwReg *)0x4100A0BEUL) /**< \brief (DMAC) Channel 7 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS7 (*(RwReg *)0x4100A0BFUL) /**< \brief (DMAC) Channel 7 Status */
#define REG_DMAC_CHCTRLA8 (*(RwReg *)0x4100A0C0UL) /**< \brief (DMAC) Channel 8 Control A */
#define REG_DMAC_CHCTRLB8 (*(RwReg *)0x4100A0C4UL) /**< \brief (DMAC) Channel 8 Control B */
#define REG_DMAC_CHPRILVL8 (*(RwReg *)0x4100A0C5UL) /**< \brief (DMAC) Channel 8 Priority Level */
#define REG_DMAC_CHEVCTRL8 (*(RwReg *)0x4100A0C6UL) /**< \brief (DMAC) Channel 8 Event Control */
#define REG_DMAC_CHINTENCLR8 (*(RwReg *)0x4100A0CCUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET8 (*(RwReg *)0x4100A0CDUL) /**< \brief (DMAC) Channel 8 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG8 (*(RwReg *)0x4100A0CEUL) /**< \brief (DMAC) Channel 8 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS8 (*(RwReg *)0x4100A0CFUL) /**< \brief (DMAC) Channel 8 Status */
#define REG_DMAC_CHCTRLA9 (*(RwReg *)0x4100A0D0UL) /**< \brief (DMAC) Channel 9 Control A */
#define REG_DMAC_CHCTRLB9 (*(RwReg *)0x4100A0D4UL) /**< \brief (DMAC) Channel 9 Control B */
#define REG_DMAC_CHPRILVL9 (*(RwReg *)0x4100A0D5UL) /**< \brief (DMAC) Channel 9 Priority Level */
#define REG_DMAC_CHEVCTRL9 (*(RwReg *)0x4100A0D6UL) /**< \brief (DMAC) Channel 9 Event Control */
#define REG_DMAC_CHINTENCLR9 (*(RwReg *)0x4100A0DCUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET9 (*(RwReg *)0x4100A0DDUL) /**< \brief (DMAC) Channel 9 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG9 (*(RwReg *)0x4100A0DEUL) /**< \brief (DMAC) Channel 9 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS9 (*(RwReg *)0x4100A0DFUL) /**< \brief (DMAC) Channel 9 Status */
#define REG_DMAC_CHCTRLA10 (*(RwReg *)0x4100A0E0UL) /**< \brief (DMAC) Channel 10 Control A */
#define REG_DMAC_CHCTRLB10 (*(RwReg *)0x4100A0E4UL) /**< \brief (DMAC) Channel 10 Control B */
#define REG_DMAC_CHPRILVL10 (*(RwReg *)0x4100A0E5UL) /**< \brief (DMAC) Channel 10 Priority Level */
#define REG_DMAC_CHEVCTRL10 (*(RwReg *)0x4100A0E6UL) /**< \brief (DMAC) Channel 10 Event Control */
#define REG_DMAC_CHINTENCLR10 (*(RwReg *)0x4100A0ECUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET10 (*(RwReg *)0x4100A0EDUL) /**< \brief (DMAC) Channel 10 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG10 (*(RwReg *)0x4100A0EEUL) /**< \brief (DMAC) Channel 10 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS10 (*(RwReg *)0x4100A0EFUL) /**< \brief (DMAC) Channel 10 Status */
#define REG_DMAC_CHCTRLA11 (*(RwReg *)0x4100A0F0UL) /**< \brief (DMAC) Channel 11 Control A */
#define REG_DMAC_CHCTRLB11 (*(RwReg *)0x4100A0F4UL) /**< \brief (DMAC) Channel 11 Control B */
#define REG_DMAC_CHPRILVL11 (*(RwReg *)0x4100A0F5UL) /**< \brief (DMAC) Channel 11 Priority Level */
#define REG_DMAC_CHEVCTRL11 (*(RwReg *)0x4100A0F6UL) /**< \brief (DMAC) Channel 11 Event Control */
#define REG_DMAC_CHINTENCLR11 (*(RwReg *)0x4100A0FCUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET11 (*(RwReg *)0x4100A0FDUL) /**< \brief (DMAC) Channel 11 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG11 (*(RwReg *)0x4100A0FEUL) /**< \brief (DMAC) Channel 11 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS11 (*(RwReg *)0x4100A0FFUL) /**< \brief (DMAC) Channel 11 Status */
#define REG_DMAC_CHCTRLA12 (*(RwReg *)0x4100A100UL) /**< \brief (DMAC) Channel 12 Control A */
#define REG_DMAC_CHCTRLB12 (*(RwReg *)0x4100A104UL) /**< \brief (DMAC) Channel 12 Control B */
#define REG_DMAC_CHPRILVL12 (*(RwReg *)0x4100A105UL) /**< \brief (DMAC) Channel 12 Priority Level */
#define REG_DMAC_CHEVCTRL12 (*(RwReg *)0x4100A106UL) /**< \brief (DMAC) Channel 12 Event Control */
#define REG_DMAC_CHINTENCLR12 (*(RwReg *)0x4100A10CUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET12 (*(RwReg *)0x4100A10DUL) /**< \brief (DMAC) Channel 12 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG12 (*(RwReg *)0x4100A10EUL) /**< \brief (DMAC) Channel 12 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS12 (*(RwReg *)0x4100A10FUL) /**< \brief (DMAC) Channel 12 Status */
#define REG_DMAC_CHCTRLA13 (*(RwReg *)0x4100A110UL) /**< \brief (DMAC) Channel 13 Control A */
#define REG_DMAC_CHCTRLB13 (*(RwReg *)0x4100A114UL) /**< \brief (DMAC) Channel 13 Control B */
#define REG_DMAC_CHPRILVL13 (*(RwReg *)0x4100A115UL) /**< \brief (DMAC) Channel 13 Priority Level */
#define REG_DMAC_CHEVCTRL13 (*(RwReg *)0x4100A116UL) /**< \brief (DMAC) Channel 13 Event Control */
#define REG_DMAC_CHINTENCLR13 (*(RwReg *)0x4100A11CUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET13 (*(RwReg *)0x4100A11DUL) /**< \brief (DMAC) Channel 13 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG13 (*(RwReg *)0x4100A11EUL) /**< \brief (DMAC) Channel 13 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS13 (*(RwReg *)0x4100A11FUL) /**< \brief (DMAC) Channel 13 Status */
#define REG_DMAC_CHCTRLA14 (*(RwReg *)0x4100A120UL) /**< \brief (DMAC) Channel 14 Control A */
#define REG_DMAC_CHCTRLB14 (*(RwReg *)0x4100A124UL) /**< \brief (DMAC) Channel 14 Control B */
#define REG_DMAC_CHPRILVL14 (*(RwReg *)0x4100A125UL) /**< \brief (DMAC) Channel 14 Priority Level */
#define REG_DMAC_CHEVCTRL14 (*(RwReg *)0x4100A126UL) /**< \brief (DMAC) Channel 14 Event Control */
#define REG_DMAC_CHINTENCLR14 (*(RwReg *)0x4100A12CUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET14 (*(RwReg *)0x4100A12DUL) /**< \brief (DMAC) Channel 14 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG14 (*(RwReg *)0x4100A12EUL) /**< \brief (DMAC) Channel 14 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS14 (*(RwReg *)0x4100A12FUL) /**< \brief (DMAC) Channel 14 Status */
#define REG_DMAC_CHCTRLA15 (*(RwReg *)0x4100A130UL) /**< \brief (DMAC) Channel 15 Control A */
#define REG_DMAC_CHCTRLB15 (*(RwReg *)0x4100A134UL) /**< \brief (DMAC) Channel 15 Control B */
#define REG_DMAC_CHPRILVL15 (*(RwReg *)0x4100A135UL) /**< \brief (DMAC) Channel 15 Priority Level */
#define REG_DMAC_CHEVCTRL15 (*(RwReg *)0x4100A136UL) /**< \brief (DMAC) Channel 15 Event Control */
#define REG_DMAC_CHINTENCLR15 (*(RwReg *)0x4100A13CUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET15 (*(RwReg *)0x4100A13DUL) /**< \brief (DMAC) Channel 15 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG15 (*(RwReg *)0x4100A13EUL) /**< \brief (DMAC) Channel 15 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS15 (*(RwReg *)0x4100A13FUL) /**< \brief (DMAC) Channel 15 Status */
#define REG_DMAC_CHCTRLA16 (*(RwReg *)0x4100A140UL) /**< \brief (DMAC) Channel 16 Control A */
#define REG_DMAC_CHCTRLB16 (*(RwReg *)0x4100A144UL) /**< \brief (DMAC) Channel 16 Control B */
#define REG_DMAC_CHPRILVL16 (*(RwReg *)0x4100A145UL) /**< \brief (DMAC) Channel 16 Priority Level */
#define REG_DMAC_CHEVCTRL16 (*(RwReg *)0x4100A146UL) /**< \brief (DMAC) Channel 16 Event Control */
#define REG_DMAC_CHINTENCLR16 (*(RwReg *)0x4100A14CUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET16 (*(RwReg *)0x4100A14DUL) /**< \brief (DMAC) Channel 16 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG16 (*(RwReg *)0x4100A14EUL) /**< \brief (DMAC) Channel 16 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS16 (*(RwReg *)0x4100A14FUL) /**< \brief (DMAC) Channel 16 Status */
#define REG_DMAC_CHCTRLA17 (*(RwReg *)0x4100A150UL) /**< \brief (DMAC) Channel 17 Control A */
#define REG_DMAC_CHCTRLB17 (*(RwReg *)0x4100A154UL) /**< \brief (DMAC) Channel 17 Control B */
#define REG_DMAC_CHPRILVL17 (*(RwReg *)0x4100A155UL) /**< \brief (DMAC) Channel 17 Priority Level */
#define REG_DMAC_CHEVCTRL17 (*(RwReg *)0x4100A156UL) /**< \brief (DMAC) Channel 17 Event Control */
#define REG_DMAC_CHINTENCLR17 (*(RwReg *)0x4100A15CUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET17 (*(RwReg *)0x4100A15DUL) /**< \brief (DMAC) Channel 17 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG17 (*(RwReg *)0x4100A15EUL) /**< \brief (DMAC) Channel 17 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS17 (*(RwReg *)0x4100A15FUL) /**< \brief (DMAC) Channel 17 Status */
#define REG_DMAC_CHCTRLA18 (*(RwReg *)0x4100A160UL) /**< \brief (DMAC) Channel 18 Control A */
#define REG_DMAC_CHCTRLB18 (*(RwReg *)0x4100A164UL) /**< \brief (DMAC) Channel 18 Control B */
#define REG_DMAC_CHPRILVL18 (*(RwReg *)0x4100A165UL) /**< \brief (DMAC) Channel 18 Priority Level */
#define REG_DMAC_CHEVCTRL18 (*(RwReg *)0x4100A166UL) /**< \brief (DMAC) Channel 18 Event Control */
#define REG_DMAC_CHINTENCLR18 (*(RwReg *)0x4100A16CUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET18 (*(RwReg *)0x4100A16DUL) /**< \brief (DMAC) Channel 18 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG18 (*(RwReg *)0x4100A16EUL) /**< \brief (DMAC) Channel 18 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS18 (*(RwReg *)0x4100A16FUL) /**< \brief (DMAC) Channel 18 Status */
#define REG_DMAC_CHCTRLA19 (*(RwReg *)0x4100A170UL) /**< \brief (DMAC) Channel 19 Control A */
#define REG_DMAC_CHCTRLB19 (*(RwReg *)0x4100A174UL) /**< \brief (DMAC) Channel 19 Control B */
#define REG_DMAC_CHPRILVL19 (*(RwReg *)0x4100A175UL) /**< \brief (DMAC) Channel 19 Priority Level */
#define REG_DMAC_CHEVCTRL19 (*(RwReg *)0x4100A176UL) /**< \brief (DMAC) Channel 19 Event Control */
#define REG_DMAC_CHINTENCLR19 (*(RwReg *)0x4100A17CUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET19 (*(RwReg *)0x4100A17DUL) /**< \brief (DMAC) Channel 19 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG19 (*(RwReg *)0x4100A17EUL) /**< \brief (DMAC) Channel 19 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS19 (*(RwReg *)0x4100A17FUL) /**< \brief (DMAC) Channel 19 Status */
#define REG_DMAC_CHCTRLA20 (*(RwReg *)0x4100A180UL) /**< \brief (DMAC) Channel 20 Control A */
#define REG_DMAC_CHCTRLB20 (*(RwReg *)0x4100A184UL) /**< \brief (DMAC) Channel 20 Control B */
#define REG_DMAC_CHPRILVL20 (*(RwReg *)0x4100A185UL) /**< \brief (DMAC) Channel 20 Priority Level */
#define REG_DMAC_CHEVCTRL20 (*(RwReg *)0x4100A186UL) /**< \brief (DMAC) Channel 20 Event Control */
#define REG_DMAC_CHINTENCLR20 (*(RwReg *)0x4100A18CUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET20 (*(RwReg *)0x4100A18DUL) /**< \brief (DMAC) Channel 20 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG20 (*(RwReg *)0x4100A18EUL) /**< \brief (DMAC) Channel 20 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS20 (*(RwReg *)0x4100A18FUL) /**< \brief (DMAC) Channel 20 Status */
#define REG_DMAC_CHCTRLA21 (*(RwReg *)0x4100A190UL) /**< \brief (DMAC) Channel 21 Control A */
#define REG_DMAC_CHCTRLB21 (*(RwReg *)0x4100A194UL) /**< \brief (DMAC) Channel 21 Control B */
#define REG_DMAC_CHPRILVL21 (*(RwReg *)0x4100A195UL) /**< \brief (DMAC) Channel 21 Priority Level */
#define REG_DMAC_CHEVCTRL21 (*(RwReg *)0x4100A196UL) /**< \brief (DMAC) Channel 21 Event Control */
#define REG_DMAC_CHINTENCLR21 (*(RwReg *)0x4100A19CUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET21 (*(RwReg *)0x4100A19DUL) /**< \brief (DMAC) Channel 21 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG21 (*(RwReg *)0x4100A19EUL) /**< \brief (DMAC) Channel 21 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS21 (*(RwReg *)0x4100A19FUL) /**< \brief (DMAC) Channel 21 Status */
#define REG_DMAC_CHCTRLA22 (*(RwReg *)0x4100A1A0UL) /**< \brief (DMAC) Channel 22 Control A */
#define REG_DMAC_CHCTRLB22 (*(RwReg *)0x4100A1A4UL) /**< \brief (DMAC) Channel 22 Control B */
#define REG_DMAC_CHPRILVL22 (*(RwReg *)0x4100A1A5UL) /**< \brief (DMAC) Channel 22 Priority Level */
#define REG_DMAC_CHEVCTRL22 (*(RwReg *)0x4100A1A6UL) /**< \brief (DMAC) Channel 22 Event Control */
#define REG_DMAC_CHINTENCLR22 (*(RwReg *)0x4100A1ACUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET22 (*(RwReg *)0x4100A1ADUL) /**< \brief (DMAC) Channel 22 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG22 (*(RwReg *)0x4100A1AEUL) /**< \brief (DMAC) Channel 22 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS22 (*(RwReg *)0x4100A1AFUL) /**< \brief (DMAC) Channel 22 Status */
#define REG_DMAC_CHCTRLA23 (*(RwReg *)0x4100A1B0UL) /**< \brief (DMAC) Channel 23 Control A */
#define REG_DMAC_CHCTRLB23 (*(RwReg *)0x4100A1B4UL) /**< \brief (DMAC) Channel 23 Control B */
#define REG_DMAC_CHPRILVL23 (*(RwReg *)0x4100A1B5UL) /**< \brief (DMAC) Channel 23 Priority Level */
#define REG_DMAC_CHEVCTRL23 (*(RwReg *)0x4100A1B6UL) /**< \brief (DMAC) Channel 23 Event Control */
#define REG_DMAC_CHINTENCLR23 (*(RwReg *)0x4100A1BCUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET23 (*(RwReg *)0x4100A1BDUL) /**< \brief (DMAC) Channel 23 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG23 (*(RwReg *)0x4100A1BEUL) /**< \brief (DMAC) Channel 23 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS23 (*(RwReg *)0x4100A1BFUL) /**< \brief (DMAC) Channel 23 Status */
#define REG_DMAC_CHCTRLA24 (*(RwReg *)0x4100A1C0UL) /**< \brief (DMAC) Channel 24 Control A */
#define REG_DMAC_CHCTRLB24 (*(RwReg *)0x4100A1C4UL) /**< \brief (DMAC) Channel 24 Control B */
#define REG_DMAC_CHPRILVL24 (*(RwReg *)0x4100A1C5UL) /**< \brief (DMAC) Channel 24 Priority Level */
#define REG_DMAC_CHEVCTRL24 (*(RwReg *)0x4100A1C6UL) /**< \brief (DMAC) Channel 24 Event Control */
#define REG_DMAC_CHINTENCLR24 (*(RwReg *)0x4100A1CCUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET24 (*(RwReg *)0x4100A1CDUL) /**< \brief (DMAC) Channel 24 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG24 (*(RwReg *)0x4100A1CEUL) /**< \brief (DMAC) Channel 24 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS24 (*(RwReg *)0x4100A1CFUL) /**< \brief (DMAC) Channel 24 Status */
#define REG_DMAC_CHCTRLA25 (*(RwReg *)0x4100A1D0UL) /**< \brief (DMAC) Channel 25 Control A */
#define REG_DMAC_CHCTRLB25 (*(RwReg *)0x4100A1D4UL) /**< \brief (DMAC) Channel 25 Control B */
#define REG_DMAC_CHPRILVL25 (*(RwReg *)0x4100A1D5UL) /**< \brief (DMAC) Channel 25 Priority Level */
#define REG_DMAC_CHEVCTRL25 (*(RwReg *)0x4100A1D6UL) /**< \brief (DMAC) Channel 25 Event Control */
#define REG_DMAC_CHINTENCLR25 (*(RwReg *)0x4100A1DCUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET25 (*(RwReg *)0x4100A1DDUL) /**< \brief (DMAC) Channel 25 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG25 (*(RwReg *)0x4100A1DEUL) /**< \brief (DMAC) Channel 25 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS25 (*(RwReg *)0x4100A1DFUL) /**< \brief (DMAC) Channel 25 Status */
#define REG_DMAC_CHCTRLA26 (*(RwReg *)0x4100A1E0UL) /**< \brief (DMAC) Channel 26 Control A */
#define REG_DMAC_CHCTRLB26 (*(RwReg *)0x4100A1E4UL) /**< \brief (DMAC) Channel 26 Control B */
#define REG_DMAC_CHPRILVL26 (*(RwReg *)0x4100A1E5UL) /**< \brief (DMAC) Channel 26 Priority Level */
#define REG_DMAC_CHEVCTRL26 (*(RwReg *)0x4100A1E6UL) /**< \brief (DMAC) Channel 26 Event Control */
#define REG_DMAC_CHINTENCLR26 (*(RwReg *)0x4100A1ECUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET26 (*(RwReg *)0x4100A1EDUL) /**< \brief (DMAC) Channel 26 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG26 (*(RwReg *)0x4100A1EEUL) /**< \brief (DMAC) Channel 26 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS26 (*(RwReg *)0x4100A1EFUL) /**< \brief (DMAC) Channel 26 Status */
#define REG_DMAC_CHCTRLA27 (*(RwReg *)0x4100A1F0UL) /**< \brief (DMAC) Channel 27 Control A */
#define REG_DMAC_CHCTRLB27 (*(RwReg *)0x4100A1F4UL) /**< \brief (DMAC) Channel 27 Control B */
#define REG_DMAC_CHPRILVL27 (*(RwReg *)0x4100A1F5UL) /**< \brief (DMAC) Channel 27 Priority Level */
#define REG_DMAC_CHEVCTRL27 (*(RwReg *)0x4100A1F6UL) /**< \brief (DMAC) Channel 27 Event Control */
#define REG_DMAC_CHINTENCLR27 (*(RwReg *)0x4100A1FCUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET27 (*(RwReg *)0x4100A1FDUL) /**< \brief (DMAC) Channel 27 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG27 (*(RwReg *)0x4100A1FEUL) /**< \brief (DMAC) Channel 27 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS27 (*(RwReg *)0x4100A1FFUL) /**< \brief (DMAC) Channel 27 Status */
#define REG_DMAC_CHCTRLA28 (*(RwReg *)0x4100A200UL) /**< \brief (DMAC) Channel 28 Control A */
#define REG_DMAC_CHCTRLB28 (*(RwReg *)0x4100A204UL) /**< \brief (DMAC) Channel 28 Control B */
#define REG_DMAC_CHPRILVL28 (*(RwReg *)0x4100A205UL) /**< \brief (DMAC) Channel 28 Priority Level */
#define REG_DMAC_CHEVCTRL28 (*(RwReg *)0x4100A206UL) /**< \brief (DMAC) Channel 28 Event Control */
#define REG_DMAC_CHINTENCLR28 (*(RwReg *)0x4100A20CUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET28 (*(RwReg *)0x4100A20DUL) /**< \brief (DMAC) Channel 28 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG28 (*(RwReg *)0x4100A20EUL) /**< \brief (DMAC) Channel 28 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS28 (*(RwReg *)0x4100A20FUL) /**< \brief (DMAC) Channel 28 Status */
#define REG_DMAC_CHCTRLA29 (*(RwReg *)0x4100A210UL) /**< \brief (DMAC) Channel 29 Control A */
#define REG_DMAC_CHCTRLB29 (*(RwReg *)0x4100A214UL) /**< \brief (DMAC) Channel 29 Control B */
#define REG_DMAC_CHPRILVL29 (*(RwReg *)0x4100A215UL) /**< \brief (DMAC) Channel 29 Priority Level */
#define REG_DMAC_CHEVCTRL29 (*(RwReg *)0x4100A216UL) /**< \brief (DMAC) Channel 29 Event Control */
#define REG_DMAC_CHINTENCLR29 (*(RwReg *)0x4100A21CUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET29 (*(RwReg *)0x4100A21DUL) /**< \brief (DMAC) Channel 29 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG29 (*(RwReg *)0x4100A21EUL) /**< \brief (DMAC) Channel 29 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS29 (*(RwReg *)0x4100A21FUL) /**< \brief (DMAC) Channel 29 Status */
#define REG_DMAC_CHCTRLA30 (*(RwReg *)0x4100A220UL) /**< \brief (DMAC) Channel 30 Control A */
#define REG_DMAC_CHCTRLB30 (*(RwReg *)0x4100A224UL) /**< \brief (DMAC) Channel 30 Control B */
#define REG_DMAC_CHPRILVL30 (*(RwReg *)0x4100A225UL) /**< \brief (DMAC) Channel 30 Priority Level */
#define REG_DMAC_CHEVCTRL30 (*(RwReg *)0x4100A226UL) /**< \brief (DMAC) Channel 30 Event Control */
#define REG_DMAC_CHINTENCLR30 (*(RwReg *)0x4100A22CUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET30 (*(RwReg *)0x4100A22DUL) /**< \brief (DMAC) Channel 30 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG30 (*(RwReg *)0x4100A22EUL) /**< \brief (DMAC) Channel 30 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS30 (*(RwReg *)0x4100A22FUL) /**< \brief (DMAC) Channel 30 Status */
#define REG_DMAC_CHCTRLA31 (*(RwReg *)0x4100A230UL) /**< \brief (DMAC) Channel 31 Control A */
#define REG_DMAC_CHCTRLB31 (*(RwReg *)0x4100A234UL) /**< \brief (DMAC) Channel 31 Control B */
#define REG_DMAC_CHPRILVL31 (*(RwReg *)0x4100A235UL) /**< \brief (DMAC) Channel 31 Priority Level */
#define REG_DMAC_CHEVCTRL31 (*(RwReg *)0x4100A236UL) /**< \brief (DMAC) Channel 31 Event Control */
#define REG_DMAC_CHINTENCLR31 (*(RwReg *)0x4100A23CUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET31 (*(RwReg *)0x4100A23DUL) /**< \brief (DMAC) Channel 31 Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG31 (*(RwReg *)0x4100A23EUL) /**< \brief (DMAC) Channel 31 Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS31 (*(RwReg *)0x4100A23FUL) /**< \brief (DMAC) Channel 31 Status */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DMAC peripheral ========== */
#define DMAC_BURST 1 // 0: no burst support; 1: burst support
#define DMAC_CH_BITS 5 // Number of bits to select channel
#define DMAC_CH_NUM 32 // Number of channels
#define DMAC_CLK_AHB_ID 9 // AHB clock index
#define DMAC_EVIN_NUM 8 // Number of input events
#define DMAC_EVOUT_NUM 4 // Number of output events
#define DMAC_FIFO_SIZE 16 // FIFO size for burst mode.
#define DMAC_LVL_BITS 2 // Number of bits to select level priority
#define DMAC_LVL_NUM 4 // Enable priority level number
#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value
#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value
#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value
#define DMAC_TRIG_BITS 7 // Number of bits to select trigger source
#define DMAC_TRIG_NUM 85 // Number of peripheral triggers
#endif /* _SAMD51_DMAC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for DSU
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_DSU_INSTANCE_
#define _SAMD51_DSU_INSTANCE_
/* ========== Register definition for DSU peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */
#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */
#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */
#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */
#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */
#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */
#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
#define REG_DSU_CFG (0x4100201C) /**< \brief (DSU) Configuration */
#define REG_DSU_MBCTRL (0x41002040) /**< \brief (DSU) MBIST Control */
#define REG_DSU_MBCONFIG (0x41002044) /**< \brief (DSU) MBIST Configuration */
#define REG_DSU_MBWORD (0x41002048) /**< \brief (DSU) MBIST Background Word */
#define REG_DSU_MBGSTAT (0x4100204C) /**< \brief (DSU) MBIST Global Status */
#define REG_DSU_MBDFAIL (0x41002050) /**< \brief (DSU) MBIST Fail Data */
#define REG_DSU_MBDEXP (0x41002054) /**< \brief (DSU) MBIST Expected Data */
#define REG_DSU_MBAFAIL (0x41002058) /**< \brief (DSU) MBIST Fail Address */
#define REG_DSU_MBCONTEXT (0x4100205C) /**< \brief (DSU) MBIST Fail Context */
#define REG_DSU_MBENABLE0 (0x41002060) /**< \brief (DSU) MBIST Memory Enable 0 */
#define REG_DSU_MBBUSY0 (0x41002068) /**< \brief (DSU) MBIST Memory Busy 0 */
#define REG_DSU_MBSTATUS0 (0x41002070) /**< \brief (DSU) MBIST Memory Status 0 */
#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */
#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */
#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
#define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */
#define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */
#define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */
#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
#else
#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */
#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */
#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */
#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
#define REG_DSU_CFG (*(RwReg *)0x4100201CUL) /**< \brief (DSU) Configuration */
#define REG_DSU_MBCTRL (*(RwReg *)0x41002040UL) /**< \brief (DSU) MBIST Control */
#define REG_DSU_MBCONFIG (*(RwReg *)0x41002044UL) /**< \brief (DSU) MBIST Configuration */
#define REG_DSU_MBWORD (*(RwReg *)0x41002048UL) /**< \brief (DSU) MBIST Background Word */
#define REG_DSU_MBGSTAT (*(RwReg *)0x4100204CUL) /**< \brief (DSU) MBIST Global Status */
#define REG_DSU_MBDFAIL (*(RoReg *)0x41002050UL) /**< \brief (DSU) MBIST Fail Data */
#define REG_DSU_MBDEXP (*(RoReg *)0x41002054UL) /**< \brief (DSU) MBIST Expected Data */
#define REG_DSU_MBAFAIL (*(RoReg *)0x41002058UL) /**< \brief (DSU) MBIST Fail Address */
#define REG_DSU_MBCONTEXT (*(RoReg *)0x4100205CUL) /**< \brief (DSU) MBIST Fail Context */
#define REG_DSU_MBENABLE0 (*(RwReg *)0x41002060UL) /**< \brief (DSU) MBIST Memory Enable 0 */
#define REG_DSU_MBBUSY0 (*(RoReg *)0x41002068UL) /**< \brief (DSU) MBIST Memory Busy 0 */
#define REG_DSU_MBSTATUS0 (*(RwReg *)0x41002070UL) /**< \brief (DSU) MBIST Memory Status 0 */
#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */
#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */
#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
#define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */
#define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */
#define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */
#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DSU peripheral ========== */
#define DSU_CLK_AHB_ID 4
#define DSU_DMAC_ID_DCC0 2 // DMAC ID for DCC0 register
#define DSU_DMAC_ID_DCC1 3 // DMAC ID for DCC1 register
#endif /* _SAMD51_DSU_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for EIC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_EIC_INSTANCE_
#define _SAMD51_EIC_INSTANCE_
/* ========== Register definition for EIC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control A */
#define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) Non-Maskable Interrupt Control */
#define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
#define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Synchronization Busy */
#define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */
#define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */
#define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */
#define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */
#define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) External Interrupt Asynchronous Mode */
#define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
#define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
#define REG_EIC_DEBOUNCEN (0x40002830) /**< \brief (EIC) Debouncer Enable */
#define REG_EIC_DPRESCALER (0x40002834) /**< \brief (EIC) Debouncer Prescaler */
#define REG_EIC_PINSTATE (0x40002838) /**< \brief (EIC) Pin State */
#else
#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control A */
#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Synchronization Busy */
#define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */
#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */
#define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */
#define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
#define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) External Interrupt Asynchronous Mode */
#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) External Interrupt Sense Configuration 0 */
#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) External Interrupt Sense Configuration 1 */
#define REG_EIC_DEBOUNCEN (*(RwReg *)0x40002830UL) /**< \brief (EIC) Debouncer Enable */
#define REG_EIC_DPRESCALER (*(RwReg *)0x40002834UL) /**< \brief (EIC) Debouncer Prescaler */
#define REG_EIC_PINSTATE (*(RoReg *)0x40002838UL) /**< \brief (EIC) Pin State */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EIC peripheral ========== */
#define EIC_EXTINT_NUM 16 // Number of external interrupts
#define EIC_GCLK_ID 4 // Generic Clock index
#define EIC_NUMBER_OF_CONFIG_REGS 2 // Number of CONFIG registers
#define EIC_NUMBER_OF_DPRESCALER_REGS 2 // Number of DPRESCALER pin groups
#define EIC_NUMBER_OF_INTERRUPTS 16 // Number of external interrupts (obsolete)
#endif /* _SAMD51_EIC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for EVSYS
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_EVSYS_INSTANCE_
#define _SAMD51_EVSYS_INSTANCE_
/* ========== Register definition for EVSYS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EVSYS_CTRLA (0x4100E000) /**< \brief (EVSYS) Control */
#define REG_EVSYS_SWEVT (0x4100E004) /**< \brief (EVSYS) Software Event */
#define REG_EVSYS_PRICTRL (0x4100E008) /**< \brief (EVSYS) Priority Control */
#define REG_EVSYS_INTPEND (0x4100E010) /**< \brief (EVSYS) Channel Pending Interrupt */
#define REG_EVSYS_INTSTATUS (0x4100E014) /**< \brief (EVSYS) Interrupt Status */
#define REG_EVSYS_BUSYCH (0x4100E018) /**< \brief (EVSYS) Busy Channels */
#define REG_EVSYS_READYUSR (0x4100E01C) /**< \brief (EVSYS) Ready Users */
#define REG_EVSYS_CHANNEL0 (0x4100E020) /**< \brief (EVSYS) Channel 0 Control */
#define REG_EVSYS_CHINTENCLR0 (0x4100E024) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET0 (0x4100E025) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG0 (0x4100E026) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS0 (0x4100E027) /**< \brief (EVSYS) Channel 0 Status */
#define REG_EVSYS_CHANNEL1 (0x4100E028) /**< \brief (EVSYS) Channel 1 Control */
#define REG_EVSYS_CHINTENCLR1 (0x4100E02C) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET1 (0x4100E02D) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG1 (0x4100E02E) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS1 (0x4100E02F) /**< \brief (EVSYS) Channel 1 Status */
#define REG_EVSYS_CHANNEL2 (0x4100E030) /**< \brief (EVSYS) Channel 2 Control */
#define REG_EVSYS_CHINTENCLR2 (0x4100E034) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET2 (0x4100E035) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG2 (0x4100E036) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS2 (0x4100E037) /**< \brief (EVSYS) Channel 2 Status */
#define REG_EVSYS_CHANNEL3 (0x4100E038) /**< \brief (EVSYS) Channel 3 Control */
#define REG_EVSYS_CHINTENCLR3 (0x4100E03C) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET3 (0x4100E03D) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG3 (0x4100E03E) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS3 (0x4100E03F) /**< \brief (EVSYS) Channel 3 Status */
#define REG_EVSYS_CHANNEL4 (0x4100E040) /**< \brief (EVSYS) Channel 4 Control */
#define REG_EVSYS_CHINTENCLR4 (0x4100E044) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET4 (0x4100E045) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG4 (0x4100E046) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS4 (0x4100E047) /**< \brief (EVSYS) Channel 4 Status */
#define REG_EVSYS_CHANNEL5 (0x4100E048) /**< \brief (EVSYS) Channel 5 Control */
#define REG_EVSYS_CHINTENCLR5 (0x4100E04C) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET5 (0x4100E04D) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG5 (0x4100E04E) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS5 (0x4100E04F) /**< \brief (EVSYS) Channel 5 Status */
#define REG_EVSYS_CHANNEL6 (0x4100E050) /**< \brief (EVSYS) Channel 6 Control */
#define REG_EVSYS_CHINTENCLR6 (0x4100E054) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET6 (0x4100E055) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG6 (0x4100E056) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS6 (0x4100E057) /**< \brief (EVSYS) Channel 6 Status */
#define REG_EVSYS_CHANNEL7 (0x4100E058) /**< \brief (EVSYS) Channel 7 Control */
#define REG_EVSYS_CHINTENCLR7 (0x4100E05C) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET7 (0x4100E05D) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG7 (0x4100E05E) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS7 (0x4100E05F) /**< \brief (EVSYS) Channel 7 Status */
#define REG_EVSYS_CHANNEL8 (0x4100E060) /**< \brief (EVSYS) Channel 8 Control */
#define REG_EVSYS_CHINTENCLR8 (0x4100E064) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET8 (0x4100E065) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG8 (0x4100E066) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS8 (0x4100E067) /**< \brief (EVSYS) Channel 8 Status */
#define REG_EVSYS_CHANNEL9 (0x4100E068) /**< \brief (EVSYS) Channel 9 Control */
#define REG_EVSYS_CHINTENCLR9 (0x4100E06C) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET9 (0x4100E06D) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG9 (0x4100E06E) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS9 (0x4100E06F) /**< \brief (EVSYS) Channel 9 Status */
#define REG_EVSYS_CHANNEL10 (0x4100E070) /**< \brief (EVSYS) Channel 10 Control */
#define REG_EVSYS_CHINTENCLR10 (0x4100E074) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET10 (0x4100E075) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG10 (0x4100E076) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS10 (0x4100E077) /**< \brief (EVSYS) Channel 10 Status */
#define REG_EVSYS_CHANNEL11 (0x4100E078) /**< \brief (EVSYS) Channel 11 Control */
#define REG_EVSYS_CHINTENCLR11 (0x4100E07C) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET11 (0x4100E07D) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG11 (0x4100E07E) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS11 (0x4100E07F) /**< \brief (EVSYS) Channel 11 Status */
#define REG_EVSYS_CHANNEL12 (0x4100E080) /**< \brief (EVSYS) Channel 12 Control */
#define REG_EVSYS_CHINTENCLR12 (0x4100E084) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET12 (0x4100E085) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG12 (0x4100E086) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS12 (0x4100E087) /**< \brief (EVSYS) Channel 12 Status */
#define REG_EVSYS_CHANNEL13 (0x4100E088) /**< \brief (EVSYS) Channel 13 Control */
#define REG_EVSYS_CHINTENCLR13 (0x4100E08C) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET13 (0x4100E08D) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG13 (0x4100E08E) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS13 (0x4100E08F) /**< \brief (EVSYS) Channel 13 Status */
#define REG_EVSYS_CHANNEL14 (0x4100E090) /**< \brief (EVSYS) Channel 14 Control */
#define REG_EVSYS_CHINTENCLR14 (0x4100E094) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET14 (0x4100E095) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG14 (0x4100E096) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS14 (0x4100E097) /**< \brief (EVSYS) Channel 14 Status */
#define REG_EVSYS_CHANNEL15 (0x4100E098) /**< \brief (EVSYS) Channel 15 Control */
#define REG_EVSYS_CHINTENCLR15 (0x4100E09C) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET15 (0x4100E09D) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG15 (0x4100E09E) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS15 (0x4100E09F) /**< \brief (EVSYS) Channel 15 Status */
#define REG_EVSYS_CHANNEL16 (0x4100E0A0) /**< \brief (EVSYS) Channel 16 Control */
#define REG_EVSYS_CHINTENCLR16 (0x4100E0A4) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET16 (0x4100E0A5) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG16 (0x4100E0A6) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS16 (0x4100E0A7) /**< \brief (EVSYS) Channel 16 Status */
#define REG_EVSYS_CHANNEL17 (0x4100E0A8) /**< \brief (EVSYS) Channel 17 Control */
#define REG_EVSYS_CHINTENCLR17 (0x4100E0AC) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET17 (0x4100E0AD) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG17 (0x4100E0AE) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS17 (0x4100E0AF) /**< \brief (EVSYS) Channel 17 Status */
#define REG_EVSYS_CHANNEL18 (0x4100E0B0) /**< \brief (EVSYS) Channel 18 Control */
#define REG_EVSYS_CHINTENCLR18 (0x4100E0B4) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET18 (0x4100E0B5) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG18 (0x4100E0B6) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS18 (0x4100E0B7) /**< \brief (EVSYS) Channel 18 Status */
#define REG_EVSYS_CHANNEL19 (0x4100E0B8) /**< \brief (EVSYS) Channel 19 Control */
#define REG_EVSYS_CHINTENCLR19 (0x4100E0BC) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET19 (0x4100E0BD) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG19 (0x4100E0BE) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS19 (0x4100E0BF) /**< \brief (EVSYS) Channel 19 Status */
#define REG_EVSYS_CHANNEL20 (0x4100E0C0) /**< \brief (EVSYS) Channel 20 Control */
#define REG_EVSYS_CHINTENCLR20 (0x4100E0C4) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET20 (0x4100E0C5) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG20 (0x4100E0C6) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS20 (0x4100E0C7) /**< \brief (EVSYS) Channel 20 Status */
#define REG_EVSYS_CHANNEL21 (0x4100E0C8) /**< \brief (EVSYS) Channel 21 Control */
#define REG_EVSYS_CHINTENCLR21 (0x4100E0CC) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET21 (0x4100E0CD) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG21 (0x4100E0CE) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS21 (0x4100E0CF) /**< \brief (EVSYS) Channel 21 Status */
#define REG_EVSYS_CHANNEL22 (0x4100E0D0) /**< \brief (EVSYS) Channel 22 Control */
#define REG_EVSYS_CHINTENCLR22 (0x4100E0D4) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET22 (0x4100E0D5) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG22 (0x4100E0D6) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS22 (0x4100E0D7) /**< \brief (EVSYS) Channel 22 Status */
#define REG_EVSYS_CHANNEL23 (0x4100E0D8) /**< \brief (EVSYS) Channel 23 Control */
#define REG_EVSYS_CHINTENCLR23 (0x4100E0DC) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET23 (0x4100E0DD) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG23 (0x4100E0DE) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS23 (0x4100E0DF) /**< \brief (EVSYS) Channel 23 Status */
#define REG_EVSYS_CHANNEL24 (0x4100E0E0) /**< \brief (EVSYS) Channel 24 Control */
#define REG_EVSYS_CHINTENCLR24 (0x4100E0E4) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET24 (0x4100E0E5) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG24 (0x4100E0E6) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS24 (0x4100E0E7) /**< \brief (EVSYS) Channel 24 Status */
#define REG_EVSYS_CHANNEL25 (0x4100E0E8) /**< \brief (EVSYS) Channel 25 Control */
#define REG_EVSYS_CHINTENCLR25 (0x4100E0EC) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET25 (0x4100E0ED) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG25 (0x4100E0EE) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS25 (0x4100E0EF) /**< \brief (EVSYS) Channel 25 Status */
#define REG_EVSYS_CHANNEL26 (0x4100E0F0) /**< \brief (EVSYS) Channel 26 Control */
#define REG_EVSYS_CHINTENCLR26 (0x4100E0F4) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET26 (0x4100E0F5) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG26 (0x4100E0F6) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS26 (0x4100E0F7) /**< \brief (EVSYS) Channel 26 Status */
#define REG_EVSYS_CHANNEL27 (0x4100E0F8) /**< \brief (EVSYS) Channel 27 Control */
#define REG_EVSYS_CHINTENCLR27 (0x4100E0FC) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET27 (0x4100E0FD) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG27 (0x4100E0FE) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS27 (0x4100E0FF) /**< \brief (EVSYS) Channel 27 Status */
#define REG_EVSYS_CHANNEL28 (0x4100E100) /**< \brief (EVSYS) Channel 28 Control */
#define REG_EVSYS_CHINTENCLR28 (0x4100E104) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET28 (0x4100E105) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG28 (0x4100E106) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS28 (0x4100E107) /**< \brief (EVSYS) Channel 28 Status */
#define REG_EVSYS_CHANNEL29 (0x4100E108) /**< \brief (EVSYS) Channel 29 Control */
#define REG_EVSYS_CHINTENCLR29 (0x4100E10C) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET29 (0x4100E10D) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG29 (0x4100E10E) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS29 (0x4100E10F) /**< \brief (EVSYS) Channel 29 Status */
#define REG_EVSYS_CHANNEL30 (0x4100E110) /**< \brief (EVSYS) Channel 30 Control */
#define REG_EVSYS_CHINTENCLR30 (0x4100E114) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET30 (0x4100E115) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG30 (0x4100E116) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS30 (0x4100E117) /**< \brief (EVSYS) Channel 30 Status */
#define REG_EVSYS_CHANNEL31 (0x4100E118) /**< \brief (EVSYS) Channel 31 Control */
#define REG_EVSYS_CHINTENCLR31 (0x4100E11C) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET31 (0x4100E11D) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG31 (0x4100E11E) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS31 (0x4100E11F) /**< \brief (EVSYS) Channel 31 Status */
#define REG_EVSYS_USER0 (0x4100E120) /**< \brief (EVSYS) User Multiplexer 0 */
#define REG_EVSYS_USER1 (0x4100E124) /**< \brief (EVSYS) User Multiplexer 1 */
#define REG_EVSYS_USER2 (0x4100E128) /**< \brief (EVSYS) User Multiplexer 2 */
#define REG_EVSYS_USER3 (0x4100E12C) /**< \brief (EVSYS) User Multiplexer 3 */
#define REG_EVSYS_USER4 (0x4100E130) /**< \brief (EVSYS) User Multiplexer 4 */
#define REG_EVSYS_USER5 (0x4100E134) /**< \brief (EVSYS) User Multiplexer 5 */
#define REG_EVSYS_USER6 (0x4100E138) /**< \brief (EVSYS) User Multiplexer 6 */
#define REG_EVSYS_USER7 (0x4100E13C) /**< \brief (EVSYS) User Multiplexer 7 */
#define REG_EVSYS_USER8 (0x4100E140) /**< \brief (EVSYS) User Multiplexer 8 */
#define REG_EVSYS_USER9 (0x4100E144) /**< \brief (EVSYS) User Multiplexer 9 */
#define REG_EVSYS_USER10 (0x4100E148) /**< \brief (EVSYS) User Multiplexer 10 */
#define REG_EVSYS_USER11 (0x4100E14C) /**< \brief (EVSYS) User Multiplexer 11 */
#define REG_EVSYS_USER12 (0x4100E150) /**< \brief (EVSYS) User Multiplexer 12 */
#define REG_EVSYS_USER13 (0x4100E154) /**< \brief (EVSYS) User Multiplexer 13 */
#define REG_EVSYS_USER14 (0x4100E158) /**< \brief (EVSYS) User Multiplexer 14 */
#define REG_EVSYS_USER15 (0x4100E15C) /**< \brief (EVSYS) User Multiplexer 15 */
#define REG_EVSYS_USER16 (0x4100E160) /**< \brief (EVSYS) User Multiplexer 16 */
#define REG_EVSYS_USER17 (0x4100E164) /**< \brief (EVSYS) User Multiplexer 17 */
#define REG_EVSYS_USER18 (0x4100E168) /**< \brief (EVSYS) User Multiplexer 18 */
#define REG_EVSYS_USER19 (0x4100E16C) /**< \brief (EVSYS) User Multiplexer 19 */
#define REG_EVSYS_USER20 (0x4100E170) /**< \brief (EVSYS) User Multiplexer 20 */
#define REG_EVSYS_USER21 (0x4100E174) /**< \brief (EVSYS) User Multiplexer 21 */
#define REG_EVSYS_USER22 (0x4100E178) /**< \brief (EVSYS) User Multiplexer 22 */
#define REG_EVSYS_USER23 (0x4100E17C) /**< \brief (EVSYS) User Multiplexer 23 */
#define REG_EVSYS_USER24 (0x4100E180) /**< \brief (EVSYS) User Multiplexer 24 */
#define REG_EVSYS_USER25 (0x4100E184) /**< \brief (EVSYS) User Multiplexer 25 */
#define REG_EVSYS_USER26 (0x4100E188) /**< \brief (EVSYS) User Multiplexer 26 */
#define REG_EVSYS_USER27 (0x4100E18C) /**< \brief (EVSYS) User Multiplexer 27 */
#define REG_EVSYS_USER28 (0x4100E190) /**< \brief (EVSYS) User Multiplexer 28 */
#define REG_EVSYS_USER29 (0x4100E194) /**< \brief (EVSYS) User Multiplexer 29 */
#define REG_EVSYS_USER30 (0x4100E198) /**< \brief (EVSYS) User Multiplexer 30 */
#define REG_EVSYS_USER31 (0x4100E19C) /**< \brief (EVSYS) User Multiplexer 31 */
#define REG_EVSYS_USER32 (0x4100E1A0) /**< \brief (EVSYS) User Multiplexer 32 */
#define REG_EVSYS_USER33 (0x4100E1A4) /**< \brief (EVSYS) User Multiplexer 33 */
#define REG_EVSYS_USER34 (0x4100E1A8) /**< \brief (EVSYS) User Multiplexer 34 */
#define REG_EVSYS_USER35 (0x4100E1AC) /**< \brief (EVSYS) User Multiplexer 35 */
#define REG_EVSYS_USER36 (0x4100E1B0) /**< \brief (EVSYS) User Multiplexer 36 */
#define REG_EVSYS_USER37 (0x4100E1B4) /**< \brief (EVSYS) User Multiplexer 37 */
#define REG_EVSYS_USER38 (0x4100E1B8) /**< \brief (EVSYS) User Multiplexer 38 */
#define REG_EVSYS_USER39 (0x4100E1BC) /**< \brief (EVSYS) User Multiplexer 39 */
#define REG_EVSYS_USER40 (0x4100E1C0) /**< \brief (EVSYS) User Multiplexer 40 */
#define REG_EVSYS_USER41 (0x4100E1C4) /**< \brief (EVSYS) User Multiplexer 41 */
#define REG_EVSYS_USER42 (0x4100E1C8) /**< \brief (EVSYS) User Multiplexer 42 */
#define REG_EVSYS_USER43 (0x4100E1CC) /**< \brief (EVSYS) User Multiplexer 43 */
#define REG_EVSYS_USER44 (0x4100E1D0) /**< \brief (EVSYS) User Multiplexer 44 */
#define REG_EVSYS_USER45 (0x4100E1D4) /**< \brief (EVSYS) User Multiplexer 45 */
#define REG_EVSYS_USER46 (0x4100E1D8) /**< \brief (EVSYS) User Multiplexer 46 */
#define REG_EVSYS_USER47 (0x4100E1DC) /**< \brief (EVSYS) User Multiplexer 47 */
#define REG_EVSYS_USER48 (0x4100E1E0) /**< \brief (EVSYS) User Multiplexer 48 */
#define REG_EVSYS_USER49 (0x4100E1E4) /**< \brief (EVSYS) User Multiplexer 49 */
#define REG_EVSYS_USER50 (0x4100E1E8) /**< \brief (EVSYS) User Multiplexer 50 */
#define REG_EVSYS_USER51 (0x4100E1EC) /**< \brief (EVSYS) User Multiplexer 51 */
#define REG_EVSYS_USER52 (0x4100E1F0) /**< \brief (EVSYS) User Multiplexer 52 */
#define REG_EVSYS_USER53 (0x4100E1F4) /**< \brief (EVSYS) User Multiplexer 53 */
#define REG_EVSYS_USER54 (0x4100E1F8) /**< \brief (EVSYS) User Multiplexer 54 */
#define REG_EVSYS_USER55 (0x4100E1FC) /**< \brief (EVSYS) User Multiplexer 55 */
#define REG_EVSYS_USER56 (0x4100E200) /**< \brief (EVSYS) User Multiplexer 56 */
#define REG_EVSYS_USER57 (0x4100E204) /**< \brief (EVSYS) User Multiplexer 57 */
#define REG_EVSYS_USER58 (0x4100E208) /**< \brief (EVSYS) User Multiplexer 58 */
#define REG_EVSYS_USER59 (0x4100E20C) /**< \brief (EVSYS) User Multiplexer 59 */
#define REG_EVSYS_USER60 (0x4100E210) /**< \brief (EVSYS) User Multiplexer 60 */
#define REG_EVSYS_USER61 (0x4100E214) /**< \brief (EVSYS) User Multiplexer 61 */
#define REG_EVSYS_USER62 (0x4100E218) /**< \brief (EVSYS) User Multiplexer 62 */
#define REG_EVSYS_USER63 (0x4100E21C) /**< \brief (EVSYS) User Multiplexer 63 */
#define REG_EVSYS_USER64 (0x4100E220) /**< \brief (EVSYS) User Multiplexer 64 */
#define REG_EVSYS_USER65 (0x4100E224) /**< \brief (EVSYS) User Multiplexer 65 */
#define REG_EVSYS_USER66 (0x4100E228) /**< \brief (EVSYS) User Multiplexer 66 */
#else
#define REG_EVSYS_CTRLA (*(RwReg8 *)0x4100E000UL) /**< \brief (EVSYS) Control */
#define REG_EVSYS_SWEVT (*(WoReg *)0x4100E004UL) /**< \brief (EVSYS) Software Event */
#define REG_EVSYS_PRICTRL (*(RwReg8 *)0x4100E008UL) /**< \brief (EVSYS) Priority Control */
#define REG_EVSYS_INTPEND (*(RwReg16*)0x4100E010UL) /**< \brief (EVSYS) Channel Pending Interrupt */
#define REG_EVSYS_INTSTATUS (*(RoReg *)0x4100E014UL) /**< \brief (EVSYS) Interrupt Status */
#define REG_EVSYS_BUSYCH (*(RoReg *)0x4100E018UL) /**< \brief (EVSYS) Busy Channels */
#define REG_EVSYS_READYUSR (*(RoReg *)0x4100E01CUL) /**< \brief (EVSYS) Ready Users */
#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x4100E020UL) /**< \brief (EVSYS) Channel 0 Control */
#define REG_EVSYS_CHINTENCLR0 (*(RwReg *)0x4100E024UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET0 (*(RwReg *)0x4100E025UL) /**< \brief (EVSYS) Channel 0 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG0 (*(RwReg *)0x4100E026UL) /**< \brief (EVSYS) Channel 0 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS0 (*(RoReg *)0x4100E027UL) /**< \brief (EVSYS) Channel 0 Status */
#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x4100E028UL) /**< \brief (EVSYS) Channel 1 Control */
#define REG_EVSYS_CHINTENCLR1 (*(RwReg *)0x4100E02CUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET1 (*(RwReg *)0x4100E02DUL) /**< \brief (EVSYS) Channel 1 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG1 (*(RwReg *)0x4100E02EUL) /**< \brief (EVSYS) Channel 1 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS1 (*(RoReg *)0x4100E02FUL) /**< \brief (EVSYS) Channel 1 Status */
#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x4100E030UL) /**< \brief (EVSYS) Channel 2 Control */
#define REG_EVSYS_CHINTENCLR2 (*(RwReg *)0x4100E034UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET2 (*(RwReg *)0x4100E035UL) /**< \brief (EVSYS) Channel 2 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG2 (*(RwReg *)0x4100E036UL) /**< \brief (EVSYS) Channel 2 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS2 (*(RoReg *)0x4100E037UL) /**< \brief (EVSYS) Channel 2 Status */
#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4100E038UL) /**< \brief (EVSYS) Channel 3 Control */
#define REG_EVSYS_CHINTENCLR3 (*(RwReg *)0x4100E03CUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET3 (*(RwReg *)0x4100E03DUL) /**< \brief (EVSYS) Channel 3 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG3 (*(RwReg *)0x4100E03EUL) /**< \brief (EVSYS) Channel 3 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS3 (*(RoReg *)0x4100E03FUL) /**< \brief (EVSYS) Channel 3 Status */
#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x4100E040UL) /**< \brief (EVSYS) Channel 4 Control */
#define REG_EVSYS_CHINTENCLR4 (*(RwReg *)0x4100E044UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET4 (*(RwReg *)0x4100E045UL) /**< \brief (EVSYS) Channel 4 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG4 (*(RwReg *)0x4100E046UL) /**< \brief (EVSYS) Channel 4 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS4 (*(RoReg *)0x4100E047UL) /**< \brief (EVSYS) Channel 4 Status */
#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x4100E048UL) /**< \brief (EVSYS) Channel 5 Control */
#define REG_EVSYS_CHINTENCLR5 (*(RwReg *)0x4100E04CUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET5 (*(RwReg *)0x4100E04DUL) /**< \brief (EVSYS) Channel 5 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG5 (*(RwReg *)0x4100E04EUL) /**< \brief (EVSYS) Channel 5 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS5 (*(RoReg *)0x4100E04FUL) /**< \brief (EVSYS) Channel 5 Status */
#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x4100E050UL) /**< \brief (EVSYS) Channel 6 Control */
#define REG_EVSYS_CHINTENCLR6 (*(RwReg *)0x4100E054UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET6 (*(RwReg *)0x4100E055UL) /**< \brief (EVSYS) Channel 6 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG6 (*(RwReg *)0x4100E056UL) /**< \brief (EVSYS) Channel 6 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS6 (*(RoReg *)0x4100E057UL) /**< \brief (EVSYS) Channel 6 Status */
#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4100E058UL) /**< \brief (EVSYS) Channel 7 Control */
#define REG_EVSYS_CHINTENCLR7 (*(RwReg *)0x4100E05CUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET7 (*(RwReg *)0x4100E05DUL) /**< \brief (EVSYS) Channel 7 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG7 (*(RwReg *)0x4100E05EUL) /**< \brief (EVSYS) Channel 7 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS7 (*(RoReg *)0x4100E05FUL) /**< \brief (EVSYS) Channel 7 Status */
#define REG_EVSYS_CHANNEL8 (*(RwReg *)0x4100E060UL) /**< \brief (EVSYS) Channel 8 Control */
#define REG_EVSYS_CHINTENCLR8 (*(RwReg *)0x4100E064UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET8 (*(RwReg *)0x4100E065UL) /**< \brief (EVSYS) Channel 8 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG8 (*(RwReg *)0x4100E066UL) /**< \brief (EVSYS) Channel 8 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS8 (*(RoReg *)0x4100E067UL) /**< \brief (EVSYS) Channel 8 Status */
#define REG_EVSYS_CHANNEL9 (*(RwReg *)0x4100E068UL) /**< \brief (EVSYS) Channel 9 Control */
#define REG_EVSYS_CHINTENCLR9 (*(RwReg *)0x4100E06CUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET9 (*(RwReg *)0x4100E06DUL) /**< \brief (EVSYS) Channel 9 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG9 (*(RwReg *)0x4100E06EUL) /**< \brief (EVSYS) Channel 9 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS9 (*(RoReg *)0x4100E06FUL) /**< \brief (EVSYS) Channel 9 Status */
#define REG_EVSYS_CHANNEL10 (*(RwReg *)0x4100E070UL) /**< \brief (EVSYS) Channel 10 Control */
#define REG_EVSYS_CHINTENCLR10 (*(RwReg *)0x4100E074UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET10 (*(RwReg *)0x4100E075UL) /**< \brief (EVSYS) Channel 10 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG10 (*(RwReg *)0x4100E076UL) /**< \brief (EVSYS) Channel 10 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS10 (*(RoReg *)0x4100E077UL) /**< \brief (EVSYS) Channel 10 Status */
#define REG_EVSYS_CHANNEL11 (*(RwReg *)0x4100E078UL) /**< \brief (EVSYS) Channel 11 Control */
#define REG_EVSYS_CHINTENCLR11 (*(RwReg *)0x4100E07CUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET11 (*(RwReg *)0x4100E07DUL) /**< \brief (EVSYS) Channel 11 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG11 (*(RwReg *)0x4100E07EUL) /**< \brief (EVSYS) Channel 11 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS11 (*(RoReg *)0x4100E07FUL) /**< \brief (EVSYS) Channel 11 Status */
#define REG_EVSYS_CHANNEL12 (*(RwReg *)0x4100E080UL) /**< \brief (EVSYS) Channel 12 Control */
#define REG_EVSYS_CHINTENCLR12 (*(RwReg *)0x4100E084UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET12 (*(RwReg *)0x4100E085UL) /**< \brief (EVSYS) Channel 12 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG12 (*(RwReg *)0x4100E086UL) /**< \brief (EVSYS) Channel 12 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS12 (*(RoReg *)0x4100E087UL) /**< \brief (EVSYS) Channel 12 Status */
#define REG_EVSYS_CHANNEL13 (*(RwReg *)0x4100E088UL) /**< \brief (EVSYS) Channel 13 Control */
#define REG_EVSYS_CHINTENCLR13 (*(RwReg *)0x4100E08CUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET13 (*(RwReg *)0x4100E08DUL) /**< \brief (EVSYS) Channel 13 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG13 (*(RwReg *)0x4100E08EUL) /**< \brief (EVSYS) Channel 13 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS13 (*(RoReg *)0x4100E08FUL) /**< \brief (EVSYS) Channel 13 Status */
#define REG_EVSYS_CHANNEL14 (*(RwReg *)0x4100E090UL) /**< \brief (EVSYS) Channel 14 Control */
#define REG_EVSYS_CHINTENCLR14 (*(RwReg *)0x4100E094UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET14 (*(RwReg *)0x4100E095UL) /**< \brief (EVSYS) Channel 14 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG14 (*(RwReg *)0x4100E096UL) /**< \brief (EVSYS) Channel 14 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS14 (*(RoReg *)0x4100E097UL) /**< \brief (EVSYS) Channel 14 Status */
#define REG_EVSYS_CHANNEL15 (*(RwReg *)0x4100E098UL) /**< \brief (EVSYS) Channel 15 Control */
#define REG_EVSYS_CHINTENCLR15 (*(RwReg *)0x4100E09CUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET15 (*(RwReg *)0x4100E09DUL) /**< \brief (EVSYS) Channel 15 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG15 (*(RwReg *)0x4100E09EUL) /**< \brief (EVSYS) Channel 15 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS15 (*(RoReg *)0x4100E09FUL) /**< \brief (EVSYS) Channel 15 Status */
#define REG_EVSYS_CHANNEL16 (*(RwReg *)0x4100E0A0UL) /**< \brief (EVSYS) Channel 16 Control */
#define REG_EVSYS_CHINTENCLR16 (*(RwReg *)0x4100E0A4UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET16 (*(RwReg *)0x4100E0A5UL) /**< \brief (EVSYS) Channel 16 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG16 (*(RwReg *)0x4100E0A6UL) /**< \brief (EVSYS) Channel 16 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS16 (*(RoReg *)0x4100E0A7UL) /**< \brief (EVSYS) Channel 16 Status */
#define REG_EVSYS_CHANNEL17 (*(RwReg *)0x4100E0A8UL) /**< \brief (EVSYS) Channel 17 Control */
#define REG_EVSYS_CHINTENCLR17 (*(RwReg *)0x4100E0ACUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET17 (*(RwReg *)0x4100E0ADUL) /**< \brief (EVSYS) Channel 17 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG17 (*(RwReg *)0x4100E0AEUL) /**< \brief (EVSYS) Channel 17 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS17 (*(RoReg *)0x4100E0AFUL) /**< \brief (EVSYS) Channel 17 Status */
#define REG_EVSYS_CHANNEL18 (*(RwReg *)0x4100E0B0UL) /**< \brief (EVSYS) Channel 18 Control */
#define REG_EVSYS_CHINTENCLR18 (*(RwReg *)0x4100E0B4UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET18 (*(RwReg *)0x4100E0B5UL) /**< \brief (EVSYS) Channel 18 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG18 (*(RwReg *)0x4100E0B6UL) /**< \brief (EVSYS) Channel 18 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS18 (*(RoReg *)0x4100E0B7UL) /**< \brief (EVSYS) Channel 18 Status */
#define REG_EVSYS_CHANNEL19 (*(RwReg *)0x4100E0B8UL) /**< \brief (EVSYS) Channel 19 Control */
#define REG_EVSYS_CHINTENCLR19 (*(RwReg *)0x4100E0BCUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET19 (*(RwReg *)0x4100E0BDUL) /**< \brief (EVSYS) Channel 19 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG19 (*(RwReg *)0x4100E0BEUL) /**< \brief (EVSYS) Channel 19 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS19 (*(RoReg *)0x4100E0BFUL) /**< \brief (EVSYS) Channel 19 Status */
#define REG_EVSYS_CHANNEL20 (*(RwReg *)0x4100E0C0UL) /**< \brief (EVSYS) Channel 20 Control */
#define REG_EVSYS_CHINTENCLR20 (*(RwReg *)0x4100E0C4UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET20 (*(RwReg *)0x4100E0C5UL) /**< \brief (EVSYS) Channel 20 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG20 (*(RwReg *)0x4100E0C6UL) /**< \brief (EVSYS) Channel 20 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS20 (*(RoReg *)0x4100E0C7UL) /**< \brief (EVSYS) Channel 20 Status */
#define REG_EVSYS_CHANNEL21 (*(RwReg *)0x4100E0C8UL) /**< \brief (EVSYS) Channel 21 Control */
#define REG_EVSYS_CHINTENCLR21 (*(RwReg *)0x4100E0CCUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET21 (*(RwReg *)0x4100E0CDUL) /**< \brief (EVSYS) Channel 21 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG21 (*(RwReg *)0x4100E0CEUL) /**< \brief (EVSYS) Channel 21 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS21 (*(RoReg *)0x4100E0CFUL) /**< \brief (EVSYS) Channel 21 Status */
#define REG_EVSYS_CHANNEL22 (*(RwReg *)0x4100E0D0UL) /**< \brief (EVSYS) Channel 22 Control */
#define REG_EVSYS_CHINTENCLR22 (*(RwReg *)0x4100E0D4UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET22 (*(RwReg *)0x4100E0D5UL) /**< \brief (EVSYS) Channel 22 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG22 (*(RwReg *)0x4100E0D6UL) /**< \brief (EVSYS) Channel 22 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS22 (*(RoReg *)0x4100E0D7UL) /**< \brief (EVSYS) Channel 22 Status */
#define REG_EVSYS_CHANNEL23 (*(RwReg *)0x4100E0D8UL) /**< \brief (EVSYS) Channel 23 Control */
#define REG_EVSYS_CHINTENCLR23 (*(RwReg *)0x4100E0DCUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET23 (*(RwReg *)0x4100E0DDUL) /**< \brief (EVSYS) Channel 23 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG23 (*(RwReg *)0x4100E0DEUL) /**< \brief (EVSYS) Channel 23 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS23 (*(RoReg *)0x4100E0DFUL) /**< \brief (EVSYS) Channel 23 Status */
#define REG_EVSYS_CHANNEL24 (*(RwReg *)0x4100E0E0UL) /**< \brief (EVSYS) Channel 24 Control */
#define REG_EVSYS_CHINTENCLR24 (*(RwReg *)0x4100E0E4UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET24 (*(RwReg *)0x4100E0E5UL) /**< \brief (EVSYS) Channel 24 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG24 (*(RwReg *)0x4100E0E6UL) /**< \brief (EVSYS) Channel 24 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS24 (*(RoReg *)0x4100E0E7UL) /**< \brief (EVSYS) Channel 24 Status */
#define REG_EVSYS_CHANNEL25 (*(RwReg *)0x4100E0E8UL) /**< \brief (EVSYS) Channel 25 Control */
#define REG_EVSYS_CHINTENCLR25 (*(RwReg *)0x4100E0ECUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET25 (*(RwReg *)0x4100E0EDUL) /**< \brief (EVSYS) Channel 25 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG25 (*(RwReg *)0x4100E0EEUL) /**< \brief (EVSYS) Channel 25 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS25 (*(RoReg *)0x4100E0EFUL) /**< \brief (EVSYS) Channel 25 Status */
#define REG_EVSYS_CHANNEL26 (*(RwReg *)0x4100E0F0UL) /**< \brief (EVSYS) Channel 26 Control */
#define REG_EVSYS_CHINTENCLR26 (*(RwReg *)0x4100E0F4UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET26 (*(RwReg *)0x4100E0F5UL) /**< \brief (EVSYS) Channel 26 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG26 (*(RwReg *)0x4100E0F6UL) /**< \brief (EVSYS) Channel 26 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS26 (*(RoReg *)0x4100E0F7UL) /**< \brief (EVSYS) Channel 26 Status */
#define REG_EVSYS_CHANNEL27 (*(RwReg *)0x4100E0F8UL) /**< \brief (EVSYS) Channel 27 Control */
#define REG_EVSYS_CHINTENCLR27 (*(RwReg *)0x4100E0FCUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET27 (*(RwReg *)0x4100E0FDUL) /**< \brief (EVSYS) Channel 27 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG27 (*(RwReg *)0x4100E0FEUL) /**< \brief (EVSYS) Channel 27 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS27 (*(RoReg *)0x4100E0FFUL) /**< \brief (EVSYS) Channel 27 Status */
#define REG_EVSYS_CHANNEL28 (*(RwReg *)0x4100E100UL) /**< \brief (EVSYS) Channel 28 Control */
#define REG_EVSYS_CHINTENCLR28 (*(RwReg *)0x4100E104UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET28 (*(RwReg *)0x4100E105UL) /**< \brief (EVSYS) Channel 28 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG28 (*(RwReg *)0x4100E106UL) /**< \brief (EVSYS) Channel 28 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS28 (*(RoReg *)0x4100E107UL) /**< \brief (EVSYS) Channel 28 Status */
#define REG_EVSYS_CHANNEL29 (*(RwReg *)0x4100E108UL) /**< \brief (EVSYS) Channel 29 Control */
#define REG_EVSYS_CHINTENCLR29 (*(RwReg *)0x4100E10CUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET29 (*(RwReg *)0x4100E10DUL) /**< \brief (EVSYS) Channel 29 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG29 (*(RwReg *)0x4100E10EUL) /**< \brief (EVSYS) Channel 29 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS29 (*(RoReg *)0x4100E10FUL) /**< \brief (EVSYS) Channel 29 Status */
#define REG_EVSYS_CHANNEL30 (*(RwReg *)0x4100E110UL) /**< \brief (EVSYS) Channel 30 Control */
#define REG_EVSYS_CHINTENCLR30 (*(RwReg *)0x4100E114UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET30 (*(RwReg *)0x4100E115UL) /**< \brief (EVSYS) Channel 30 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG30 (*(RwReg *)0x4100E116UL) /**< \brief (EVSYS) Channel 30 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS30 (*(RoReg *)0x4100E117UL) /**< \brief (EVSYS) Channel 30 Status */
#define REG_EVSYS_CHANNEL31 (*(RwReg *)0x4100E118UL) /**< \brief (EVSYS) Channel 31 Control */
#define REG_EVSYS_CHINTENCLR31 (*(RwReg *)0x4100E11CUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Clear */
#define REG_EVSYS_CHINTENSET31 (*(RwReg *)0x4100E11DUL) /**< \brief (EVSYS) Channel 31 Interrupt Enable Set */
#define REG_EVSYS_CHINTFLAG31 (*(RwReg *)0x4100E11EUL) /**< \brief (EVSYS) Channel 31 Interrupt Flag Status and Clear */
#define REG_EVSYS_CHSTATUS31 (*(RoReg *)0x4100E11FUL) /**< \brief (EVSYS) Channel 31 Status */
#define REG_EVSYS_USER0 (*(RwReg *)0x4100E120UL) /**< \brief (EVSYS) User Multiplexer 0 */
#define REG_EVSYS_USER1 (*(RwReg *)0x4100E124UL) /**< \brief (EVSYS) User Multiplexer 1 */
#define REG_EVSYS_USER2 (*(RwReg *)0x4100E128UL) /**< \brief (EVSYS) User Multiplexer 2 */
#define REG_EVSYS_USER3 (*(RwReg *)0x4100E12CUL) /**< \brief (EVSYS) User Multiplexer 3 */
#define REG_EVSYS_USER4 (*(RwReg *)0x4100E130UL) /**< \brief (EVSYS) User Multiplexer 4 */
#define REG_EVSYS_USER5 (*(RwReg *)0x4100E134UL) /**< \brief (EVSYS) User Multiplexer 5 */
#define REG_EVSYS_USER6 (*(RwReg *)0x4100E138UL) /**< \brief (EVSYS) User Multiplexer 6 */
#define REG_EVSYS_USER7 (*(RwReg *)0x4100E13CUL) /**< \brief (EVSYS) User Multiplexer 7 */
#define REG_EVSYS_USER8 (*(RwReg *)0x4100E140UL) /**< \brief (EVSYS) User Multiplexer 8 */
#define REG_EVSYS_USER9 (*(RwReg *)0x4100E144UL) /**< \brief (EVSYS) User Multiplexer 9 */
#define REG_EVSYS_USER10 (*(RwReg *)0x4100E148UL) /**< \brief (EVSYS) User Multiplexer 10 */
#define REG_EVSYS_USER11 (*(RwReg *)0x4100E14CUL) /**< \brief (EVSYS) User Multiplexer 11 */
#define REG_EVSYS_USER12 (*(RwReg *)0x4100E150UL) /**< \brief (EVSYS) User Multiplexer 12 */
#define REG_EVSYS_USER13 (*(RwReg *)0x4100E154UL) /**< \brief (EVSYS) User Multiplexer 13 */
#define REG_EVSYS_USER14 (*(RwReg *)0x4100E158UL) /**< \brief (EVSYS) User Multiplexer 14 */
#define REG_EVSYS_USER15 (*(RwReg *)0x4100E15CUL) /**< \brief (EVSYS) User Multiplexer 15 */
#define REG_EVSYS_USER16 (*(RwReg *)0x4100E160UL) /**< \brief (EVSYS) User Multiplexer 16 */
#define REG_EVSYS_USER17 (*(RwReg *)0x4100E164UL) /**< \brief (EVSYS) User Multiplexer 17 */
#define REG_EVSYS_USER18 (*(RwReg *)0x4100E168UL) /**< \brief (EVSYS) User Multiplexer 18 */
#define REG_EVSYS_USER19 (*(RwReg *)0x4100E16CUL) /**< \brief (EVSYS) User Multiplexer 19 */
#define REG_EVSYS_USER20 (*(RwReg *)0x4100E170UL) /**< \brief (EVSYS) User Multiplexer 20 */
#define REG_EVSYS_USER21 (*(RwReg *)0x4100E174UL) /**< \brief (EVSYS) User Multiplexer 21 */
#define REG_EVSYS_USER22 (*(RwReg *)0x4100E178UL) /**< \brief (EVSYS) User Multiplexer 22 */
#define REG_EVSYS_USER23 (*(RwReg *)0x4100E17CUL) /**< \brief (EVSYS) User Multiplexer 23 */
#define REG_EVSYS_USER24 (*(RwReg *)0x4100E180UL) /**< \brief (EVSYS) User Multiplexer 24 */
#define REG_EVSYS_USER25 (*(RwReg *)0x4100E184UL) /**< \brief (EVSYS) User Multiplexer 25 */
#define REG_EVSYS_USER26 (*(RwReg *)0x4100E188UL) /**< \brief (EVSYS) User Multiplexer 26 */
#define REG_EVSYS_USER27 (*(RwReg *)0x4100E18CUL) /**< \brief (EVSYS) User Multiplexer 27 */
#define REG_EVSYS_USER28 (*(RwReg *)0x4100E190UL) /**< \brief (EVSYS) User Multiplexer 28 */
#define REG_EVSYS_USER29 (*(RwReg *)0x4100E194UL) /**< \brief (EVSYS) User Multiplexer 29 */
#define REG_EVSYS_USER30 (*(RwReg *)0x4100E198UL) /**< \brief (EVSYS) User Multiplexer 30 */
#define REG_EVSYS_USER31 (*(RwReg *)0x4100E19CUL) /**< \brief (EVSYS) User Multiplexer 31 */
#define REG_EVSYS_USER32 (*(RwReg *)0x4100E1A0UL) /**< \brief (EVSYS) User Multiplexer 32 */
#define REG_EVSYS_USER33 (*(RwReg *)0x4100E1A4UL) /**< \brief (EVSYS) User Multiplexer 33 */
#define REG_EVSYS_USER34 (*(RwReg *)0x4100E1A8UL) /**< \brief (EVSYS) User Multiplexer 34 */
#define REG_EVSYS_USER35 (*(RwReg *)0x4100E1ACUL) /**< \brief (EVSYS) User Multiplexer 35 */
#define REG_EVSYS_USER36 (*(RwReg *)0x4100E1B0UL) /**< \brief (EVSYS) User Multiplexer 36 */
#define REG_EVSYS_USER37 (*(RwReg *)0x4100E1B4UL) /**< \brief (EVSYS) User Multiplexer 37 */
#define REG_EVSYS_USER38 (*(RwReg *)0x4100E1B8UL) /**< \brief (EVSYS) User Multiplexer 38 */
#define REG_EVSYS_USER39 (*(RwReg *)0x4100E1BCUL) /**< \brief (EVSYS) User Multiplexer 39 */
#define REG_EVSYS_USER40 (*(RwReg *)0x4100E1C0UL) /**< \brief (EVSYS) User Multiplexer 40 */
#define REG_EVSYS_USER41 (*(RwReg *)0x4100E1C4UL) /**< \brief (EVSYS) User Multiplexer 41 */
#define REG_EVSYS_USER42 (*(RwReg *)0x4100E1C8UL) /**< \brief (EVSYS) User Multiplexer 42 */
#define REG_EVSYS_USER43 (*(RwReg *)0x4100E1CCUL) /**< \brief (EVSYS) User Multiplexer 43 */
#define REG_EVSYS_USER44 (*(RwReg *)0x4100E1D0UL) /**< \brief (EVSYS) User Multiplexer 44 */
#define REG_EVSYS_USER45 (*(RwReg *)0x4100E1D4UL) /**< \brief (EVSYS) User Multiplexer 45 */
#define REG_EVSYS_USER46 (*(RwReg *)0x4100E1D8UL) /**< \brief (EVSYS) User Multiplexer 46 */
#define REG_EVSYS_USER47 (*(RwReg *)0x4100E1DCUL) /**< \brief (EVSYS) User Multiplexer 47 */
#define REG_EVSYS_USER48 (*(RwReg *)0x4100E1E0UL) /**< \brief (EVSYS) User Multiplexer 48 */
#define REG_EVSYS_USER49 (*(RwReg *)0x4100E1E4UL) /**< \brief (EVSYS) User Multiplexer 49 */
#define REG_EVSYS_USER50 (*(RwReg *)0x4100E1E8UL) /**< \brief (EVSYS) User Multiplexer 50 */
#define REG_EVSYS_USER51 (*(RwReg *)0x4100E1ECUL) /**< \brief (EVSYS) User Multiplexer 51 */
#define REG_EVSYS_USER52 (*(RwReg *)0x4100E1F0UL) /**< \brief (EVSYS) User Multiplexer 52 */
#define REG_EVSYS_USER53 (*(RwReg *)0x4100E1F4UL) /**< \brief (EVSYS) User Multiplexer 53 */
#define REG_EVSYS_USER54 (*(RwReg *)0x4100E1F8UL) /**< \brief (EVSYS) User Multiplexer 54 */
#define REG_EVSYS_USER55 (*(RwReg *)0x4100E1FCUL) /**< \brief (EVSYS) User Multiplexer 55 */
#define REG_EVSYS_USER56 (*(RwReg *)0x4100E200UL) /**< \brief (EVSYS) User Multiplexer 56 */
#define REG_EVSYS_USER57 (*(RwReg *)0x4100E204UL) /**< \brief (EVSYS) User Multiplexer 57 */
#define REG_EVSYS_USER58 (*(RwReg *)0x4100E208UL) /**< \brief (EVSYS) User Multiplexer 58 */
#define REG_EVSYS_USER59 (*(RwReg *)0x4100E20CUL) /**< \brief (EVSYS) User Multiplexer 59 */
#define REG_EVSYS_USER60 (*(RwReg *)0x4100E210UL) /**< \brief (EVSYS) User Multiplexer 60 */
#define REG_EVSYS_USER61 (*(RwReg *)0x4100E214UL) /**< \brief (EVSYS) User Multiplexer 61 */
#define REG_EVSYS_USER62 (*(RwReg *)0x4100E218UL) /**< \brief (EVSYS) User Multiplexer 62 */
#define REG_EVSYS_USER63 (*(RwReg *)0x4100E21CUL) /**< \brief (EVSYS) User Multiplexer 63 */
#define REG_EVSYS_USER64 (*(RwReg *)0x4100E220UL) /**< \brief (EVSYS) User Multiplexer 64 */
#define REG_EVSYS_USER65 (*(RwReg *)0x4100E224UL) /**< \brief (EVSYS) User Multiplexer 65 */
#define REG_EVSYS_USER66 (*(RwReg *)0x4100E228UL) /**< \brief (EVSYS) User Multiplexer 66 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EVSYS peripheral ========== */
#define EVSYS_ASYNCHRONOUS_CHANNELS 0xFFFFF000 // Mask of Only Asynchronous Channels
#define EVSYS_CHANNELS 32 // Total Number of Channels
#define EVSYS_CHANNELS_BITS 5 // Number of bits to select Channel
#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
#define EVSYS_GCLK_ID_0 11
#define EVSYS_GCLK_ID_1 12
#define EVSYS_GCLK_ID_2 13
#define EVSYS_GCLK_ID_3 14
#define EVSYS_GCLK_ID_4 15
#define EVSYS_GCLK_ID_5 16
#define EVSYS_GCLK_ID_6 17
#define EVSYS_GCLK_ID_7 18
#define EVSYS_GCLK_ID_8 19
#define EVSYS_GCLK_ID_9 20
#define EVSYS_GCLK_ID_10 21
#define EVSYS_GCLK_ID_11 22
#define EVSYS_GCLK_ID_LSB 11
#define EVSYS_GCLK_ID_MSB 22
#define EVSYS_GCLK_ID_SIZE 12
#define EVSYS_GENERATORS 119 // Total Number of Event Generators
#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
#define EVSYS_SYNCH_NUM 12 // Number of Synchronous Channels
#define EVSYS_SYNCH_NUM_BITS 4 // Number of bits to select Synchronous Channels
#define EVSYS_USERS 67 // Total Number of Event Users
#define EVSYS_USERS_BITS 7 // Number of bits to select Event User
// GENERATORS
#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_0 1
#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_1 2
#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3
#define EVSYS_ID_GEN_RTC_PER_0 4
#define EVSYS_ID_GEN_RTC_PER_1 5
#define EVSYS_ID_GEN_RTC_PER_2 6
#define EVSYS_ID_GEN_RTC_PER_3 7
#define EVSYS_ID_GEN_RTC_PER_4 8
#define EVSYS_ID_GEN_RTC_PER_5 9
#define EVSYS_ID_GEN_RTC_PER_6 10
#define EVSYS_ID_GEN_RTC_PER_7 11
#define EVSYS_ID_GEN_RTC_CMP_0 12
#define EVSYS_ID_GEN_RTC_CMP_1 13
#define EVSYS_ID_GEN_RTC_CMP_2 14
#define EVSYS_ID_GEN_RTC_CMP_3 15
#define EVSYS_ID_GEN_RTC_TAMPER 16
#define EVSYS_ID_GEN_RTC_OVF 17
#define EVSYS_ID_GEN_EIC_EXTINT_0 18
#define EVSYS_ID_GEN_EIC_EXTINT_1 19
#define EVSYS_ID_GEN_EIC_EXTINT_2 20
#define EVSYS_ID_GEN_EIC_EXTINT_3 21
#define EVSYS_ID_GEN_EIC_EXTINT_4 22
#define EVSYS_ID_GEN_EIC_EXTINT_5 23
#define EVSYS_ID_GEN_EIC_EXTINT_6 24
#define EVSYS_ID_GEN_EIC_EXTINT_7 25
#define EVSYS_ID_GEN_EIC_EXTINT_8 26
#define EVSYS_ID_GEN_EIC_EXTINT_9 27
#define EVSYS_ID_GEN_EIC_EXTINT_10 28
#define EVSYS_ID_GEN_EIC_EXTINT_11 29
#define EVSYS_ID_GEN_EIC_EXTINT_12 30
#define EVSYS_ID_GEN_EIC_EXTINT_13 31
#define EVSYS_ID_GEN_EIC_EXTINT_14 32
#define EVSYS_ID_GEN_EIC_EXTINT_15 33
#define EVSYS_ID_GEN_DMAC_CH_0 34
#define EVSYS_ID_GEN_DMAC_CH_1 35
#define EVSYS_ID_GEN_DMAC_CH_2 36
#define EVSYS_ID_GEN_DMAC_CH_3 37
#define EVSYS_ID_GEN_PAC_ACCERR 38
#define EVSYS_ID_GEN_TAL_BRK 39
#define EVSYS_ID_GEN_TAL_IRQMON_0 40
#define EVSYS_ID_GEN_TCC0_OVF 41
#define EVSYS_ID_GEN_TCC0_TRG 42
#define EVSYS_ID_GEN_TCC0_CNT 43
#define EVSYS_ID_GEN_TCC0_MCX_0 44
#define EVSYS_ID_GEN_TCC0_MCX_1 45
#define EVSYS_ID_GEN_TCC0_MCX_2 46
#define EVSYS_ID_GEN_TCC0_MCX_3 47
#define EVSYS_ID_GEN_TCC0_MCX_4 48
#define EVSYS_ID_GEN_TCC0_MCX_5 49
#define EVSYS_ID_GEN_TCC1_OVF 50
#define EVSYS_ID_GEN_TCC1_TRG 51
#define EVSYS_ID_GEN_TCC1_CNT 52
#define EVSYS_ID_GEN_TCC1_MCX_0 53
#define EVSYS_ID_GEN_TCC1_MCX_1 54
#define EVSYS_ID_GEN_TCC1_MCX_2 55
#define EVSYS_ID_GEN_TCC1_MCX_3 56
#define EVSYS_ID_GEN_TCC2_OVF 57
#define EVSYS_ID_GEN_TCC2_TRG 58
#define EVSYS_ID_GEN_TCC2_CNT 59
#define EVSYS_ID_GEN_TCC2_MCX_0 60
#define EVSYS_ID_GEN_TCC2_MCX_1 61
#define EVSYS_ID_GEN_TCC2_MCX_2 62
#define EVSYS_ID_GEN_TCC3_OVF 63
#define EVSYS_ID_GEN_TCC3_TRG 64
#define EVSYS_ID_GEN_TCC3_CNT 65
#define EVSYS_ID_GEN_TCC3_MCX_0 66
#define EVSYS_ID_GEN_TCC3_MCX_1 67
#define EVSYS_ID_GEN_TCC4_OVF 68
#define EVSYS_ID_GEN_TCC4_TRG 69
#define EVSYS_ID_GEN_TCC4_CNT 70
#define EVSYS_ID_GEN_TCC4_MCX_0 71
#define EVSYS_ID_GEN_TCC4_MCX_1 72
#define EVSYS_ID_GEN_TC0_OVF 73
#define EVSYS_ID_GEN_TC0_MCX_0 74
#define EVSYS_ID_GEN_TC0_MCX_1 75
#define EVSYS_ID_GEN_TC1_OVF 76
#define EVSYS_ID_GEN_TC1_MCX_0 77
#define EVSYS_ID_GEN_TC1_MCX_1 78
#define EVSYS_ID_GEN_TC2_OVF 79
#define EVSYS_ID_GEN_TC2_MCX_0 80
#define EVSYS_ID_GEN_TC2_MCX_1 81
#define EVSYS_ID_GEN_TC3_OVF 82
#define EVSYS_ID_GEN_TC3_MCX_0 83
#define EVSYS_ID_GEN_TC3_MCX_1 84
#define EVSYS_ID_GEN_TC4_OVF 85
#define EVSYS_ID_GEN_TC4_MCX_0 86
#define EVSYS_ID_GEN_TC4_MCX_1 87
#define EVSYS_ID_GEN_TC5_OVF 88
#define EVSYS_ID_GEN_TC5_MCX_0 89
#define EVSYS_ID_GEN_TC5_MCX_1 90
#define EVSYS_ID_GEN_TC6_OVF 91
#define EVSYS_ID_GEN_TC6_MCX_0 92
#define EVSYS_ID_GEN_TC6_MCX_1 93
#define EVSYS_ID_GEN_TC7_OVF 94
#define EVSYS_ID_GEN_TC7_MCX_0 95
#define EVSYS_ID_GEN_TC7_MCX_1 96
#define EVSYS_ID_GEN_PDEC_OVF 97
#define EVSYS_ID_GEN_PDEC_ERR 98
#define EVSYS_ID_GEN_PDEC_DIR 99
#define EVSYS_ID_GEN_PDEC_VLC 100
#define EVSYS_ID_GEN_PDEC_MCX_0 101
#define EVSYS_ID_GEN_PDEC_MCX_1 102
#define EVSYS_ID_GEN_ADC0_RESRDY 103
#define EVSYS_ID_GEN_ADC0_WINMON 104
#define EVSYS_ID_GEN_ADC1_RESRDY 105
#define EVSYS_ID_GEN_ADC1_WINMON 106
#define EVSYS_ID_GEN_AC_COMP_0 107
#define EVSYS_ID_GEN_AC_COMP_1 108
#define EVSYS_ID_GEN_AC_WIN_0 109
#define EVSYS_ID_GEN_DAC_EMPTY_0 110
#define EVSYS_ID_GEN_DAC_EMPTY_1 111
#define EVSYS_ID_GEN_DAC_RESRDY_0 112
#define EVSYS_ID_GEN_DAC_RESRDY_1 113
#define EVSYS_ID_GEN_TRNG_READY 115
#define EVSYS_ID_GEN_CCL_LUTOUT_0 116
#define EVSYS_ID_GEN_CCL_LUTOUT_1 117
#define EVSYS_ID_GEN_CCL_LUTOUT_2 118
#define EVSYS_ID_GEN_CCL_LUTOUT_3 119
// USERS
#define EVSYS_ID_USER_RTC_TAMPER 0
#define EVSYS_ID_USER_PORT_EV_0 1
#define EVSYS_ID_USER_PORT_EV_1 2
#define EVSYS_ID_USER_PORT_EV_2 3
#define EVSYS_ID_USER_PORT_EV_3 4
#define EVSYS_ID_USER_DMAC_CH_0 5
#define EVSYS_ID_USER_DMAC_CH_1 6
#define EVSYS_ID_USER_DMAC_CH_2 7
#define EVSYS_ID_USER_DMAC_CH_3 8
#define EVSYS_ID_USER_DMAC_CH_4 9
#define EVSYS_ID_USER_DMAC_CH_5 10
#define EVSYS_ID_USER_DMAC_CH_6 11
#define EVSYS_ID_USER_DMAC_CH_7 12
#define EVSYS_ID_USER_TAL_BRK 13
#define EVSYS_ID_USER_CM4_TRACE_START 14
#define EVSYS_ID_USER_CM4_TRACE_STOP 15
#define EVSYS_ID_USER_CM4_TRACE_TRIG 16
#define EVSYS_ID_USER_TCC0_EV_0 17
#define EVSYS_ID_USER_TCC0_EV_1 18
#define EVSYS_ID_USER_TCC0_MC_0 19
#define EVSYS_ID_USER_TCC0_MC_1 20
#define EVSYS_ID_USER_TCC0_MC_2 21
#define EVSYS_ID_USER_TCC0_MC_3 22
#define EVSYS_ID_USER_TCC0_MC_4 23
#define EVSYS_ID_USER_TCC0_MC_5 24
#define EVSYS_ID_USER_TCC1_EV_0 25
#define EVSYS_ID_USER_TCC1_EV_1 26
#define EVSYS_ID_USER_TCC1_MC_0 27
#define EVSYS_ID_USER_TCC1_MC_1 28
#define EVSYS_ID_USER_TCC1_MC_2 29
#define EVSYS_ID_USER_TCC1_MC_3 30
#define EVSYS_ID_USER_TCC2_EV_0 31
#define EVSYS_ID_USER_TCC2_EV_1 32
#define EVSYS_ID_USER_TCC2_MC_0 33
#define EVSYS_ID_USER_TCC2_MC_1 34
#define EVSYS_ID_USER_TCC2_MC_2 35
#define EVSYS_ID_USER_TCC3_EV_0 36
#define EVSYS_ID_USER_TCC3_EV_1 37
#define EVSYS_ID_USER_TCC3_MC_0 38
#define EVSYS_ID_USER_TCC3_MC_1 39
#define EVSYS_ID_USER_TCC4_EV_0 40
#define EVSYS_ID_USER_TCC4_EV_1 41
#define EVSYS_ID_USER_TCC4_MC_0 42
#define EVSYS_ID_USER_TCC4_MC_1 43
#define EVSYS_ID_USER_TC0_EVU 44
#define EVSYS_ID_USER_TC1_EVU 45
#define EVSYS_ID_USER_TC2_EVU 46
#define EVSYS_ID_USER_TC3_EVU 47
#define EVSYS_ID_USER_TC4_EVU 48
#define EVSYS_ID_USER_TC5_EVU 49
#define EVSYS_ID_USER_TC6_EVU 50
#define EVSYS_ID_USER_TC7_EVU 51
#define EVSYS_ID_USER_PDEC_EVU_0 52
#define EVSYS_ID_USER_PDEC_EVU_1 53
#define EVSYS_ID_USER_PDEC_EVU_2 54
#define EVSYS_ID_USER_ADC0_START 55
#define EVSYS_ID_USER_ADC0_SYNC 56
#define EVSYS_ID_USER_ADC1_START 57
#define EVSYS_ID_USER_ADC1_SYNC 58
#define EVSYS_ID_USER_AC_SOC_0 59
#define EVSYS_ID_USER_AC_SOC_1 60
#define EVSYS_ID_USER_DAC_START_0 61
#define EVSYS_ID_USER_DAC_START_1 62
#define EVSYS_ID_USER_CCL_LUTIN_0 63
#define EVSYS_ID_USER_CCL_LUTIN_1 64
#define EVSYS_ID_USER_CCL_LUTIN_2 65
#define EVSYS_ID_USER_CCL_LUTIN_3 66
#endif /* _SAMD51_EVSYS_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for FREQM
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_FREQM_INSTANCE_
#define _SAMD51_FREQM_INSTANCE_
/* ========== Register definition for FREQM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_FREQM_CTRLA (0x40002C00) /**< \brief (FREQM) Control A Register */
#define REG_FREQM_CTRLB (0x40002C01) /**< \brief (FREQM) Control B Register */
#define REG_FREQM_CFGA (0x40002C02) /**< \brief (FREQM) Config A register */
#define REG_FREQM_INTENCLR (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */
#define REG_FREQM_INTENSET (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */
#define REG_FREQM_INTFLAG (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */
#define REG_FREQM_STATUS (0x40002C0B) /**< \brief (FREQM) Status Register */
#define REG_FREQM_SYNCBUSY (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */
#define REG_FREQM_VALUE (0x40002C10) /**< \brief (FREQM) Count Value Register */
#else
#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */
#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */
#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */
#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */
#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */
#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */
#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */
#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */
#define REG_FREQM_VALUE (*(RoReg *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for FREQM peripheral ========== */
#define FREQM_GCLK_ID_MSR 5 // Index of measure generic clock
#endif /* _SAMD51_FREQM_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for GCLK
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_GCLK_INSTANCE_
#define _SAMD51_GCLK_INSTANCE_
/* ========== Register definition for GCLK peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_GCLK_CTRLA (0x40001C00) /**< \brief (GCLK) Control */
#define REG_GCLK_SYNCBUSY (0x40001C04) /**< \brief (GCLK) Synchronization Busy */
#define REG_GCLK_GENCTRL0 (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */
#define REG_GCLK_GENCTRL1 (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */
#define REG_GCLK_GENCTRL2 (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */
#define REG_GCLK_GENCTRL3 (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */
#define REG_GCLK_GENCTRL4 (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */
#define REG_GCLK_GENCTRL5 (0x40001C34) /**< \brief (GCLK) Generic Clock Generator Control 5 */
#define REG_GCLK_GENCTRL6 (0x40001C38) /**< \brief (GCLK) Generic Clock Generator Control 6 */
#define REG_GCLK_GENCTRL7 (0x40001C3C) /**< \brief (GCLK) Generic Clock Generator Control 7 */
#define REG_GCLK_GENCTRL8 (0x40001C40) /**< \brief (GCLK) Generic Clock Generator Control 8 */
#define REG_GCLK_GENCTRL9 (0x40001C44) /**< \brief (GCLK) Generic Clock Generator Control 9 */
#define REG_GCLK_GENCTRL10 (0x40001C48) /**< \brief (GCLK) Generic Clock Generator Control 10 */
#define REG_GCLK_GENCTRL11 (0x40001C4C) /**< \brief (GCLK) Generic Clock Generator Control 11 */
#define REG_GCLK_PCHCTRL0 (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */
#define REG_GCLK_PCHCTRL1 (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */
#define REG_GCLK_PCHCTRL2 (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */
#define REG_GCLK_PCHCTRL3 (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */
#define REG_GCLK_PCHCTRL4 (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */
#define REG_GCLK_PCHCTRL5 (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */
#define REG_GCLK_PCHCTRL6 (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */
#define REG_GCLK_PCHCTRL7 (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */
#define REG_GCLK_PCHCTRL8 (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */
#define REG_GCLK_PCHCTRL9 (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */
#define REG_GCLK_PCHCTRL10 (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */
#define REG_GCLK_PCHCTRL11 (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */
#define REG_GCLK_PCHCTRL12 (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */
#define REG_GCLK_PCHCTRL13 (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */
#define REG_GCLK_PCHCTRL14 (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */
#define REG_GCLK_PCHCTRL15 (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */
#define REG_GCLK_PCHCTRL16 (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */
#define REG_GCLK_PCHCTRL17 (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */
#define REG_GCLK_PCHCTRL18 (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */
#define REG_GCLK_PCHCTRL19 (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */
#define REG_GCLK_PCHCTRL20 (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */
#define REG_GCLK_PCHCTRL21 (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */
#define REG_GCLK_PCHCTRL22 (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */
#define REG_GCLK_PCHCTRL23 (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */
#define REG_GCLK_PCHCTRL24 (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */
#define REG_GCLK_PCHCTRL25 (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */
#define REG_GCLK_PCHCTRL26 (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */
#define REG_GCLK_PCHCTRL27 (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */
#define REG_GCLK_PCHCTRL28 (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */
#define REG_GCLK_PCHCTRL29 (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */
#define REG_GCLK_PCHCTRL30 (0x40001CF8) /**< \brief (GCLK) Peripheral Clock Control 30 */
#define REG_GCLK_PCHCTRL31 (0x40001CFC) /**< \brief (GCLK) Peripheral Clock Control 31 */
#define REG_GCLK_PCHCTRL32 (0x40001D00) /**< \brief (GCLK) Peripheral Clock Control 32 */
#define REG_GCLK_PCHCTRL33 (0x40001D04) /**< \brief (GCLK) Peripheral Clock Control 33 */
#define REG_GCLK_PCHCTRL34 (0x40001D08) /**< \brief (GCLK) Peripheral Clock Control 34 */
#define REG_GCLK_PCHCTRL35 (0x40001D0C) /**< \brief (GCLK) Peripheral Clock Control 35 */
#define REG_GCLK_PCHCTRL36 (0x40001D10) /**< \brief (GCLK) Peripheral Clock Control 36 */
#define REG_GCLK_PCHCTRL37 (0x40001D14) /**< \brief (GCLK) Peripheral Clock Control 37 */
#define REG_GCLK_PCHCTRL38 (0x40001D18) /**< \brief (GCLK) Peripheral Clock Control 38 */
#define REG_GCLK_PCHCTRL39 (0x40001D1C) /**< \brief (GCLK) Peripheral Clock Control 39 */
#define REG_GCLK_PCHCTRL40 (0x40001D20) /**< \brief (GCLK) Peripheral Clock Control 40 */
#define REG_GCLK_PCHCTRL41 (0x40001D24) /**< \brief (GCLK) Peripheral Clock Control 41 */
#define REG_GCLK_PCHCTRL42 (0x40001D28) /**< \brief (GCLK) Peripheral Clock Control 42 */
#define REG_GCLK_PCHCTRL43 (0x40001D2C) /**< \brief (GCLK) Peripheral Clock Control 43 */
#define REG_GCLK_PCHCTRL44 (0x40001D30) /**< \brief (GCLK) Peripheral Clock Control 44 */
#define REG_GCLK_PCHCTRL45 (0x40001D34) /**< \brief (GCLK) Peripheral Clock Control 45 */
#define REG_GCLK_PCHCTRL46 (0x40001D38) /**< \brief (GCLK) Peripheral Clock Control 46 */
#define REG_GCLK_PCHCTRL47 (0x40001D3C) /**< \brief (GCLK) Peripheral Clock Control 47 */
#else
#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */
#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */
#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */
#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */
#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */
#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */
#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */
#define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001C34UL) /**< \brief (GCLK) Generic Clock Generator Control 5 */
#define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001C38UL) /**< \brief (GCLK) Generic Clock Generator Control 6 */
#define REG_GCLK_GENCTRL7 (*(RwReg *)0x40001C3CUL) /**< \brief (GCLK) Generic Clock Generator Control 7 */
#define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001C40UL) /**< \brief (GCLK) Generic Clock Generator Control 8 */
#define REG_GCLK_GENCTRL9 (*(RwReg *)0x40001C44UL) /**< \brief (GCLK) Generic Clock Generator Control 9 */
#define REG_GCLK_GENCTRL10 (*(RwReg *)0x40001C48UL) /**< \brief (GCLK) Generic Clock Generator Control 10 */
#define REG_GCLK_GENCTRL11 (*(RwReg *)0x40001C4CUL) /**< \brief (GCLK) Generic Clock Generator Control 11 */
#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */
#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */
#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */
#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */
#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */
#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */
#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */
#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */
#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */
#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */
#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */
#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */
#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */
#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */
#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */
#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */
#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */
#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */
#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */
#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */
#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */
#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */
#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */
#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */
#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */
#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */
#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */
#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */
#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */
#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */
#define REG_GCLK_PCHCTRL30 (*(RwReg *)0x40001CF8UL) /**< \brief (GCLK) Peripheral Clock Control 30 */
#define REG_GCLK_PCHCTRL31 (*(RwReg *)0x40001CFCUL) /**< \brief (GCLK) Peripheral Clock Control 31 */
#define REG_GCLK_PCHCTRL32 (*(RwReg *)0x40001D00UL) /**< \brief (GCLK) Peripheral Clock Control 32 */
#define REG_GCLK_PCHCTRL33 (*(RwReg *)0x40001D04UL) /**< \brief (GCLK) Peripheral Clock Control 33 */
#define REG_GCLK_PCHCTRL34 (*(RwReg *)0x40001D08UL) /**< \brief (GCLK) Peripheral Clock Control 34 */
#define REG_GCLK_PCHCTRL35 (*(RwReg *)0x40001D0CUL) /**< \brief (GCLK) Peripheral Clock Control 35 */
#define REG_GCLK_PCHCTRL36 (*(RwReg *)0x40001D10UL) /**< \brief (GCLK) Peripheral Clock Control 36 */
#define REG_GCLK_PCHCTRL37 (*(RwReg *)0x40001D14UL) /**< \brief (GCLK) Peripheral Clock Control 37 */
#define REG_GCLK_PCHCTRL38 (*(RwReg *)0x40001D18UL) /**< \brief (GCLK) Peripheral Clock Control 38 */
#define REG_GCLK_PCHCTRL39 (*(RwReg *)0x40001D1CUL) /**< \brief (GCLK) Peripheral Clock Control 39 */
#define REG_GCLK_PCHCTRL40 (*(RwReg *)0x40001D20UL) /**< \brief (GCLK) Peripheral Clock Control 40 */
#define REG_GCLK_PCHCTRL41 (*(RwReg *)0x40001D24UL) /**< \brief (GCLK) Peripheral Clock Control 41 */
#define REG_GCLK_PCHCTRL42 (*(RwReg *)0x40001D28UL) /**< \brief (GCLK) Peripheral Clock Control 42 */
#define REG_GCLK_PCHCTRL43 (*(RwReg *)0x40001D2CUL) /**< \brief (GCLK) Peripheral Clock Control 43 */
#define REG_GCLK_PCHCTRL44 (*(RwReg *)0x40001D30UL) /**< \brief (GCLK) Peripheral Clock Control 44 */
#define REG_GCLK_PCHCTRL45 (*(RwReg *)0x40001D34UL) /**< \brief (GCLK) Peripheral Clock Control 45 */
#define REG_GCLK_PCHCTRL46 (*(RwReg *)0x40001D38UL) /**< \brief (GCLK) Peripheral Clock Control 46 */
#define REG_GCLK_PCHCTRL47 (*(RwReg *)0x40001D3CUL) /**< \brief (GCLK) Peripheral Clock Control 47 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
#define GCLK_GENCTRL0_RESETVALUE 106 // Default specific reset value for generator 0
#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_BITS 4
#define GCLK_GEN_NUM 12 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 11 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
#define GCLK_IO_NUM 8 // Number of Generic Clock I/Os
#define GCLK_NUM 48 // Number of Generic Clock Users
#define GCLK_SOURCE_BITS 4
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
#define GCLK_SOURCE_XOSC0 0 // Crystal Oscillator 0
#define GCLK_SOURCE_XOSC 0 // Alias to GCLK_SOURCE_XOSC0
#define GCLK_SOURCE_XOSC1 1 // Crystal Oscillator 1
#define GCLK_SOURCE_GCLKIN 2 // Input Pin of Corresponding GCLK Generator
#define GCLK_SOURCE_GCLKGEN1 3 // GCLK Generator 1 output
#define GCLK_SOURCE_OSCULP32K 4 // Ultra-low-power 32kHz Oscillator
#define GCLK_SOURCE_XOSC32K 5 // 32kHz Crystal Oscillator
#define GCLK_SOURCE_DFLL 6 // Digital FLL
#define GCLK_SOURCE_DFLL48M 6 // Alias to GCLK_SOURCE_DFLL
#define GCLK_SOURCE_OSC16M 6 // Alias to GCLK_SOURCE_DFLL
#define GCLK_SOURCE_OSC48M 6 // Alias to GCLK_SOURCE_DFLL
#define GCLK_SOURCE_DPLL0 7 // Digital PLL 0
#define GCLK_SOURCE_FDPLL 7 // Alias to GCLK_SOURCE_DPLL0
#define GCLK_SOURCE_FDPLL0 7 // Alias to GCLK_SOURCE_DPLL0
#define GCLK_SOURCE_DPLL1 8 // Digital PLL 1
#define GCLK_SOURCE_FDPLL1 8 // Alias to GCLK_SOURCE_DPLL1
#define GCLK_GEN_DIV_BITS { 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 }
#endif /* _SAMD51_GCLK_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for HMATRIX
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_HMATRIX_INSTANCE_
#define _SAMD51_HMATRIX_INSTANCE_
/* ========== Register definition for HMATRIX peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_HMATRIX_PRAS0 (0x4100C080) /**< \brief (HMATRIX) Priority A for Slave 0 */
#define REG_HMATRIX_PRBS0 (0x4100C084) /**< \brief (HMATRIX) Priority B for Slave 0 */
#define REG_HMATRIX_PRAS1 (0x4100C088) /**< \brief (HMATRIX) Priority A for Slave 1 */
#define REG_HMATRIX_PRBS1 (0x4100C08C) /**< \brief (HMATRIX) Priority B for Slave 1 */
#define REG_HMATRIX_PRAS2 (0x4100C090) /**< \brief (HMATRIX) Priority A for Slave 2 */
#define REG_HMATRIX_PRBS2 (0x4100C094) /**< \brief (HMATRIX) Priority B for Slave 2 */
#define REG_HMATRIX_PRAS3 (0x4100C098) /**< \brief (HMATRIX) Priority A for Slave 3 */
#define REG_HMATRIX_PRBS3 (0x4100C09C) /**< \brief (HMATRIX) Priority B for Slave 3 */
#define REG_HMATRIX_PRAS4 (0x4100C0A0) /**< \brief (HMATRIX) Priority A for Slave 4 */
#define REG_HMATRIX_PRBS4 (0x4100C0A4) /**< \brief (HMATRIX) Priority B for Slave 4 */
#define REG_HMATRIX_PRAS5 (0x4100C0A8) /**< \brief (HMATRIX) Priority A for Slave 5 */
#define REG_HMATRIX_PRBS5 (0x4100C0AC) /**< \brief (HMATRIX) Priority B for Slave 5 */
#define REG_HMATRIX_PRAS6 (0x4100C0B0) /**< \brief (HMATRIX) Priority A for Slave 6 */
#define REG_HMATRIX_PRBS6 (0x4100C0B4) /**< \brief (HMATRIX) Priority B for Slave 6 */
#define REG_HMATRIX_PRAS7 (0x4100C0B8) /**< \brief (HMATRIX) Priority A for Slave 7 */
#define REG_HMATRIX_PRBS7 (0x4100C0BC) /**< \brief (HMATRIX) Priority B for Slave 7 */
#define REG_HMATRIX_PRAS8 (0x4100C0C0) /**< \brief (HMATRIX) Priority A for Slave 8 */
#define REG_HMATRIX_PRBS8 (0x4100C0C4) /**< \brief (HMATRIX) Priority B for Slave 8 */
#define REG_HMATRIX_PRAS9 (0x4100C0C8) /**< \brief (HMATRIX) Priority A for Slave 9 */
#define REG_HMATRIX_PRBS9 (0x4100C0CC) /**< \brief (HMATRIX) Priority B for Slave 9 */
#define REG_HMATRIX_PRAS10 (0x4100C0D0) /**< \brief (HMATRIX) Priority A for Slave 10 */
#define REG_HMATRIX_PRBS10 (0x4100C0D4) /**< \brief (HMATRIX) Priority B for Slave 10 */
#define REG_HMATRIX_PRAS11 (0x4100C0D8) /**< \brief (HMATRIX) Priority A for Slave 11 */
#define REG_HMATRIX_PRBS11 (0x4100C0DC) /**< \brief (HMATRIX) Priority B for Slave 11 */
#define REG_HMATRIX_PRAS12 (0x4100C0E0) /**< \brief (HMATRIX) Priority A for Slave 12 */
#define REG_HMATRIX_PRBS12 (0x4100C0E4) /**< \brief (HMATRIX) Priority B for Slave 12 */
#define REG_HMATRIX_PRAS13 (0x4100C0E8) /**< \brief (HMATRIX) Priority A for Slave 13 */
#define REG_HMATRIX_PRBS13 (0x4100C0EC) /**< \brief (HMATRIX) Priority B for Slave 13 */
#define REG_HMATRIX_PRAS14 (0x4100C0F0) /**< \brief (HMATRIX) Priority A for Slave 14 */
#define REG_HMATRIX_PRBS14 (0x4100C0F4) /**< \brief (HMATRIX) Priority B for Slave 14 */
#define REG_HMATRIX_PRAS15 (0x4100C0F8) /**< \brief (HMATRIX) Priority A for Slave 15 */
#define REG_HMATRIX_PRBS15 (0x4100C0FC) /**< \brief (HMATRIX) Priority B for Slave 15 */
#else
#define REG_HMATRIX_PRAS0 (*(RwReg *)0x4100C080UL) /**< \brief (HMATRIX) Priority A for Slave 0 */
#define REG_HMATRIX_PRBS0 (*(RwReg *)0x4100C084UL) /**< \brief (HMATRIX) Priority B for Slave 0 */
#define REG_HMATRIX_PRAS1 (*(RwReg *)0x4100C088UL) /**< \brief (HMATRIX) Priority A for Slave 1 */
#define REG_HMATRIX_PRBS1 (*(RwReg *)0x4100C08CUL) /**< \brief (HMATRIX) Priority B for Slave 1 */
#define REG_HMATRIX_PRAS2 (*(RwReg *)0x4100C090UL) /**< \brief (HMATRIX) Priority A for Slave 2 */
#define REG_HMATRIX_PRBS2 (*(RwReg *)0x4100C094UL) /**< \brief (HMATRIX) Priority B for Slave 2 */
#define REG_HMATRIX_PRAS3 (*(RwReg *)0x4100C098UL) /**< \brief (HMATRIX) Priority A for Slave 3 */
#define REG_HMATRIX_PRBS3 (*(RwReg *)0x4100C09CUL) /**< \brief (HMATRIX) Priority B for Slave 3 */
#define REG_HMATRIX_PRAS4 (*(RwReg *)0x4100C0A0UL) /**< \brief (HMATRIX) Priority A for Slave 4 */
#define REG_HMATRIX_PRBS4 (*(RwReg *)0x4100C0A4UL) /**< \brief (HMATRIX) Priority B for Slave 4 */
#define REG_HMATRIX_PRAS5 (*(RwReg *)0x4100C0A8UL) /**< \brief (HMATRIX) Priority A for Slave 5 */
#define REG_HMATRIX_PRBS5 (*(RwReg *)0x4100C0ACUL) /**< \brief (HMATRIX) Priority B for Slave 5 */
#define REG_HMATRIX_PRAS6 (*(RwReg *)0x4100C0B0UL) /**< \brief (HMATRIX) Priority A for Slave 6 */
#define REG_HMATRIX_PRBS6 (*(RwReg *)0x4100C0B4UL) /**< \brief (HMATRIX) Priority B for Slave 6 */
#define REG_HMATRIX_PRAS7 (*(RwReg *)0x4100C0B8UL) /**< \brief (HMATRIX) Priority A for Slave 7 */
#define REG_HMATRIX_PRBS7 (*(RwReg *)0x4100C0BCUL) /**< \brief (HMATRIX) Priority B for Slave 7 */
#define REG_HMATRIX_PRAS8 (*(RwReg *)0x4100C0C0UL) /**< \brief (HMATRIX) Priority A for Slave 8 */
#define REG_HMATRIX_PRBS8 (*(RwReg *)0x4100C0C4UL) /**< \brief (HMATRIX) Priority B for Slave 8 */
#define REG_HMATRIX_PRAS9 (*(RwReg *)0x4100C0C8UL) /**< \brief (HMATRIX) Priority A for Slave 9 */
#define REG_HMATRIX_PRBS9 (*(RwReg *)0x4100C0CCUL) /**< \brief (HMATRIX) Priority B for Slave 9 */
#define REG_HMATRIX_PRAS10 (*(RwReg *)0x4100C0D0UL) /**< \brief (HMATRIX) Priority A for Slave 10 */
#define REG_HMATRIX_PRBS10 (*(RwReg *)0x4100C0D4UL) /**< \brief (HMATRIX) Priority B for Slave 10 */
#define REG_HMATRIX_PRAS11 (*(RwReg *)0x4100C0D8UL) /**< \brief (HMATRIX) Priority A for Slave 11 */
#define REG_HMATRIX_PRBS11 (*(RwReg *)0x4100C0DCUL) /**< \brief (HMATRIX) Priority B for Slave 11 */
#define REG_HMATRIX_PRAS12 (*(RwReg *)0x4100C0E0UL) /**< \brief (HMATRIX) Priority A for Slave 12 */
#define REG_HMATRIX_PRBS12 (*(RwReg *)0x4100C0E4UL) /**< \brief (HMATRIX) Priority B for Slave 12 */
#define REG_HMATRIX_PRAS13 (*(RwReg *)0x4100C0E8UL) /**< \brief (HMATRIX) Priority A for Slave 13 */
#define REG_HMATRIX_PRBS13 (*(RwReg *)0x4100C0ECUL) /**< \brief (HMATRIX) Priority B for Slave 13 */
#define REG_HMATRIX_PRAS14 (*(RwReg *)0x4100C0F0UL) /**< \brief (HMATRIX) Priority A for Slave 14 */
#define REG_HMATRIX_PRBS14 (*(RwReg *)0x4100C0F4UL) /**< \brief (HMATRIX) Priority B for Slave 14 */
#define REG_HMATRIX_PRAS15 (*(RwReg *)0x4100C0F8UL) /**< \brief (HMATRIX) Priority A for Slave 15 */
#define REG_HMATRIX_PRBS15 (*(RwReg *)0x4100C0FCUL) /**< \brief (HMATRIX) Priority B for Slave 15 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for HMATRIX peripheral ========== */
#define HMATRIX_CLK_AHB_ID 5 // Index of AHB Clock in MCLK.AHBMASK register (MASK may be tied to 1 depending on chip integration)
#define HMATRIX_DEFINED
/* ========== Instance parameters for HMATRIX ========== */
#define HMATRIX_SLAVE_FLASH 0
#define HMATRIX_SLAVE_FLASH_ALT 1
#define HMATRIX_SLAVE_SEEPROM 2
#define HMATRIX_SLAVE_RAMCM4S 3
#define HMATRIX_SLAVE_RAMPPPDSU 4
#define HMATRIX_SLAVE_RAMDMAWR 5
#define HMATRIX_SLAVE_RAMDMACICM 6
#define HMATRIX_SLAVE_HPB0 7
#define HMATRIX_SLAVE_HPB1 8
#define HMATRIX_SLAVE_HPB2 9
#define HMATRIX_SLAVE_HPB3 10
#define HMATRIX_SLAVE_SDHC0 12
#define HMATRIX_SLAVE_SDHC1 13
#define HMATRIX_SLAVE_QSPI 14
#define HMATRIX_SLAVE_BKUPRAM 15
#define HMATRIX_SLAVE_NUM 16
#define HMATRIX_MASTER_CM4_S 0
#define HMATRIX_MASTER_CMCC 1
#define HMATRIX_MASTER_PICOP_MEM 2
#define HMATRIX_MASTER_PICOP_IO 3
#define HMATRIX_MASTER_DMAC_DTWR 4
#define HMATRIX_MASTER_DMAC_DTRD 5
#define HMATRIX_MASTER_ICM 6
#define HMATRIX_MASTER_DSU 7
#define HMATRIX_MASTER_NUM 8
#endif /* _SAMD51_HMATRIX_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for I2S
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_I2S_INSTANCE_
#define _SAMD51_I2S_INSTANCE_
/* ========== Register definition for I2S peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_I2S_CTRLA (0x43002800) /**< \brief (I2S) Control A */
#define REG_I2S_CLKCTRL0 (0x43002804) /**< \brief (I2S) Clock Unit 0 Control */
#define REG_I2S_CLKCTRL1 (0x43002808) /**< \brief (I2S) Clock Unit 1 Control */
#define REG_I2S_INTENCLR (0x4300280C) /**< \brief (I2S) Interrupt Enable Clear */
#define REG_I2S_INTENSET (0x43002810) /**< \brief (I2S) Interrupt Enable Set */
#define REG_I2S_INTFLAG (0x43002814) /**< \brief (I2S) Interrupt Flag Status and Clear */
#define REG_I2S_SYNCBUSY (0x43002818) /**< \brief (I2S) Synchronization Status */
#define REG_I2S_TXCTRL (0x43002820) /**< \brief (I2S) Tx Serializer Control */
#define REG_I2S_RXCTRL (0x43002824) /**< \brief (I2S) Rx Serializer Control */
#define REG_I2S_TXDATA (0x43002830) /**< \brief (I2S) Tx Data */
#define REG_I2S_RXDATA (0x43002834) /**< \brief (I2S) Rx Data */
#else
#define REG_I2S_CTRLA (*(RwReg8 *)0x43002800UL) /**< \brief (I2S) Control A */
#define REG_I2S_CLKCTRL0 (*(RwReg *)0x43002804UL) /**< \brief (I2S) Clock Unit 0 Control */
#define REG_I2S_CLKCTRL1 (*(RwReg *)0x43002808UL) /**< \brief (I2S) Clock Unit 1 Control */
#define REG_I2S_INTENCLR (*(RwReg16*)0x4300280CUL) /**< \brief (I2S) Interrupt Enable Clear */
#define REG_I2S_INTENSET (*(RwReg16*)0x43002810UL) /**< \brief (I2S) Interrupt Enable Set */
#define REG_I2S_INTFLAG (*(RwReg16*)0x43002814UL) /**< \brief (I2S) Interrupt Flag Status and Clear */
#define REG_I2S_SYNCBUSY (*(RoReg16*)0x43002818UL) /**< \brief (I2S) Synchronization Status */
#define REG_I2S_TXCTRL (*(RwReg *)0x43002820UL) /**< \brief (I2S) Tx Serializer Control */
#define REG_I2S_RXCTRL (*(RwReg *)0x43002824UL) /**< \brief (I2S) Rx Serializer Control */
#define REG_I2S_TXDATA (*(WoReg *)0x43002830UL) /**< \brief (I2S) Tx Data */
#define REG_I2S_RXDATA (*(RoReg *)0x43002834UL) /**< \brief (I2S) Rx Data */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for I2S peripheral ========== */
#define I2S_CLK_NUM 2 // Number of clock units
#define I2S_DMAC_ID_RX_0 76
#define I2S_DMAC_ID_RX_1 77
#define I2S_DMAC_ID_RX_LSB 76
#define I2S_DMAC_ID_RX_MSB 77
#define I2S_DMAC_ID_RX_SIZE 2
#define I2S_DMAC_ID_TX_0 78
#define I2S_DMAC_ID_TX_1 79
#define I2S_DMAC_ID_TX_LSB 78
#define I2S_DMAC_ID_TX_MSB 79
#define I2S_DMAC_ID_TX_SIZE 2
#define I2S_GCLK_ID_0 43
#define I2S_GCLK_ID_1 44
#define I2S_GCLK_ID_LSB 43
#define I2S_GCLK_ID_MSB 44
#define I2S_GCLK_ID_SIZE 2
#define I2S_MAX_SLOTS 8 // Max number of data slots in frame
#define I2S_MAX_WL_BITS 32 // Max number of bits in data samples
#define I2S_SER_NUM 2 // Number of serializers
#endif /* _SAMD51_I2S_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for ICM
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_ICM_INSTANCE_
#define _SAMD51_ICM_INSTANCE_
/* ========== Register definition for ICM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ICM_CFG (0x42002C00) /**< \brief (ICM) Configuration */
#define REG_ICM_CTRL (0x42002C04) /**< \brief (ICM) Control */
#define REG_ICM_SR (0x42002C08) /**< \brief (ICM) Status */
#define REG_ICM_IER (0x42002C10) /**< \brief (ICM) Interrupt Enable */
#define REG_ICM_IDR (0x42002C14) /**< \brief (ICM) Interrupt Disable */
#define REG_ICM_IMR (0x42002C18) /**< \brief (ICM) Interrupt Mask */
#define REG_ICM_ISR (0x42002C1C) /**< \brief (ICM) Interrupt Status */
#define REG_ICM_UASR (0x42002C20) /**< \brief (ICM) Undefined Access Status */
#define REG_ICM_DSCR (0x42002C30) /**< \brief (ICM) Region Descriptor Area Start Address */
#define REG_ICM_HASH (0x42002C34) /**< \brief (ICM) Region Hash Area Start Address */
#define REG_ICM_UIHVAL0 (0x42002C38) /**< \brief (ICM) User Initial Hash Value 0 */
#define REG_ICM_UIHVAL1 (0x42002C3C) /**< \brief (ICM) User Initial Hash Value 1 */
#define REG_ICM_UIHVAL2 (0x42002C40) /**< \brief (ICM) User Initial Hash Value 2 */
#define REG_ICM_UIHVAL3 (0x42002C44) /**< \brief (ICM) User Initial Hash Value 3 */
#define REG_ICM_UIHVAL4 (0x42002C48) /**< \brief (ICM) User Initial Hash Value 4 */
#define REG_ICM_UIHVAL5 (0x42002C4C) /**< \brief (ICM) User Initial Hash Value 5 */
#define REG_ICM_UIHVAL6 (0x42002C50) /**< \brief (ICM) User Initial Hash Value 6 */
#define REG_ICM_UIHVAL7 (0x42002C54) /**< \brief (ICM) User Initial Hash Value 7 */
#else
#define REG_ICM_CFG (*(RwReg *)0x42002C00UL) /**< \brief (ICM) Configuration */
#define REG_ICM_CTRL (*(WoReg *)0x42002C04UL) /**< \brief (ICM) Control */
#define REG_ICM_SR (*(RoReg *)0x42002C08UL) /**< \brief (ICM) Status */
#define REG_ICM_IER (*(WoReg *)0x42002C10UL) /**< \brief (ICM) Interrupt Enable */
#define REG_ICM_IDR (*(WoReg *)0x42002C14UL) /**< \brief (ICM) Interrupt Disable */
#define REG_ICM_IMR (*(RoReg *)0x42002C18UL) /**< \brief (ICM) Interrupt Mask */
#define REG_ICM_ISR (*(RoReg *)0x42002C1CUL) /**< \brief (ICM) Interrupt Status */
#define REG_ICM_UASR (*(RoReg *)0x42002C20UL) /**< \brief (ICM) Undefined Access Status */
#define REG_ICM_DSCR (*(RwReg *)0x42002C30UL) /**< \brief (ICM) Region Descriptor Area Start Address */
#define REG_ICM_HASH (*(RwReg *)0x42002C34UL) /**< \brief (ICM) Region Hash Area Start Address */
#define REG_ICM_UIHVAL0 (*(WoReg *)0x42002C38UL) /**< \brief (ICM) User Initial Hash Value 0 */
#define REG_ICM_UIHVAL1 (*(WoReg *)0x42002C3CUL) /**< \brief (ICM) User Initial Hash Value 1 */
#define REG_ICM_UIHVAL2 (*(WoReg *)0x42002C40UL) /**< \brief (ICM) User Initial Hash Value 2 */
#define REG_ICM_UIHVAL3 (*(WoReg *)0x42002C44UL) /**< \brief (ICM) User Initial Hash Value 3 */
#define REG_ICM_UIHVAL4 (*(WoReg *)0x42002C48UL) /**< \brief (ICM) User Initial Hash Value 4 */
#define REG_ICM_UIHVAL5 (*(WoReg *)0x42002C4CUL) /**< \brief (ICM) User Initial Hash Value 5 */
#define REG_ICM_UIHVAL6 (*(WoReg *)0x42002C50UL) /**< \brief (ICM) User Initial Hash Value 6 */
#define REG_ICM_UIHVAL7 (*(WoReg *)0x42002C54UL) /**< \brief (ICM) User Initial Hash Value 7 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for ICM peripheral ========== */
#define ICM_CLK_AHB_ID 19
#endif /* _SAMD51_ICM_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for MCLK
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_MCLK_INSTANCE_
#define _SAMD51_MCLK_INSTANCE_
/* ========== Register definition for MCLK peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */
#define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */
#define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */
#define REG_MCLK_HSDIV (0x40000804) /**< \brief (MCLK) HS Clock Division */
#define REG_MCLK_CPUDIV (0x40000805) /**< \brief (MCLK) CPU Clock Division */
#define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */
#define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */
#define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */
#define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */
#define REG_MCLK_APBDMASK (0x40000820) /**< \brief (MCLK) APBD Mask */
#else
#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */
#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */
#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */
#define REG_MCLK_HSDIV (*(RoReg8 *)0x40000804UL) /**< \brief (MCLK) HS Clock Division */
#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division */
#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */
#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */
#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */
#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */
#define REG_MCLK_APBDMASK (*(RwReg *)0x40000820UL) /**< \brief (MCLK) APBD Mask */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for MCLK peripheral ========== */
#define MCLK_SYSTEM_CLOCK 48000000 // System Clock Frequency at Reset
#endif /* _SAMD51_MCLK_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for NVMCTRL
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_NVMCTRL_INSTANCE_
#define _SAMD51_NVMCTRL_INSTANCE_
/* ========== Register definition for NVMCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */
#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */
#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
#define REG_NVMCTRL_INTENSET (0x4100400E) /**< \brief (NVMCTRL) Interrupt Enable Set */
#define REG_NVMCTRL_INTFLAG (0x41004010) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
#define REG_NVMCTRL_STATUS (0x41004012) /**< \brief (NVMCTRL) Status */
#define REG_NVMCTRL_ADDR (0x41004014) /**< \brief (NVMCTRL) Address */
#define REG_NVMCTRL_RUNLOCK (0x41004018) /**< \brief (NVMCTRL) Lock Section */
#define REG_NVMCTRL_PBLDATA0 (0x4100401C) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */
#define REG_NVMCTRL_PBLDATA1 (0x41004020) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */
#define REG_NVMCTRL_ECCERR (0x41004024) /**< \brief (NVMCTRL) ECC Error Status Register */
#define REG_NVMCTRL_DBGCTRL (0x41004028) /**< \brief (NVMCTRL) Debug Control */
#define REG_NVMCTRL_SEECFG (0x4100402A) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */
#define REG_NVMCTRL_SEESTAT (0x4100402C) /**< \brief (NVMCTRL) SmartEEPROM Status Register */
#else
#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
#define REG_NVMCTRL_CTRLB (*(WoReg16*)0x41004004UL) /**< \brief (NVMCTRL) Control B */
#define REG_NVMCTRL_PARAM (*(RoReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
#define REG_NVMCTRL_INTENCLR (*(RwReg16*)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
#define REG_NVMCTRL_INTENSET (*(RwReg16*)0x4100400EUL) /**< \brief (NVMCTRL) Interrupt Enable Set */
#define REG_NVMCTRL_INTFLAG (*(RwReg16*)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
#define REG_NVMCTRL_STATUS (*(RoReg16*)0x41004012UL) /**< \brief (NVMCTRL) Status */
#define REG_NVMCTRL_ADDR (*(RwReg *)0x41004014UL) /**< \brief (NVMCTRL) Address */
#define REG_NVMCTRL_RUNLOCK (*(RoReg *)0x41004018UL) /**< \brief (NVMCTRL) Lock Section */
#define REG_NVMCTRL_PBLDATA0 (*(RoReg *)0x4100401CUL) /**< \brief (NVMCTRL) Page Buffer Load Data x 0 */
#define REG_NVMCTRL_PBLDATA1 (*(RoReg *)0x41004020UL) /**< \brief (NVMCTRL) Page Buffer Load Data x 1 */
#define REG_NVMCTRL_ECCERR (*(RoReg *)0x41004024UL) /**< \brief (NVMCTRL) ECC Error Status Register */
#define REG_NVMCTRL_DBGCTRL (*(RwReg8 *)0x41004028UL) /**< \brief (NVMCTRL) Debug Control */
#define REG_NVMCTRL_SEECFG (*(RwReg8 *)0x4100402AUL) /**< \brief (NVMCTRL) SmartEEPROM Configuration Register */
#define REG_NVMCTRL_SEESTAT (*(RoReg *)0x4100402CUL) /**< \brief (NVMCTRL) SmartEEPROM Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for NVMCTRL peripheral ========== */
#define NVMCTRL_BLOCK_SIZE 8192 // Size Of Block (Bytes, Smallest Granularity for Erase Operation)
#define NVMCTRL_CLK_AHB_ID 6 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_CLK_AHB_ID_CACHE 23 // Index of AHB Clock in PM.AHBMASK register for NVMCTRL CACHE lines
#define NVMCTRL_CLK_AHB_ID_SMEEPROM 22 // Index of AHB Clock in PM.AHBMASK register for SMEE submodule
#define NVMCTRL_PAGE_SIZE 512 // Size Of Page (Bytes, Smallest Granularity for Write Operation In Main Array)
#endif /* _SAMD51_NVMCTRL_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for OSC32KCTRL
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_OSC32KCTRL_INSTANCE_
#define _SAMD51_OSC32KCTRL_INSTANCE_
/* ========== Register definition for OSC32KCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
#define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
#define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
#define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */
#define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */
#define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
#define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */
#define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#else
#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */
#define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */
#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */
#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 0 // OSC32K coarse calibration size
#endif /* _SAMD51_OSC32KCTRL_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for OSCCTRL
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_OSCCTRL_INSTANCE_
#define _SAMD51_OSCCTRL_INSTANCE_
/* ========== Register definition for OSCCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_OSCCTRL_EVCTRL (0x40001000) /**< \brief (OSCCTRL) Event Control */
#define REG_OSCCTRL_INTENCLR (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Clear */
#define REG_OSCCTRL_INTENSET (0x40001008) /**< \brief (OSCCTRL) Interrupt Enable Set */
#define REG_OSCCTRL_INTFLAG (0x4000100C) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
#define REG_OSCCTRL_STATUS (0x40001010) /**< \brief (OSCCTRL) Status */
#define REG_OSCCTRL_XOSCCTRL0 (0x40001014) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
#define REG_OSCCTRL_XOSCCTRL1 (0x40001018) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
#define REG_OSCCTRL_DFLLCTRLA (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Control A */
#define REG_OSCCTRL_DFLLCTRLB (0x40001020) /**< \brief (OSCCTRL) DFLL48M Control B */
#define REG_OSCCTRL_DFLLVAL (0x40001024) /**< \brief (OSCCTRL) DFLL48M Value */
#define REG_OSCCTRL_DFLLMUL (0x40001028) /**< \brief (OSCCTRL) DFLL48M Multiplier */
#define REG_OSCCTRL_DFLLSYNC (0x4000102C) /**< \brief (OSCCTRL) DFLL48M Synchronization */
#define REG_OSCCTRL_DPLLCTRLA0 (0x40001030) /**< \brief (OSCCTRL) DPLL Control A 0 */
#define REG_OSCCTRL_DPLLRATIO0 (0x40001034) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
#define REG_OSCCTRL_DPLLCTRLB0 (0x40001038) /**< \brief (OSCCTRL) DPLL Control B 0 */
#define REG_OSCCTRL_DPLLSYNCBUSY0 (0x4000103C) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
#define REG_OSCCTRL_DPLLSTATUS0 (0x40001040) /**< \brief (OSCCTRL) DPLL Status 0 */
#define REG_OSCCTRL_DPLLCTRLA1 (0x40001044) /**< \brief (OSCCTRL) DPLL Control A 1 */
#define REG_OSCCTRL_DPLLRATIO1 (0x40001048) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
#define REG_OSCCTRL_DPLLCTRLB1 (0x4000104C) /**< \brief (OSCCTRL) DPLL Control B 1 */
#define REG_OSCCTRL_DPLLSYNCBUSY1 (0x40001050) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
#define REG_OSCCTRL_DPLLSTATUS1 (0x40001054) /**< \brief (OSCCTRL) DPLL Status 1 */
#else
#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001000UL) /**< \brief (OSCCTRL) Event Control */
#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x4000100CUL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
#define REG_OSCCTRL_STATUS (*(RoReg *)0x40001010UL) /**< \brief (OSCCTRL) Status */
#define REG_OSCCTRL_XOSCCTRL0 (*(RwReg *)0x40001014UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
#define REG_OSCCTRL_XOSCCTRL1 (*(RwReg *)0x40001018UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
#define REG_OSCCTRL_DFLLCTRLA (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Control A */
#define REG_OSCCTRL_DFLLCTRLB (*(RwReg8 *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Control B */
#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Value */
#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001028UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */
#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DFLL48M Synchronization */
#define REG_OSCCTRL_DPLLCTRLA0 (*(RwReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Control A 0 */
#define REG_OSCCTRL_DPLLRATIO0 (*(RwReg8 *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
#define REG_OSCCTRL_DPLLCTRLB0 (*(RwReg8 *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Control B 0 */
#define REG_OSCCTRL_DPLLSYNCBUSY0 (*(RoReg8 *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
#define REG_OSCCTRL_DPLLSTATUS0 (*(RoReg8 *)0x40001040UL) /**< \brief (OSCCTRL) DPLL Status 0 */
#define REG_OSCCTRL_DPLLCTRLA1 (*(RwReg8 *)0x40001044UL) /**< \brief (OSCCTRL) DPLL Control A 1 */
#define REG_OSCCTRL_DPLLRATIO1 (*(RwReg8 *)0x40001048UL) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
#define REG_OSCCTRL_DPLLCTRLB1 (*(RwReg8 *)0x4000104CUL) /**< \brief (OSCCTRL) DPLL Control B 1 */
#define REG_OSCCTRL_DPLLSYNCBUSY1 (*(RoReg8 *)0x40001050UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
#define REG_OSCCTRL_DPLLSTATUS1 (*(RoReg8 *)0x40001054UL) /**< \brief (OSCCTRL) DPLL Status 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for OSCCTRL peripheral ========== */
#define OSCCTRL_DFLLS_NUM 1 // Number of DFLLs
#define OSCCTRL_DFLL_IMPLEMENTED 1 // DFLL implemented
#define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED 0 // DFLL48M bias test mode implemented
#define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE 2 // Size COARSE DAC STEP
#define OSCCTRL_DFLL48M_COARSE_RESET_VALUE 32 // DFLL48M Frequency Coarse Reset Value (Before Calibration)
#define OSCCTRL_DFLL48M_COARSE_SIZE 6 // Size COARSE CALIBRATION
#define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE 1 // Run oscillator at reset
#define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE 2 // Size FINE DAC STEP
#define OSCCTRL_DFLL48M_FINE_RESET_VALUE 128 // DFLL48M Frequency Fine Reset Value (Before Calibration)
#define OSCCTRL_DFLL48M_FINE_SIZE 8 // Size FINE CALIBRATION
#define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
#define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
#define OSCCTRL_DFLL48M_TCAL_SIZE 4 // Size TEMP CALIBRATION
#define OSCCTRL_DFLL48M_TCBIAS_SIZE 2 // Size TC BIAS CALIBRATION
#define OSCCTRL_DFLL48M_TESTPTSEL_SIZE 3 // Size TEST POINT SELECTOR
#define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE 1 // Enable Wait Lock Feature
#define OSCCTRL_DPLLS_NUM 2 // Number of DPLLs
#define OSCCTRL_DPLL0_IMPLEMENTED 1 // DPLL0 implemented
#define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
#define OSCCTRL_DPLL0_OCC_IMPLEMENTED 1 // DPLL0 OCC Implemented
#define OSCCTRL_DPLL1_IMPLEMENTED 1 // DPLL1 implemented
#define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
#define OSCCTRL_DPLL1_OCC_IMPLEMENTED 0 // DPLL1 OCC Implemented
#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
#define OSCCTRL_GCLK_ID_FDPLL0 1 // Index of Generic Clock for DPLL0
#define OSCCTRL_GCLK_ID_FDPLL1 2 // Index of Generic Clock for DPLL1
#define OSCCTRL_GCLK_ID_FDPLL032K 3 // Index of Generic Clock for DPLL0 32K
#define OSCCTRL_GCLK_ID_FDPLL132K 3 // Index of Generic Clock for DPLL1 32K
#define OSCCTRL_OSC16M_IMPLEMENTED 0 // OSC16M implemented
#define OSCCTRL_OSC48M_IMPLEMENTED 0 // OSC48M implemented
#define OSCCTRL_OSC48M_NUM 1
#define OSCCTRL_RCOSCS_NUM 1 // Number of RCOSCs (min 1)
#define OSCCTRL_XOSCS_NUM 2 // Number of XOSCs
#define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
#define OSCCTRL_XOSC0_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
#define OSCCTRL_XOSC0_IMPLEMENTED 1 // XOSC0 implemented
#define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
#define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
#define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
#define OSCCTRL_XOSC1_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
#define OSCCTRL_XOSC1_IMPLEMENTED 1 // XOSC1 implemented
#define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
#define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
#define OSCCTRL_DFLL48M_VERSION 0x100
#define OSCCTRL_FDPLL_VERSION 0x100
#define OSCCTRL_XOSC_VERSION 0x100
#endif /* _SAMD51_OSCCTRL_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PAC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PAC_INSTANCE_
#define _SAMD51_PAC_INSTANCE_
/* ========== Register definition for PAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */
#define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */
#define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */
#define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */
#define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */
#define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
#define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
#define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
#define REG_PAC_INTFLAGD (0x40000020) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
#define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */
#define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */
#define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */
#define REG_PAC_STATUSD (0x40000040) /**< \brief (PAC) Peripheral write protection status - Bridge D */
#else
#define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */
#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */
#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */
#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */
#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */
#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
#define REG_PAC_INTFLAGD (*(RwReg *)0x40000020UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge D */
#define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */
#define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */
#define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */
#define REG_PAC_STATUSD (*(RoReg *)0x40000040UL) /**< \brief (PAC) Peripheral write protection status - Bridge D */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PAC peripheral ========== */
#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock
#define PAC_CLK_AHB_ID 12 // AHB clock index
#define PAC_HPB_NUM 4 // Number of bridges AHB/APB
#endif /* _SAMD51_PAC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PCC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PCC_INSTANCE_
#define _SAMD51_PCC_INSTANCE_
/* ========== Register definition for PCC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PCC_MR (0x43002C00) /**< \brief (PCC) Mode Register */
#define REG_PCC_IER (0x43002C04) /**< \brief (PCC) Interrupt Enable Register */
#define REG_PCC_IDR (0x43002C08) /**< \brief (PCC) Interrupt Disable Register */
#define REG_PCC_IMR (0x43002C0C) /**< \brief (PCC) Interrupt Mask Register */
#define REG_PCC_ISR (0x43002C10) /**< \brief (PCC) Interrupt Status Register */
#define REG_PCC_RHR (0x43002C14) /**< \brief (PCC) Reception Holding Register */
#define REG_PCC_WPMR (0x43002CE0) /**< \brief (PCC) Write Protection Mode Register */
#define REG_PCC_WPSR (0x43002CE4) /**< \brief (PCC) Write Protection Status Register */
#else
#define REG_PCC_MR (*(RwReg *)0x43002C00UL) /**< \brief (PCC) Mode Register */
#define REG_PCC_IER (*(WoReg *)0x43002C04UL) /**< \brief (PCC) Interrupt Enable Register */
#define REG_PCC_IDR (*(WoReg *)0x43002C08UL) /**< \brief (PCC) Interrupt Disable Register */
#define REG_PCC_IMR (*(RoReg *)0x43002C0CUL) /**< \brief (PCC) Interrupt Mask Register */
#define REG_PCC_ISR (*(RoReg *)0x43002C10UL) /**< \brief (PCC) Interrupt Status Register */
#define REG_PCC_RHR (*(RoReg *)0x43002C14UL) /**< \brief (PCC) Reception Holding Register */
#define REG_PCC_WPMR (*(RwReg *)0x43002CE0UL) /**< \brief (PCC) Write Protection Mode Register */
#define REG_PCC_WPSR (*(RoReg *)0x43002CE4UL) /**< \brief (PCC) Write Protection Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PCC peripheral ========== */
#define PCC_DATA_SIZE 14
#define PCC_DMAC_ID_RX 80
#endif /* _SAMD51_PCC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PDEC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PDEC_INSTANCE_
#define _SAMD51_PDEC_INSTANCE_
/* ========== Register definition for PDEC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PDEC_CTRLA (0x42001C00) /**< \brief (PDEC) Control A */
#define REG_PDEC_CTRLBCLR (0x42001C04) /**< \brief (PDEC) Control B Clear */
#define REG_PDEC_CTRLBSET (0x42001C05) /**< \brief (PDEC) Control B Set */
#define REG_PDEC_EVCTRL (0x42001C06) /**< \brief (PDEC) Event Control */
#define REG_PDEC_INTENCLR (0x42001C08) /**< \brief (PDEC) Interrupt Enable Clear */
#define REG_PDEC_INTENSET (0x42001C09) /**< \brief (PDEC) Interrupt Enable Set */
#define REG_PDEC_INTFLAG (0x42001C0A) /**< \brief (PDEC) Interrupt Flag Status and Clear */
#define REG_PDEC_STATUS (0x42001C0C) /**< \brief (PDEC) Status */
#define REG_PDEC_DBGCTRL (0x42001C0F) /**< \brief (PDEC) Debug Control */
#define REG_PDEC_SYNCBUSY (0x42001C10) /**< \brief (PDEC) Synchronization Status */
#define REG_PDEC_PRESC (0x42001C14) /**< \brief (PDEC) Prescaler Value */
#define REG_PDEC_FILTER (0x42001C15) /**< \brief (PDEC) Filter Value */
#define REG_PDEC_PRESCBUF (0x42001C18) /**< \brief (PDEC) Prescaler Buffer Value */
#define REG_PDEC_FILTERBUF (0x42001C19) /**< \brief (PDEC) Filter Buffer Value */
#define REG_PDEC_COUNT (0x42001C1C) /**< \brief (PDEC) Counter Value */
#define REG_PDEC_CC0 (0x42001C20) /**< \brief (PDEC) Channel 0 Compare Value */
#define REG_PDEC_CC1 (0x42001C24) /**< \brief (PDEC) Channel 1 Compare Value */
#define REG_PDEC_CCBUF0 (0x42001C30) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
#define REG_PDEC_CCBUF1 (0x42001C34) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
#else
#define REG_PDEC_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (PDEC) Control A */
#define REG_PDEC_CTRLBCLR (*(RwReg8 *)0x42001C04UL) /**< \brief (PDEC) Control B Clear */
#define REG_PDEC_CTRLBSET (*(RwReg8 *)0x42001C05UL) /**< \brief (PDEC) Control B Set */
#define REG_PDEC_EVCTRL (*(RwReg16*)0x42001C06UL) /**< \brief (PDEC) Event Control */
#define REG_PDEC_INTENCLR (*(RwReg8 *)0x42001C08UL) /**< \brief (PDEC) Interrupt Enable Clear */
#define REG_PDEC_INTENSET (*(RwReg8 *)0x42001C09UL) /**< \brief (PDEC) Interrupt Enable Set */
#define REG_PDEC_INTFLAG (*(RwReg8 *)0x42001C0AUL) /**< \brief (PDEC) Interrupt Flag Status and Clear */
#define REG_PDEC_STATUS (*(RwReg16*)0x42001C0CUL) /**< \brief (PDEC) Status */
#define REG_PDEC_DBGCTRL (*(RwReg8 *)0x42001C0FUL) /**< \brief (PDEC) Debug Control */
#define REG_PDEC_SYNCBUSY (*(RoReg *)0x42001C10UL) /**< \brief (PDEC) Synchronization Status */
#define REG_PDEC_PRESC (*(RwReg8 *)0x42001C14UL) /**< \brief (PDEC) Prescaler Value */
#define REG_PDEC_FILTER (*(RwReg8 *)0x42001C15UL) /**< \brief (PDEC) Filter Value */
#define REG_PDEC_PRESCBUF (*(RwReg8 *)0x42001C18UL) /**< \brief (PDEC) Prescaler Buffer Value */
#define REG_PDEC_FILTERBUF (*(RwReg8 *)0x42001C19UL) /**< \brief (PDEC) Filter Buffer Value */
#define REG_PDEC_COUNT (*(RwReg *)0x42001C1CUL) /**< \brief (PDEC) Counter Value */
#define REG_PDEC_CC0 (*(RwReg *)0x42001C20UL) /**< \brief (PDEC) Channel 0 Compare Value */
#define REG_PDEC_CC1 (*(RwReg *)0x42001C24UL) /**< \brief (PDEC) Channel 1 Compare Value */
#define REG_PDEC_CCBUF0 (*(RwReg *)0x42001C30UL) /**< \brief (PDEC) Channel Compare Buffer Value 0 */
#define REG_PDEC_CCBUF1 (*(RwReg *)0x42001C34UL) /**< \brief (PDEC) Channel Compare Buffer Value 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PDEC peripheral ========== */
#define PDEC_CC_NUM 2 // Number of Compare Channels units
#define PDEC_GCLK_ID 31
#endif /* _SAMD51_PDEC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PM
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PM_INSTANCE_
#define _SAMD51_PM_INSTANCE_
/* ========== Register definition for PM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PM_CTRLA (0x40000400) /**< \brief (PM) Control A */
#define REG_PM_SLEEPCFG (0x40000401) /**< \brief (PM) Sleep Configuration */
#define REG_PM_INTENCLR (0x40000404) /**< \brief (PM) Interrupt Enable Clear */
#define REG_PM_INTENSET (0x40000405) /**< \brief (PM) Interrupt Enable Set */
#define REG_PM_INTFLAG (0x40000406) /**< \brief (PM) Interrupt Flag Status and Clear */
#define REG_PM_STDBYCFG (0x40000408) /**< \brief (PM) Standby Configuration */
#define REG_PM_HIBCFG (0x40000409) /**< \brief (PM) Hibernate Configuration */
#define REG_PM_BKUPCFG (0x4000040A) /**< \brief (PM) Backup Configuration */
#define REG_PM_PWSAKDLY (0x40000412) /**< \brief (PM) Power Switch Acknowledge Delay */
#else
#define REG_PM_CTRLA (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control A */
#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */
#define REG_PM_INTENCLR (*(RwReg8 *)0x40000404UL) /**< \brief (PM) Interrupt Enable Clear */
#define REG_PM_INTENSET (*(RwReg8 *)0x40000405UL) /**< \brief (PM) Interrupt Enable Set */
#define REG_PM_INTFLAG (*(RwReg8 *)0x40000406UL) /**< \brief (PM) Interrupt Flag Status and Clear */
#define REG_PM_STDBYCFG (*(RwReg8 *)0x40000408UL) /**< \brief (PM) Standby Configuration */
#define REG_PM_HIBCFG (*(RwReg8 *)0x40000409UL) /**< \brief (PM) Hibernate Configuration */
#define REG_PM_BKUPCFG (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) Backup Configuration */
#define REG_PM_PWSAKDLY (*(RwReg8 *)0x40000412UL) /**< \brief (PM) Power Switch Acknowledge Delay */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PM peripheral ========== */
#define PM_PD_NUM 0 // Number of switchable Power Domains
#endif /* _SAMD51_PM_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PORT
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PORT_INSTANCE_
#define _SAMD51_PORT_INSTANCE_
/* ========== Register definition for PORT peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PORT_DIR0 (0x41008000) /**< \brief (PORT) Data Direction 0 */
#define REG_PORT_DIRCLR0 (0x41008004) /**< \brief (PORT) Data Direction Clear 0 */
#define REG_PORT_DIRSET0 (0x41008008) /**< \brief (PORT) Data Direction Set 0 */
#define REG_PORT_DIRTGL0 (0x4100800C) /**< \brief (PORT) Data Direction Toggle 0 */
#define REG_PORT_OUT0 (0x41008010) /**< \brief (PORT) Data Output Value 0 */
#define REG_PORT_OUTCLR0 (0x41008014) /**< \brief (PORT) Data Output Value Clear 0 */
#define REG_PORT_OUTSET0 (0x41008018) /**< \brief (PORT) Data Output Value Set 0 */
#define REG_PORT_OUTTGL0 (0x4100801C) /**< \brief (PORT) Data Output Value Toggle 0 */
#define REG_PORT_IN0 (0x41008020) /**< \brief (PORT) Data Input Value 0 */
#define REG_PORT_CTRL0 (0x41008024) /**< \brief (PORT) Control 0 */
#define REG_PORT_WRCONFIG0 (0x41008028) /**< \brief (PORT) Write Configuration 0 */
#define REG_PORT_EVCTRL0 (0x4100802C) /**< \brief (PORT) Event Input Control 0 */
#define REG_PORT_PMUX0 (0x41008030) /**< \brief (PORT) Peripheral Multiplexing 0 */
#define REG_PORT_PINCFG0 (0x41008040) /**< \brief (PORT) Pin Configuration 0 */
#define REG_PORT_DIR1 (0x41008080) /**< \brief (PORT) Data Direction 1 */
#define REG_PORT_DIRCLR1 (0x41008084) /**< \brief (PORT) Data Direction Clear 1 */
#define REG_PORT_DIRSET1 (0x41008088) /**< \brief (PORT) Data Direction Set 1 */
#define REG_PORT_DIRTGL1 (0x4100808C) /**< \brief (PORT) Data Direction Toggle 1 */
#define REG_PORT_OUT1 (0x41008090) /**< \brief (PORT) Data Output Value 1 */
#define REG_PORT_OUTCLR1 (0x41008094) /**< \brief (PORT) Data Output Value Clear 1 */
#define REG_PORT_OUTSET1 (0x41008098) /**< \brief (PORT) Data Output Value Set 1 */
#define REG_PORT_OUTTGL1 (0x4100809C) /**< \brief (PORT) Data Output Value Toggle 1 */
#define REG_PORT_IN1 (0x410080A0) /**< \brief (PORT) Data Input Value 1 */
#define REG_PORT_CTRL1 (0x410080A4) /**< \brief (PORT) Control 1 */
#define REG_PORT_WRCONFIG1 (0x410080A8) /**< \brief (PORT) Write Configuration 1 */
#define REG_PORT_EVCTRL1 (0x410080AC) /**< \brief (PORT) Event Input Control 1 */
#define REG_PORT_PMUX1 (0x410080B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
#define REG_PORT_PINCFG1 (0x410080C0) /**< \brief (PORT) Pin Configuration 1 */
#define REG_PORT_DIR2 (0x41008100) /**< \brief (PORT) Data Direction 2 */
#define REG_PORT_DIRCLR2 (0x41008104) /**< \brief (PORT) Data Direction Clear 2 */
#define REG_PORT_DIRSET2 (0x41008108) /**< \brief (PORT) Data Direction Set 2 */
#define REG_PORT_DIRTGL2 (0x4100810C) /**< \brief (PORT) Data Direction Toggle 2 */
#define REG_PORT_OUT2 (0x41008110) /**< \brief (PORT) Data Output Value 2 */
#define REG_PORT_OUTCLR2 (0x41008114) /**< \brief (PORT) Data Output Value Clear 2 */
#define REG_PORT_OUTSET2 (0x41008118) /**< \brief (PORT) Data Output Value Set 2 */
#define REG_PORT_OUTTGL2 (0x4100811C) /**< \brief (PORT) Data Output Value Toggle 2 */
#define REG_PORT_IN2 (0x41008120) /**< \brief (PORT) Data Input Value 2 */
#define REG_PORT_CTRL2 (0x41008124) /**< \brief (PORT) Control 2 */
#define REG_PORT_WRCONFIG2 (0x41008128) /**< \brief (PORT) Write Configuration 2 */
#define REG_PORT_EVCTRL2 (0x4100812C) /**< \brief (PORT) Event Input Control 2 */
#define REG_PORT_PMUX2 (0x41008130) /**< \brief (PORT) Peripheral Multiplexing 2 */
#define REG_PORT_PINCFG2 (0x41008140) /**< \brief (PORT) Pin Configuration 2 */
#define REG_PORT_DIR3 (0x41008180) /**< \brief (PORT) Data Direction 3 */
#define REG_PORT_DIRCLR3 (0x41008184) /**< \brief (PORT) Data Direction Clear 3 */
#define REG_PORT_DIRSET3 (0x41008188) /**< \brief (PORT) Data Direction Set 3 */
#define REG_PORT_DIRTGL3 (0x4100818C) /**< \brief (PORT) Data Direction Toggle 3 */
#define REG_PORT_OUT3 (0x41008190) /**< \brief (PORT) Data Output Value 3 */
#define REG_PORT_OUTCLR3 (0x41008194) /**< \brief (PORT) Data Output Value Clear 3 */
#define REG_PORT_OUTSET3 (0x41008198) /**< \brief (PORT) Data Output Value Set 3 */
#define REG_PORT_OUTTGL3 (0x4100819C) /**< \brief (PORT) Data Output Value Toggle 3 */
#define REG_PORT_IN3 (0x410081A0) /**< \brief (PORT) Data Input Value 3 */
#define REG_PORT_CTRL3 (0x410081A4) /**< \brief (PORT) Control 3 */
#define REG_PORT_WRCONFIG3 (0x410081A8) /**< \brief (PORT) Write Configuration 3 */
#define REG_PORT_EVCTRL3 (0x410081AC) /**< \brief (PORT) Event Input Control 3 */
#define REG_PORT_PMUX3 (0x410081B0) /**< \brief (PORT) Peripheral Multiplexing 3 */
#define REG_PORT_PINCFG3 (0x410081C0) /**< \brief (PORT) Pin Configuration 3 */
#else
#define REG_PORT_DIR0 (*(RwReg *)0x41008000UL) /**< \brief (PORT) Data Direction 0 */
#define REG_PORT_DIRCLR0 (*(RwReg *)0x41008004UL) /**< \brief (PORT) Data Direction Clear 0 */
#define REG_PORT_DIRSET0 (*(RwReg *)0x41008008UL) /**< \brief (PORT) Data Direction Set 0 */
#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100800CUL) /**< \brief (PORT) Data Direction Toggle 0 */
#define REG_PORT_OUT0 (*(RwReg *)0x41008010UL) /**< \brief (PORT) Data Output Value 0 */
#define REG_PORT_OUTCLR0 (*(RwReg *)0x41008014UL) /**< \brief (PORT) Data Output Value Clear 0 */
#define REG_PORT_OUTSET0 (*(RwReg *)0x41008018UL) /**< \brief (PORT) Data Output Value Set 0 */
#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100801CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
#define REG_PORT_IN0 (*(RoReg *)0x41008020UL) /**< \brief (PORT) Data Input Value 0 */
#define REG_PORT_CTRL0 (*(RwReg *)0x41008024UL) /**< \brief (PORT) Control 0 */
#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41008028UL) /**< \brief (PORT) Write Configuration 0 */
#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100802CUL) /**< \brief (PORT) Event Input Control 0 */
#define REG_PORT_PMUX0 (*(RwReg *)0x41008030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
#define REG_PORT_PINCFG0 (*(RwReg *)0x41008040UL) /**< \brief (PORT) Pin Configuration 0 */
#define REG_PORT_DIR1 (*(RwReg *)0x41008080UL) /**< \brief (PORT) Data Direction 1 */
#define REG_PORT_DIRCLR1 (*(RwReg *)0x41008084UL) /**< \brief (PORT) Data Direction Clear 1 */
#define REG_PORT_DIRSET1 (*(RwReg *)0x41008088UL) /**< \brief (PORT) Data Direction Set 1 */
#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100808CUL) /**< \brief (PORT) Data Direction Toggle 1 */
#define REG_PORT_OUT1 (*(RwReg *)0x41008090UL) /**< \brief (PORT) Data Output Value 1 */
#define REG_PORT_OUTCLR1 (*(RwReg *)0x41008094UL) /**< \brief (PORT) Data Output Value Clear 1 */
#define REG_PORT_OUTSET1 (*(RwReg *)0x41008098UL) /**< \brief (PORT) Data Output Value Set 1 */
#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100809CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
#define REG_PORT_IN1 (*(RoReg *)0x410080A0UL) /**< \brief (PORT) Data Input Value 1 */
#define REG_PORT_CTRL1 (*(RwReg *)0x410080A4UL) /**< \brief (PORT) Control 1 */
#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410080A8UL) /**< \brief (PORT) Write Configuration 1 */
#define REG_PORT_EVCTRL1 (*(RwReg *)0x410080ACUL) /**< \brief (PORT) Event Input Control 1 */
#define REG_PORT_PMUX1 (*(RwReg *)0x410080B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
#define REG_PORT_PINCFG1 (*(RwReg *)0x410080C0UL) /**< \brief (PORT) Pin Configuration 1 */
#define REG_PORT_DIR2 (*(RwReg *)0x41008100UL) /**< \brief (PORT) Data Direction 2 */
#define REG_PORT_DIRCLR2 (*(RwReg *)0x41008104UL) /**< \brief (PORT) Data Direction Clear 2 */
#define REG_PORT_DIRSET2 (*(RwReg *)0x41008108UL) /**< \brief (PORT) Data Direction Set 2 */
#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100810CUL) /**< \brief (PORT) Data Direction Toggle 2 */
#define REG_PORT_OUT2 (*(RwReg *)0x41008110UL) /**< \brief (PORT) Data Output Value 2 */
#define REG_PORT_OUTCLR2 (*(RwReg *)0x41008114UL) /**< \brief (PORT) Data Output Value Clear 2 */
#define REG_PORT_OUTSET2 (*(RwReg *)0x41008118UL) /**< \brief (PORT) Data Output Value Set 2 */
#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100811CUL) /**< \brief (PORT) Data Output Value Toggle 2 */
#define REG_PORT_IN2 (*(RoReg *)0x41008120UL) /**< \brief (PORT) Data Input Value 2 */
#define REG_PORT_CTRL2 (*(RwReg *)0x41008124UL) /**< \brief (PORT) Control 2 */
#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41008128UL) /**< \brief (PORT) Write Configuration 2 */
#define REG_PORT_EVCTRL2 (*(RwReg *)0x4100812CUL) /**< \brief (PORT) Event Input Control 2 */
#define REG_PORT_PMUX2 (*(RwReg *)0x41008130UL) /**< \brief (PORT) Peripheral Multiplexing 2 */
#define REG_PORT_PINCFG2 (*(RwReg *)0x41008140UL) /**< \brief (PORT) Pin Configuration 2 */
#define REG_PORT_DIR3 (*(RwReg *)0x41008180UL) /**< \brief (PORT) Data Direction 3 */
#define REG_PORT_DIRCLR3 (*(RwReg *)0x41008184UL) /**< \brief (PORT) Data Direction Clear 3 */
#define REG_PORT_DIRSET3 (*(RwReg *)0x41008188UL) /**< \brief (PORT) Data Direction Set 3 */
#define REG_PORT_DIRTGL3 (*(RwReg *)0x4100818CUL) /**< \brief (PORT) Data Direction Toggle 3 */
#define REG_PORT_OUT3 (*(RwReg *)0x41008190UL) /**< \brief (PORT) Data Output Value 3 */
#define REG_PORT_OUTCLR3 (*(RwReg *)0x41008194UL) /**< \brief (PORT) Data Output Value Clear 3 */
#define REG_PORT_OUTSET3 (*(RwReg *)0x41008198UL) /**< \brief (PORT) Data Output Value Set 3 */
#define REG_PORT_OUTTGL3 (*(RwReg *)0x4100819CUL) /**< \brief (PORT) Data Output Value Toggle 3 */
#define REG_PORT_IN3 (*(RoReg *)0x410081A0UL) /**< \brief (PORT) Data Input Value 3 */
#define REG_PORT_CTRL3 (*(RwReg *)0x410081A4UL) /**< \brief (PORT) Control 3 */
#define REG_PORT_WRCONFIG3 (*(WoReg *)0x410081A8UL) /**< \brief (PORT) Write Configuration 3 */
#define REG_PORT_EVCTRL3 (*(RwReg *)0x410081ACUL) /**< \brief (PORT) Event Input Control 3 */
#define REG_PORT_PMUX3 (*(RwReg *)0x410081B0UL) /**< \brief (PORT) Peripheral Multiplexing 3 */
#define REG_PORT_PINCFG3 (*(RwReg *)0x410081C0UL) /**< \brief (PORT) Pin Configuration 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PORT peripheral ========== */
#define PORT_BITS 118
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
#define PORT_DRVSTR 1 // DRVSTR supported
#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
#define PORT_EV_NUM 4
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
#define PORT_ODRAIN 0 // ODRAIN supported
#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
#define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
#define PORT_PMUXBIT0_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 }
#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 }
#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PMUXBIT2_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 }
#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PMUXBIT3_IMPLEMENTED { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 }
#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
#define PORT_PPP_IMPLEMENTED { 0x00000001 } // IOBUS2 implemented?
#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
#define PORT_SLEWLIM 0 // SLEWLIM supported
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
#endif /* _SAMD51_PORT_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PUKCC
*
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_PUKCC_INSTANCE_
#define _SAMD51_PUKCC_INSTANCE_
/* ========== Register definition for PUKCC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#else
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PUKCC peripheral ========== */
#define PUKCC_CLK_AHB_ID 20
#define PUKCC_RAM_ADDR_SIZE 12
#define PUKCC_ROM_ADDR_SIZE 16
#endif /* _SAMD51_PUKCC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for QSPI
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_QSPI_INSTANCE_
#define _SAMD51_QSPI_INSTANCE_
/* ========== Register definition for QSPI peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_QSPI_CTRLA (0x42003400) /**< \brief (QSPI) Control A */
#define REG_QSPI_CTRLB (0x42003404) /**< \brief (QSPI) Control B */
#define REG_QSPI_BAUD (0x42003408) /**< \brief (QSPI) Baud Rate */
#define REG_QSPI_RXDATA (0x4200340C) /**< \brief (QSPI) Receive Data */
#define REG_QSPI_TXDATA (0x42003410) /**< \brief (QSPI) Transmit Data */
#define REG_QSPI_INTENCLR (0x42003414) /**< \brief (QSPI) Interrupt Enable Clear */
#define REG_QSPI_INTENSET (0x42003418) /**< \brief (QSPI) Interrupt Enable Set */
#define REG_QSPI_INTFLAG (0x4200341C) /**< \brief (QSPI) Interrupt Flag Status and Clear */
#define REG_QSPI_STATUS (0x42003420) /**< \brief (QSPI) Status Register */
#define REG_QSPI_INSTRADDR (0x42003430) /**< \brief (QSPI) Instruction Address */
#define REG_QSPI_INSTRCTRL (0x42003434) /**< \brief (QSPI) Instruction Code */
#define REG_QSPI_INSTRFRAME (0x42003438) /**< \brief (QSPI) Instruction Frame */
#define REG_QSPI_SCRAMBCTRL (0x42003440) /**< \brief (QSPI) Scrambling Mode */
#define REG_QSPI_SCRAMBKEY (0x42003444) /**< \brief (QSPI) Scrambling Key */
#else
#define REG_QSPI_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (QSPI) Control A */
#define REG_QSPI_CTRLB (*(RwReg *)0x42003404UL) /**< \brief (QSPI) Control B */
#define REG_QSPI_BAUD (*(RwReg *)0x42003408UL) /**< \brief (QSPI) Baud Rate */
#define REG_QSPI_RXDATA (*(RoReg *)0x4200340CUL) /**< \brief (QSPI) Receive Data */
#define REG_QSPI_TXDATA (*(WoReg *)0x42003410UL) /**< \brief (QSPI) Transmit Data */
#define REG_QSPI_INTENCLR (*(RwReg *)0x42003414UL) /**< \brief (QSPI) Interrupt Enable Clear */
#define REG_QSPI_INTENSET (*(RwReg *)0x42003418UL) /**< \brief (QSPI) Interrupt Enable Set */
#define REG_QSPI_INTFLAG (*(RwReg *)0x4200341CUL) /**< \brief (QSPI) Interrupt Flag Status and Clear */
#define REG_QSPI_STATUS (*(RoReg *)0x42003420UL) /**< \brief (QSPI) Status Register */
#define REG_QSPI_INSTRADDR (*(RwReg *)0x42003430UL) /**< \brief (QSPI) Instruction Address */
#define REG_QSPI_INSTRCTRL (*(RwReg *)0x42003434UL) /**< \brief (QSPI) Instruction Code */
#define REG_QSPI_INSTRFRAME (*(RwReg *)0x42003438UL) /**< \brief (QSPI) Instruction Frame */
#define REG_QSPI_SCRAMBCTRL (*(RwReg *)0x42003440UL) /**< \brief (QSPI) Scrambling Mode */
#define REG_QSPI_SCRAMBKEY (*(WoReg *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for QSPI peripheral ========== */
#define QSPI_DMAC_ID_RX 83
#define QSPI_DMAC_ID_TX 84
#define QSPI_HADDR_MSB 23
#define QSPI_OCMS 1
#endif /* _SAMD51_QSPI_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RAMECC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_RAMECC_INSTANCE_
#define _SAMD51_RAMECC_INSTANCE_
/* ========== Register definition for RAMECC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RAMECC_INTENCLR (0x41020000) /**< \brief (RAMECC) Interrupt Enable Clear */
#define REG_RAMECC_INTENSET (0x41020001) /**< \brief (RAMECC) Interrupt Enable Set */
#define REG_RAMECC_INTFLAG (0x41020002) /**< \brief (RAMECC) Interrupt Flag */
#define REG_RAMECC_STATUS (0x41020003) /**< \brief (RAMECC) Status */
#define REG_RAMECC_ERRADDR (0x41020004) /**< \brief (RAMECC) Error Address */
#define REG_RAMECC_DBGCTRL (0x4102000F) /**< \brief (RAMECC) Debug Control */
#else
#define REG_RAMECC_INTENCLR (*(RwReg8 *)0x41020000UL) /**< \brief (RAMECC) Interrupt Enable Clear */
#define REG_RAMECC_INTENSET (*(RwReg8 *)0x41020001UL) /**< \brief (RAMECC) Interrupt Enable Set */
#define REG_RAMECC_INTFLAG (*(RwReg8 *)0x41020002UL) /**< \brief (RAMECC) Interrupt Flag */
#define REG_RAMECC_STATUS (*(RoReg8 *)0x41020003UL) /**< \brief (RAMECC) Status */
#define REG_RAMECC_ERRADDR (*(RoReg *)0x41020004UL) /**< \brief (RAMECC) Error Address */
#define REG_RAMECC_DBGCTRL (*(RwReg8 *)0x4102000FUL) /**< \brief (RAMECC) Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RAMECC peripheral ========== */
#define RAMECC_RAMADDR_BITS 13 // Number of RAM address bits
#define RAMECC_RAMBANK_NUM 4 // Number of RAM banks
#endif /* _SAMD51_RAMECC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RSTC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_RSTC_INSTANCE_
#define _SAMD51_RSTC_INSTANCE_
/* ========== Register definition for RSTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RSTC_RCAUSE (0x40000C00) /**< \brief (RSTC) Reset Cause */
#define REG_RSTC_BKUPEXIT (0x40000C02) /**< \brief (RSTC) Backup Exit Source */
#else
#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */
#define REG_RSTC_BKUPEXIT (*(RoReg8 *)0x40000C02UL) /**< \brief (RSTC) Backup Exit Source */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RSTC peripheral ========== */
#define RSTC_BACKUP_IMPLEMENTED 1
#define RSTC_HIB_IMPLEMENTED 1
#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line
#define RSTC_NVMRST_IMPLEMENTED 1
#endif /* _SAMD51_RSTC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RTC
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_RTC_INSTANCE_
#define _SAMD51_RTC_INSTANCE_
/* ========== Register definition for RTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */
#define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */
#define REG_RTC_GP0 (0x40002440) /**< \brief (RTC) General Purpose 0 */
#define REG_RTC_GP1 (0x40002444) /**< \brief (RTC) General Purpose 1 */
#define REG_RTC_GP2 (0x40002448) /**< \brief (RTC) General Purpose 2 */
#define REG_RTC_GP3 (0x4000244C) /**< \brief (RTC) General Purpose 3 */
#define REG_RTC_TAMPCTRL (0x40002460) /**< \brief (RTC) Tamper Control */
#define REG_RTC_TAMPID (0x40002468) /**< \brief (RTC) Tamper ID */
#define REG_RTC_BKUP0 (0x40002480) /**< \brief (RTC) Backup 0 */
#define REG_RTC_BKUP1 (0x40002484) /**< \brief (RTC) Backup 1 */
#define REG_RTC_BKUP2 (0x40002488) /**< \brief (RTC) Backup 2 */
#define REG_RTC_BKUP3 (0x4000248C) /**< \brief (RTC) Backup 3 */
#define REG_RTC_BKUP4 (0x40002490) /**< \brief (RTC) Backup 4 */
#define REG_RTC_BKUP5 (0x40002494) /**< \brief (RTC) Backup 5 */
#define REG_RTC_BKUP6 (0x40002498) /**< \brief (RTC) Backup 6 */
#define REG_RTC_BKUP7 (0x4000249C) /**< \brief (RTC) Backup 7 */
#define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */
#define REG_RTC_MODE0_CTRLB (0x40002402) /**< \brief (RTC) MODE0 Control B */
#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */
#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */
#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */
#define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */
#define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */
#define REG_RTC_MODE0_COMP1 (0x40002424) /**< \brief (RTC) MODE0 Compare 1 Value */
#define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE0 Timestamp */
#define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */
#define REG_RTC_MODE1_CTRLB (0x40002402) /**< \brief (RTC) MODE1 Control B */
#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */
#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */
#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */
#define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */
#define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */
#define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */
#define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */
#define REG_RTC_MODE1_COMP2 (0x40002424) /**< \brief (RTC) MODE1 Compare 2 Value */
#define REG_RTC_MODE1_COMP3 (0x40002426) /**< \brief (RTC) MODE1 Compare 3 Value */
#define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE1 Timestamp */
#define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */
#define REG_RTC_MODE2_CTRLB (0x40002402) /**< \brief (RTC) MODE2 Control B */
#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */
#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */
#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */
#define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */
#define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< \brief (RTC) MODE2 Timestamp */
#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
#define REG_RTC_MODE2_ALARM_ALARM1 (0x40002428) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
#define REG_RTC_MODE2_ALARM_MASK1 (0x4000242C) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
#else
#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */
#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */
#define REG_RTC_GP0 (*(RwReg *)0x40002440UL) /**< \brief (RTC) General Purpose 0 */
#define REG_RTC_GP1 (*(RwReg *)0x40002444UL) /**< \brief (RTC) General Purpose 1 */
#define REG_RTC_GP2 (*(RwReg *)0x40002448UL) /**< \brief (RTC) General Purpose 2 */
#define REG_RTC_GP3 (*(RwReg *)0x4000244CUL) /**< \brief (RTC) General Purpose 3 */
#define REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) /**< \brief (RTC) Tamper Control */
#define REG_RTC_TAMPID (*(RwReg *)0x40002468UL) /**< \brief (RTC) Tamper ID */
#define REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) /**< \brief (RTC) Backup 0 */
#define REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) /**< \brief (RTC) Backup 1 */
#define REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) /**< \brief (RTC) Backup 2 */
#define REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) /**< \brief (RTC) Backup 3 */
#define REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) /**< \brief (RTC) Backup 4 */
#define REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) /**< \brief (RTC) Backup 5 */
#define REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) /**< \brief (RTC) Backup 6 */
#define REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) /**< \brief (RTC) Backup 7 */
#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */
#define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */
#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */
#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */
#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */
#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */
#define REG_RTC_MODE0_COMP1 (*(RwReg *)0x40002424UL) /**< \brief (RTC) MODE0 Compare 1 Value */
#define REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE0 Timestamp */
#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */
#define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */
#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */
#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */
#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */
#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */
#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */
#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */
#define REG_RTC_MODE1_COMP2 (*(RwReg16*)0x40002424UL) /**< \brief (RTC) MODE1 Compare 2 Value */
#define REG_RTC_MODE1_COMP3 (*(RwReg16*)0x40002426UL) /**< \brief (RTC) MODE1 Compare 3 Value */
#define REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE1 Timestamp */
#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */
#define REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE2 Control B */
#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */
#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */
#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */
#define REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) /**< \brief (RTC) MODE2 Timestamp */
#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
#define REG_RTC_MODE2_ALARM_ALARM1 (*(RwReg *)0x40002428UL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Value */
#define REG_RTC_MODE2_ALARM_MASK1 (*(RwReg *)0x4000242CUL) /**< \brief (RTC) MODE2_ALARM Alarm 1 Mask */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RTC peripheral ========== */
#define RTC_DMAC_ID_TIMESTAMP 1 // DMA RTC timestamp trigger
#define RTC_GPR_NUM 4 // Number of General-Purpose Registers
#define RTC_NUM_OF_ALARMS 2 // Number of Alarms
#define RTC_NUM_OF_BKREGS 8 // Number of Backup Registers
#define RTC_NUM_OF_COMP16 4 // Number of 16-bit Comparators
#define RTC_NUM_OF_COMP32 2 // Number of 32-bit Comparators
#define RTC_NUM_OF_TAMPERS 5 // Number of Tamper Inputs
#define RTC_PER_NUM 8 // Number of Periodic Intervals
#endif /* _SAMD51_RTC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SDHC0
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_SDHC0_INSTANCE_
#define _SAMD51_SDHC0_INSTANCE_
/* ========== Register definition for SDHC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SDHC0_SSAR (0x45000000) /**< \brief (SDHC0) SDMA System Address / Argument 2 */
#define REG_SDHC0_BSR (0x45000004) /**< \brief (SDHC0) Block Size */
#define REG_SDHC0_BCR (0x45000006) /**< \brief (SDHC0) Block Count */
#define REG_SDHC0_ARG1R (0x45000008) /**< \brief (SDHC0) Argument 1 */
#define REG_SDHC0_TMR (0x4500000C) /**< \brief (SDHC0) Transfer Mode */
#define REG_SDHC0_CR (0x4500000E) /**< \brief (SDHC0) Command */
#define REG_SDHC0_RR0 (0x45000010) /**< \brief (SDHC0) Response 0 */
#define REG_SDHC0_RR1 (0x45000014) /**< \brief (SDHC0) Response 1 */
#define REG_SDHC0_RR2 (0x45000018) /**< \brief (SDHC0) Response 2 */
#define REG_SDHC0_RR3 (0x4500001C) /**< \brief (SDHC0) Response 3 */
#define REG_SDHC0_BDPR (0x45000020) /**< \brief (SDHC0) Buffer Data Port */
#define REG_SDHC0_PSR (0x45000024) /**< \brief (SDHC0) Present State */
#define REG_SDHC0_HC1R (0x45000028) /**< \brief (SDHC0) Host Control 1 */
#define REG_SDHC0_PCR (0x45000029) /**< \brief (SDHC0) Power Control */
#define REG_SDHC0_BGCR (0x4500002A) /**< \brief (SDHC0) Block Gap Control */
#define REG_SDHC0_WCR (0x4500002B) /**< \brief (SDHC0) Wakeup Control */
#define REG_SDHC0_CCR (0x4500002C) /**< \brief (SDHC0) Clock Control */
#define REG_SDHC0_TCR (0x4500002E) /**< \brief (SDHC0) Timeout Control */
#define REG_SDHC0_SRR (0x4500002F) /**< \brief (SDHC0) Software Reset */
#define REG_SDHC0_NISTR (0x45000030) /**< \brief (SDHC0) Normal Interrupt Status */
#define REG_SDHC0_EISTR (0x45000032) /**< \brief (SDHC0) Error Interrupt Status */
#define REG_SDHC0_NISTER (0x45000034) /**< \brief (SDHC0) Normal Interrupt Status Enable */
#define REG_SDHC0_EISTER (0x45000036) /**< \brief (SDHC0) Error Interrupt Status Enable */
#define REG_SDHC0_NISIER (0x45000038) /**< \brief (SDHC0) Normal Interrupt Signal Enable */
#define REG_SDHC0_EISIER (0x4500003A) /**< \brief (SDHC0) Error Interrupt Signal Enable */
#define REG_SDHC0_ACESR (0x4500003C) /**< \brief (SDHC0) Auto CMD Error Status */
#define REG_SDHC0_HC2R (0x4500003E) /**< \brief (SDHC0) Host Control 2 */
#define REG_SDHC0_CA0R (0x45000040) /**< \brief (SDHC0) Capabilities 0 */
#define REG_SDHC0_CA1R (0x45000044) /**< \brief (SDHC0) Capabilities 1 */
#define REG_SDHC0_MCCAR (0x45000048) /**< \brief (SDHC0) Maximum Current Capabilities */
#define REG_SDHC0_FERACES (0x45000050) /**< \brief (SDHC0) Force Event for Auto CMD Error Status */
#define REG_SDHC0_FEREIS (0x45000052) /**< \brief (SDHC0) Force Event for Error Interrupt Status */
#define REG_SDHC0_AESR (0x45000054) /**< \brief (SDHC0) ADMA Error Status */
#define REG_SDHC0_ASAR0 (0x45000058) /**< \brief (SDHC0) ADMA System Address 0 */
#define REG_SDHC0_PVR0 (0x45000060) /**< \brief (SDHC0) Preset Value 0 */
#define REG_SDHC0_PVR1 (0x45000062) /**< \brief (SDHC0) Preset Value 1 */
#define REG_SDHC0_PVR2 (0x45000064) /**< \brief (SDHC0) Preset Value 2 */
#define REG_SDHC0_PVR3 (0x45000066) /**< \brief (SDHC0) Preset Value 3 */
#define REG_SDHC0_PVR4 (0x45000068) /**< \brief (SDHC0) Preset Value 4 */
#define REG_SDHC0_PVR5 (0x4500006A) /**< \brief (SDHC0) Preset Value 5 */
#define REG_SDHC0_PVR6 (0x4500006C) /**< \brief (SDHC0) Preset Value 6 */
#define REG_SDHC0_PVR7 (0x4500006E) /**< \brief (SDHC0) Preset Value 7 */
#define REG_SDHC0_SISR (0x450000FC) /**< \brief (SDHC0) Slot Interrupt Status */
#define REG_SDHC0_HCVR (0x450000FE) /**< \brief (SDHC0) Host Controller Version */
#define REG_SDHC0_MC1R (0x45000204) /**< \brief (SDHC0) MMC Control 1 */
#define REG_SDHC0_MC2R (0x45000205) /**< \brief (SDHC0) MMC Control 2 */
#define REG_SDHC0_ACR (0x45000208) /**< \brief (SDHC0) AHB Control */
#define REG_SDHC0_CC2R (0x4500020C) /**< \brief (SDHC0) Clock Control 2 */
#define REG_SDHC0_CACR (0x45000230) /**< \brief (SDHC0) Capabilities Control */
#define REG_SDHC0_DBGR (0x45000234) /**< \brief (SDHC0) Debug */
#else
#define REG_SDHC0_SSAR (*(RwReg *)0x45000000UL) /**< \brief (SDHC0) SDMA System Address / Argument 2 */
#define REG_SDHC0_BSR (*(RwReg16*)0x45000004UL) /**< \brief (SDHC0) Block Size */
#define REG_SDHC0_BCR (*(RwReg16*)0x45000006UL) /**< \brief (SDHC0) Block Count */
#define REG_SDHC0_ARG1R (*(RwReg *)0x45000008UL) /**< \brief (SDHC0) Argument 1 */
#define REG_SDHC0_TMR (*(RwReg16*)0x4500000CUL) /**< \brief (SDHC0) Transfer Mode */
#define REG_SDHC0_CR (*(RwReg16*)0x4500000EUL) /**< \brief (SDHC0) Command */
#define REG_SDHC0_RR0 (*(RoReg *)0x45000010UL) /**< \brief (SDHC0) Response 0 */
#define REG_SDHC0_RR1 (*(RoReg *)0x45000014UL) /**< \brief (SDHC0) Response 1 */
#define REG_SDHC0_RR2 (*(RoReg *)0x45000018UL) /**< \brief (SDHC0) Response 2 */
#define REG_SDHC0_RR3 (*(RoReg *)0x4500001CUL) /**< \brief (SDHC0) Response 3 */
#define REG_SDHC0_BDPR (*(RwReg *)0x45000020UL) /**< \brief (SDHC0) Buffer Data Port */
#define REG_SDHC0_PSR (*(RoReg *)0x45000024UL) /**< \brief (SDHC0) Present State */
#define REG_SDHC0_HC1R (*(RwReg8 *)0x45000028UL) /**< \brief (SDHC0) Host Control 1 */
#define REG_SDHC0_PCR (*(RwReg8 *)0x45000029UL) /**< \brief (SDHC0) Power Control */
#define REG_SDHC0_BGCR (*(RwReg8 *)0x4500002AUL) /**< \brief (SDHC0) Block Gap Control */
#define REG_SDHC0_WCR (*(RwReg8 *)0x4500002BUL) /**< \brief (SDHC0) Wakeup Control */
#define REG_SDHC0_CCR (*(RwReg16*)0x4500002CUL) /**< \brief (SDHC0) Clock Control */
#define REG_SDHC0_TCR (*(RwReg8 *)0x4500002EUL) /**< \brief (SDHC0) Timeout Control */
#define REG_SDHC0_SRR (*(RwReg8 *)0x4500002FUL) /**< \brief (SDHC0) Software Reset */
#define REG_SDHC0_NISTR (*(RwReg16*)0x45000030UL) /**< \brief (SDHC0) Normal Interrupt Status */
#define REG_SDHC0_EISTR (*(RwReg16*)0x45000032UL) /**< \brief (SDHC0) Error Interrupt Status */
#define REG_SDHC0_NISTER (*(RwReg16*)0x45000034UL) /**< \brief (SDHC0) Normal Interrupt Status Enable */
#define REG_SDHC0_EISTER (*(RwReg16*)0x45000036UL) /**< \brief (SDHC0) Error Interrupt Status Enable */
#define REG_SDHC0_NISIER (*(RwReg16*)0x45000038UL) /**< \brief (SDHC0) Normal Interrupt Signal Enable */
#define REG_SDHC0_EISIER (*(RwReg16*)0x4500003AUL) /**< \brief (SDHC0) Error Interrupt Signal Enable */
#define REG_SDHC0_ACESR (*(RoReg16*)0x4500003CUL) /**< \brief (SDHC0) Auto CMD Error Status */
#define REG_SDHC0_HC2R (*(RwReg16*)0x4500003EUL) /**< \brief (SDHC0) Host Control 2 */
#define REG_SDHC0_CA0R (*(RoReg *)0x45000040UL) /**< \brief (SDHC0) Capabilities 0 */
#define REG_SDHC0_CA1R (*(RoReg *)0x45000044UL) /**< \brief (SDHC0) Capabilities 1 */
#define REG_SDHC0_MCCAR (*(RoReg *)0x45000048UL) /**< \brief (SDHC0) Maximum Current Capabilities */
#define REG_SDHC0_FERACES (*(WoReg16*)0x45000050UL) /**< \brief (SDHC0) Force Event for Auto CMD Error Status */
#define REG_SDHC0_FEREIS (*(WoReg16*)0x45000052UL) /**< \brief (SDHC0) Force Event for Error Interrupt Status */
#define REG_SDHC0_AESR (*(RoReg8 *)0x45000054UL) /**< \brief (SDHC0) ADMA Error Status */
#define REG_SDHC0_ASAR0 (*(RwReg *)0x45000058UL) /**< \brief (SDHC0) ADMA System Address 0 */
#define REG_SDHC0_PVR0 (*(RwReg16*)0x45000060UL) /**< \brief (SDHC0) Preset Value 0 */
#define REG_SDHC0_PVR1 (*(RwReg16*)0x45000062UL) /**< \brief (SDHC0) Preset Value 1 */
#define REG_SDHC0_PVR2 (*(RwReg16*)0x45000064UL) /**< \brief (SDHC0) Preset Value 2 */
#define REG_SDHC0_PVR3 (*(RwReg16*)0x45000066UL) /**< \brief (SDHC0) Preset Value 3 */
#define REG_SDHC0_PVR4 (*(RwReg16*)0x45000068UL) /**< \brief (SDHC0) Preset Value 4 */
#define REG_SDHC0_PVR5 (*(RwReg16*)0x4500006AUL) /**< \brief (SDHC0) Preset Value 5 */
#define REG_SDHC0_PVR6 (*(RwReg16*)0x4500006CUL) /**< \brief (SDHC0) Preset Value 6 */
#define REG_SDHC0_PVR7 (*(RwReg16*)0x4500006EUL) /**< \brief (SDHC0) Preset Value 7 */
#define REG_SDHC0_SISR (*(RoReg16*)0x450000FCUL) /**< \brief (SDHC0) Slot Interrupt Status */
#define REG_SDHC0_HCVR (*(RoReg16*)0x450000FEUL) /**< \brief (SDHC0) Host Controller Version */
#define REG_SDHC0_MC1R (*(RwReg8 *)0x45000204UL) /**< \brief (SDHC0) MMC Control 1 */
#define REG_SDHC0_MC2R (*(WoReg8 *)0x45000205UL) /**< \brief (SDHC0) MMC Control 2 */
#define REG_SDHC0_ACR (*(RwReg *)0x45000208UL) /**< \brief (SDHC0) AHB Control */
#define REG_SDHC0_CC2R (*(RwReg *)0x4500020CUL) /**< \brief (SDHC0) Clock Control 2 */
#define REG_SDHC0_CACR (*(RwReg *)0x45000230UL) /**< \brief (SDHC0) Capabilities Control */
#define REG_SDHC0_DBGR (*(RwReg8 *)0x45000234UL) /**< \brief (SDHC0) Debug */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SDHC0 peripheral ========== */
#define SDHC0_CARD_DATA_SIZE 4
#define SDHC0_CLK_AHB_ID 15
#define SDHC0_GCLK_ID 45
#define SDHC0_GCLK_ID_SLOW 3
#define SDHC0_NB_OF_DEVICES 1
#define SDHC0_NB_REG_PVR 8
#define SDHC0_NB_REG_RR 4
#endif /* _SAMD51_SDHC0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SDHC1
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_SDHC1_INSTANCE_
#define _SAMD51_SDHC1_INSTANCE_
/* ========== Register definition for SDHC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SDHC1_SSAR (0x46000000) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
#define REG_SDHC1_BSR (0x46000004) /**< \brief (SDHC1) Block Size */
#define REG_SDHC1_BCR (0x46000006) /**< \brief (SDHC1) Block Count */
#define REG_SDHC1_ARG1R (0x46000008) /**< \brief (SDHC1) Argument 1 */
#define REG_SDHC1_TMR (0x4600000C) /**< \brief (SDHC1) Transfer Mode */
#define REG_SDHC1_CR (0x4600000E) /**< \brief (SDHC1) Command */
#define REG_SDHC1_RR0 (0x46000010) /**< \brief (SDHC1) Response 0 */
#define REG_SDHC1_RR1 (0x46000014) /**< \brief (SDHC1) Response 1 */
#define REG_SDHC1_RR2 (0x46000018) /**< \brief (SDHC1) Response 2 */
#define REG_SDHC1_RR3 (0x4600001C) /**< \brief (SDHC1) Response 3 */
#define REG_SDHC1_BDPR (0x46000020) /**< \brief (SDHC1) Buffer Data Port */
#define REG_SDHC1_PSR (0x46000024) /**< \brief (SDHC1) Present State */
#define REG_SDHC1_HC1R (0x46000028) /**< \brief (SDHC1) Host Control 1 */
#define REG_SDHC1_PCR (0x46000029) /**< \brief (SDHC1) Power Control */
#define REG_SDHC1_BGCR (0x4600002A) /**< \brief (SDHC1) Block Gap Control */
#define REG_SDHC1_WCR (0x4600002B) /**< \brief (SDHC1) Wakeup Control */
#define REG_SDHC1_CCR (0x4600002C) /**< \brief (SDHC1) Clock Control */
#define REG_SDHC1_TCR (0x4600002E) /**< \brief (SDHC1) Timeout Control */
#define REG_SDHC1_SRR (0x4600002F) /**< \brief (SDHC1) Software Reset */
#define REG_SDHC1_NISTR (0x46000030) /**< \brief (SDHC1) Normal Interrupt Status */
#define REG_SDHC1_EISTR (0x46000032) /**< \brief (SDHC1) Error Interrupt Status */
#define REG_SDHC1_NISTER (0x46000034) /**< \brief (SDHC1) Normal Interrupt Status Enable */
#define REG_SDHC1_EISTER (0x46000036) /**< \brief (SDHC1) Error Interrupt Status Enable */
#define REG_SDHC1_NISIER (0x46000038) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
#define REG_SDHC1_EISIER (0x4600003A) /**< \brief (SDHC1) Error Interrupt Signal Enable */
#define REG_SDHC1_ACESR (0x4600003C) /**< \brief (SDHC1) Auto CMD Error Status */
#define REG_SDHC1_HC2R (0x4600003E) /**< \brief (SDHC1) Host Control 2 */
#define REG_SDHC1_CA0R (0x46000040) /**< \brief (SDHC1) Capabilities 0 */
#define REG_SDHC1_CA1R (0x46000044) /**< \brief (SDHC1) Capabilities 1 */
#define REG_SDHC1_MCCAR (0x46000048) /**< \brief (SDHC1) Maximum Current Capabilities */
#define REG_SDHC1_FERACES (0x46000050) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
#define REG_SDHC1_FEREIS (0x46000052) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
#define REG_SDHC1_AESR (0x46000054) /**< \brief (SDHC1) ADMA Error Status */
#define REG_SDHC1_ASAR0 (0x46000058) /**< \brief (SDHC1) ADMA System Address 0 */
#define REG_SDHC1_PVR0 (0x46000060) /**< \brief (SDHC1) Preset Value 0 */
#define REG_SDHC1_PVR1 (0x46000062) /**< \brief (SDHC1) Preset Value 1 */
#define REG_SDHC1_PVR2 (0x46000064) /**< \brief (SDHC1) Preset Value 2 */
#define REG_SDHC1_PVR3 (0x46000066) /**< \brief (SDHC1) Preset Value 3 */
#define REG_SDHC1_PVR4 (0x46000068) /**< \brief (SDHC1) Preset Value 4 */
#define REG_SDHC1_PVR5 (0x4600006A) /**< \brief (SDHC1) Preset Value 5 */
#define REG_SDHC1_PVR6 (0x4600006C) /**< \brief (SDHC1) Preset Value 6 */
#define REG_SDHC1_PVR7 (0x4600006E) /**< \brief (SDHC1) Preset Value 7 */
#define REG_SDHC1_SISR (0x460000FC) /**< \brief (SDHC1) Slot Interrupt Status */
#define REG_SDHC1_HCVR (0x460000FE) /**< \brief (SDHC1) Host Controller Version */
#define REG_SDHC1_MC1R (0x46000204) /**< \brief (SDHC1) MMC Control 1 */
#define REG_SDHC1_MC2R (0x46000205) /**< \brief (SDHC1) MMC Control 2 */
#define REG_SDHC1_ACR (0x46000208) /**< \brief (SDHC1) AHB Control */
#define REG_SDHC1_CC2R (0x4600020C) /**< \brief (SDHC1) Clock Control 2 */
#define REG_SDHC1_CACR (0x46000230) /**< \brief (SDHC1) Capabilities Control */
#define REG_SDHC1_DBGR (0x46000234) /**< \brief (SDHC1) Debug */
#else
#define REG_SDHC1_SSAR (*(RwReg *)0x46000000UL) /**< \brief (SDHC1) SDMA System Address / Argument 2 */
#define REG_SDHC1_BSR (*(RwReg16*)0x46000004UL) /**< \brief (SDHC1) Block Size */
#define REG_SDHC1_BCR (*(RwReg16*)0x46000006UL) /**< \brief (SDHC1) Block Count */
#define REG_SDHC1_ARG1R (*(RwReg *)0x46000008UL) /**< \brief (SDHC1) Argument 1 */
#define REG_SDHC1_TMR (*(RwReg16*)0x4600000CUL) /**< \brief (SDHC1) Transfer Mode */
#define REG_SDHC1_CR (*(RwReg16*)0x4600000EUL) /**< \brief (SDHC1) Command */
#define REG_SDHC1_RR0 (*(RoReg *)0x46000010UL) /**< \brief (SDHC1) Response 0 */
#define REG_SDHC1_RR1 (*(RoReg *)0x46000014UL) /**< \brief (SDHC1) Response 1 */
#define REG_SDHC1_RR2 (*(RoReg *)0x46000018UL) /**< \brief (SDHC1) Response 2 */
#define REG_SDHC1_RR3 (*(RoReg *)0x4600001CUL) /**< \brief (SDHC1) Response 3 */
#define REG_SDHC1_BDPR (*(RwReg *)0x46000020UL) /**< \brief (SDHC1) Buffer Data Port */
#define REG_SDHC1_PSR (*(RoReg *)0x46000024UL) /**< \brief (SDHC1) Present State */
#define REG_SDHC1_HC1R (*(RwReg8 *)0x46000028UL) /**< \brief (SDHC1) Host Control 1 */
#define REG_SDHC1_PCR (*(RwReg8 *)0x46000029UL) /**< \brief (SDHC1) Power Control */
#define REG_SDHC1_BGCR (*(RwReg8 *)0x4600002AUL) /**< \brief (SDHC1) Block Gap Control */
#define REG_SDHC1_WCR (*(RwReg8 *)0x4600002BUL) /**< \brief (SDHC1) Wakeup Control */
#define REG_SDHC1_CCR (*(RwReg16*)0x4600002CUL) /**< \brief (SDHC1) Clock Control */
#define REG_SDHC1_TCR (*(RwReg8 *)0x4600002EUL) /**< \brief (SDHC1) Timeout Control */
#define REG_SDHC1_SRR (*(RwReg8 *)0x4600002FUL) /**< \brief (SDHC1) Software Reset */
#define REG_SDHC1_NISTR (*(RwReg16*)0x46000030UL) /**< \brief (SDHC1) Normal Interrupt Status */
#define REG_SDHC1_EISTR (*(RwReg16*)0x46000032UL) /**< \brief (SDHC1) Error Interrupt Status */
#define REG_SDHC1_NISTER (*(RwReg16*)0x46000034UL) /**< \brief (SDHC1) Normal Interrupt Status Enable */
#define REG_SDHC1_EISTER (*(RwReg16*)0x46000036UL) /**< \brief (SDHC1) Error Interrupt Status Enable */
#define REG_SDHC1_NISIER (*(RwReg16*)0x46000038UL) /**< \brief (SDHC1) Normal Interrupt Signal Enable */
#define REG_SDHC1_EISIER (*(RwReg16*)0x4600003AUL) /**< \brief (SDHC1) Error Interrupt Signal Enable */
#define REG_SDHC1_ACESR (*(RoReg16*)0x4600003CUL) /**< \brief (SDHC1) Auto CMD Error Status */
#define REG_SDHC1_HC2R (*(RwReg16*)0x4600003EUL) /**< \brief (SDHC1) Host Control 2 */
#define REG_SDHC1_CA0R (*(RoReg *)0x46000040UL) /**< \brief (SDHC1) Capabilities 0 */
#define REG_SDHC1_CA1R (*(RoReg *)0x46000044UL) /**< \brief (SDHC1) Capabilities 1 */
#define REG_SDHC1_MCCAR (*(RoReg *)0x46000048UL) /**< \brief (SDHC1) Maximum Current Capabilities */
#define REG_SDHC1_FERACES (*(WoReg16*)0x46000050UL) /**< \brief (SDHC1) Force Event for Auto CMD Error Status */
#define REG_SDHC1_FEREIS (*(WoReg16*)0x46000052UL) /**< \brief (SDHC1) Force Event for Error Interrupt Status */
#define REG_SDHC1_AESR (*(RoReg8 *)0x46000054UL) /**< \brief (SDHC1) ADMA Error Status */
#define REG_SDHC1_ASAR0 (*(RwReg *)0x46000058UL) /**< \brief (SDHC1) ADMA System Address 0 */
#define REG_SDHC1_PVR0 (*(RwReg16*)0x46000060UL) /**< \brief (SDHC1) Preset Value 0 */
#define REG_SDHC1_PVR1 (*(RwReg16*)0x46000062UL) /**< \brief (SDHC1) Preset Value 1 */
#define REG_SDHC1_PVR2 (*(RwReg16*)0x46000064UL) /**< \brief (SDHC1) Preset Value 2 */
#define REG_SDHC1_PVR3 (*(RwReg16*)0x46000066UL) /**< \brief (SDHC1) Preset Value 3 */
#define REG_SDHC1_PVR4 (*(RwReg16*)0x46000068UL) /**< \brief (SDHC1) Preset Value 4 */
#define REG_SDHC1_PVR5 (*(RwReg16*)0x4600006AUL) /**< \brief (SDHC1) Preset Value 5 */
#define REG_SDHC1_PVR6 (*(RwReg16*)0x4600006CUL) /**< \brief (SDHC1) Preset Value 6 */
#define REG_SDHC1_PVR7 (*(RwReg16*)0x4600006EUL) /**< \brief (SDHC1) Preset Value 7 */
#define REG_SDHC1_SISR (*(RoReg16*)0x460000FCUL) /**< \brief (SDHC1) Slot Interrupt Status */
#define REG_SDHC1_HCVR (*(RoReg16*)0x460000FEUL) /**< \brief (SDHC1) Host Controller Version */
#define REG_SDHC1_MC1R (*(RwReg8 *)0x46000204UL) /**< \brief (SDHC1) MMC Control 1 */
#define REG_SDHC1_MC2R (*(WoReg8 *)0x46000205UL) /**< \brief (SDHC1) MMC Control 2 */
#define REG_SDHC1_ACR (*(RwReg *)0x46000208UL) /**< \brief (SDHC1) AHB Control */
#define REG_SDHC1_CC2R (*(RwReg *)0x4600020CUL) /**< \brief (SDHC1) Clock Control 2 */
#define REG_SDHC1_CACR (*(RwReg *)0x46000230UL) /**< \brief (SDHC1) Capabilities Control */
#define REG_SDHC1_DBGR (*(RwReg8 *)0x46000234UL) /**< \brief (SDHC1) Debug */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SDHC1 peripheral ========== */
#define SDHC1_CARD_DATA_SIZE 4
#define SDHC1_CLK_AHB_ID 16
#define SDHC1_GCLK_ID 46
#define SDHC1_GCLK_ID_SLOW 3
#define SDHC1_NB_OF_DEVICES 1
#define SDHC1_NB_REG_PVR 8
#define SDHC1_NB_REG_RR 4
#endif /* _SAMD51_SDHC1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SERCOM0
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_SERCOM0_INSTANCE_
#define _SAMD51_SERCOM0_INSTANCE_
/* ========== Register definition for SERCOM0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM0_I2CM_CTRLA (0x40003000) /**< \brief (SERCOM0) I2CM Control A */
#define REG_SERCOM0_I2CM_CTRLB (0x40003004) /**< \brief (SERCOM0) I2CM Control B */
#define REG_SERCOM0_I2CM_CTRLC (0x40003008) /**< \brief (SERCOM0) I2CM Control C */
#define REG_SERCOM0_I2CM_BAUD (0x4000300C) /**< \brief (SERCOM0) I2CM Baud Rate */
#define REG_SERCOM0_I2CM_INTENCLR (0x40003014) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
#define REG_SERCOM0_I2CM_INTENSET (0x40003016) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
#define REG_SERCOM0_I2CM_INTFLAG (0x40003018) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CM_STATUS (0x4000301A) /**< \brief (SERCOM0) I2CM Status */
#define REG_SERCOM0_I2CM_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) I2CM Synchronization Busy */
#define REG_SERCOM0_I2CM_ADDR (0x40003024) /**< \brief (SERCOM0) I2CM Address */
#define REG_SERCOM0_I2CM_DATA (0x40003028) /**< \brief (SERCOM0) I2CM Data */
#define REG_SERCOM0_I2CM_DBGCTRL (0x40003030) /**< \brief (SERCOM0) I2CM Debug Control */
#define REG_SERCOM0_I2CS_CTRLA (0x40003000) /**< \brief (SERCOM0) I2CS Control A */
#define REG_SERCOM0_I2CS_CTRLB (0x40003004) /**< \brief (SERCOM0) I2CS Control B */
#define REG_SERCOM0_I2CS_CTRLC (0x40003008) /**< \brief (SERCOM0) I2CS Control C */
#define REG_SERCOM0_I2CS_INTENCLR (0x40003014) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
#define REG_SERCOM0_I2CS_INTENSET (0x40003016) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
#define REG_SERCOM0_I2CS_INTFLAG (0x40003018) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CS_STATUS (0x4000301A) /**< \brief (SERCOM0) I2CS Status */
#define REG_SERCOM0_I2CS_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) I2CS Synchronization Busy */
#define REG_SERCOM0_I2CS_LENGTH (0x40003022) /**< \brief (SERCOM0) I2CS Length */
#define REG_SERCOM0_I2CS_ADDR (0x40003024) /**< \brief (SERCOM0) I2CS Address */
#define REG_SERCOM0_I2CS_DATA (0x40003028) /**< \brief (SERCOM0) I2CS Data */
#define REG_SERCOM0_SPI_CTRLA (0x40003000) /**< \brief (SERCOM0) SPI Control A */
#define REG_SERCOM0_SPI_CTRLB (0x40003004) /**< \brief (SERCOM0) SPI Control B */
#define REG_SERCOM0_SPI_CTRLC (0x40003008) /**< \brief (SERCOM0) SPI Control C */
#define REG_SERCOM0_SPI_BAUD (0x4000300C) /**< \brief (SERCOM0) SPI Baud Rate */
#define REG_SERCOM0_SPI_INTENCLR (0x40003014) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
#define REG_SERCOM0_SPI_INTENSET (0x40003016) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
#define REG_SERCOM0_SPI_INTFLAG (0x40003018) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM0_SPI_STATUS (0x4000301A) /**< \brief (SERCOM0) SPI Status */
#define REG_SERCOM0_SPI_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) SPI Synchronization Busy */
#define REG_SERCOM0_SPI_LENGTH (0x40003022) /**< \brief (SERCOM0) SPI Length */
#define REG_SERCOM0_SPI_ADDR (0x40003024) /**< \brief (SERCOM0) SPI Address */
#define REG_SERCOM0_SPI_DATA (0x40003028) /**< \brief (SERCOM0) SPI Data */
#define REG_SERCOM0_SPI_DBGCTRL (0x40003030) /**< \brief (SERCOM0) SPI Debug Control */
#define REG_SERCOM0_USART_CTRLA (0x40003000) /**< \brief (SERCOM0) USART Control A */
#define REG_SERCOM0_USART_CTRLB (0x40003004) /**< \brief (SERCOM0) USART Control B */
#define REG_SERCOM0_USART_CTRLC (0x40003008) /**< \brief (SERCOM0) USART Control C */
#define REG_SERCOM0_USART_BAUD (0x4000300C) /**< \brief (SERCOM0) USART Baud Rate */
#define REG_SERCOM0_USART_RXPL (0x4000300E) /**< \brief (SERCOM0) USART Receive Pulse Length */
#define REG_SERCOM0_USART_INTENCLR (0x40003014) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
#define REG_SERCOM0_USART_INTENSET (0x40003016) /**< \brief (SERCOM0) USART Interrupt Enable Set */
#define REG_SERCOM0_USART_INTFLAG (0x40003018) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
#define REG_SERCOM0_USART_STATUS (0x4000301A) /**< \brief (SERCOM0) USART Status */
#define REG_SERCOM0_USART_SYNCBUSY (0x4000301C) /**< \brief (SERCOM0) USART Synchronization Busy */
#define REG_SERCOM0_USART_RXERRCNT (0x40003020) /**< \brief (SERCOM0) USART Receive Error Count */
#define REG_SERCOM0_USART_LENGTH (0x40003022) /**< \brief (SERCOM0) USART Length */
#define REG_SERCOM0_USART_DATA (0x40003028) /**< \brief (SERCOM0) USART Data */
#define REG_SERCOM0_USART_DBGCTRL (0x40003030) /**< \brief (SERCOM0) USART Debug Control */
#else
#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) I2CM Control A */
#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) I2CM Control B */
#define REG_SERCOM0_I2CM_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) I2CM Control C */
#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4000300CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CM Status */
#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */
#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) I2CM Address */
#define REG_SERCOM0_I2CM_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) I2CM Data */
#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) I2CM Debug Control */
#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) I2CS Control A */
#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) I2CS Control B */
#define REG_SERCOM0_I2CS_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) I2CS Control C */
#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) I2CS Status */
#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */
#define REG_SERCOM0_I2CS_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) I2CS Length */
#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) I2CS Address */
#define REG_SERCOM0_I2CS_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) I2CS Data */
#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) SPI Control A */
#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) SPI Control B */
#define REG_SERCOM0_SPI_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) SPI Control C */
#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4000300CUL) /**< \brief (SERCOM0) SPI Baud Rate */
#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) SPI Status */
#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */
#define REG_SERCOM0_SPI_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) SPI Length */
#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x40003024UL) /**< \brief (SERCOM0) SPI Address */
#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) SPI Data */
#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) SPI Debug Control */
#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x40003000UL) /**< \brief (SERCOM0) USART Control A */
#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x40003004UL) /**< \brief (SERCOM0) USART Control B */
#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x40003008UL) /**< \brief (SERCOM0) USART Control C */
#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4000300CUL) /**< \brief (SERCOM0) USART Baud Rate */
#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4000300EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x40003014UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x40003016UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x40003018UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4000301AUL) /**< \brief (SERCOM0) USART Status */
#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4000301CUL) /**< \brief (SERCOM0) USART Synchronization Busy */
#define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x40003020UL) /**< \brief (SERCOM0) USART Receive Error Count */
#define REG_SERCOM0_USART_LENGTH (*(RwReg16*)0x40003022UL) /**< \brief (SERCOM0) USART Length */
#define REG_SERCOM0_USART_DATA (*(RwReg *)0x40003028UL) /**< \brief (SERCOM0) USART Data */
#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x40003030UL) /**< \brief (SERCOM0) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM0 peripheral ========== */
#define SERCOM0_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
#define SERCOM0_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
#define SERCOM0_DMA 1 // DMA support implemented?
#define SERCOM0_DMAC_ID_RX 4 // Index of DMA RX trigger
#define SERCOM0_DMAC_ID_TX 5 // Index of DMA TX trigger
#define SERCOM0_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
#define SERCOM0_GCLK_ID_CORE 7
#define SERCOM0_GCLK_ID_SLOW 3
#define SERCOM0_INT_MSB 6
#define SERCOM0_PMSB 3
#define SERCOM0_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM0_SE_CNT 1 // SE counter included?
#define SERCOM0_SPI 1 // SPI mode implemented?
#define SERCOM0_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
#define SERCOM0_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
#define SERCOM0_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM0_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM0_TTBIT_EXTENSION 1 // 32-bit extension implemented?
#define SERCOM0_TWIM 1 // TWI Master mode implemented?
#define SERCOM0_TWIS 1 // TWI Slave mode implemented?
#define SERCOM0_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
#define SERCOM0_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
#define SERCOM0_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
#define SERCOM0_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
#define SERCOM0_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
#define SERCOM0_TWI_FASTMP 1 // TWI fast mode plus implemented?
#define SERCOM0_TWI_HSMODE 1 // USART mode implemented?
#define SERCOM0_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
#define SERCOM0_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
#define SERCOM0_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM0_USART 1 // USART mode implemented?
#define SERCOM0_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM0_USART_COLDET 1 // USART collision detection implemented?
#define SERCOM0_USART_FLOW_CTRL 1 // USART flow control implemented?
#define SERCOM0_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
#define SERCOM0_USART_IRDA 1 // USART IrDA implemented?
#define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented?
#define SERCOM0_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
#define SERCOM0_USART_RS485 1 // USART RS485 mode implemented?
#define SERCOM0_USART_SAMPA_EXT 1 // USART sample adjust implemented?
#define SERCOM0_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
#endif /* _SAMD51_SERCOM0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SERCOM1
*
* Copyright (c) 2017 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMD51_SERCOM1_INSTANCE_
#define _SAMD51_SERCOM1_INSTANCE_
/* ========== Register definition for SERCOM1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM1_I2CM_CTRLA (0x40003400) /**< \brief (SERCOM1) I2CM Control A */
#define REG_SERCOM1_I2CM_CTRLB (0x40003404) /**< \brief (SERCOM1) I2CM Control B */
#define REG_SERCOM1_I2CM_CTRLC (0x40003408) /**< \brief (SERCOM1) I2CM Control C */
#define REG_SERCOM1_I2CM_BAUD (0x4000340C) /**< \brief (SERCOM1) I2CM Baud Rate */
#define REG_SERCOM1_I2CM_INTENCLR (0x40003414) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
#define REG_SERCOM1_I2CM_INTENSET (0x40003416) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
#define REG_SERCOM1_I2CM_INTFLAG (0x40003418) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CM_STATUS (0x4000341A) /**< \brief (SERCOM1) I2CM Status */
#define REG_SERCOM1_I2CM_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) I2CM Synchronization Busy */
#define REG_SERCOM1_I2CM_ADDR (0x40003424) /**< \brief (SERCOM1) I2CM Address */
#define REG_SERCOM1_I2CM_DATA (0x40003428) /**< \brief (SERCOM1) I2CM Data */
#define REG_SERCOM1_I2CM_DBGCTRL (0x40003430) /**< \brief (SERCOM1) I2CM Debug Control */
#define REG_SERCOM1_I2CS_CTRLA (0x40003400) /**< \brief (SERCOM1) I2CS Control A */
#define REG_SERCOM1_I2CS_CTRLB (0x40003404) /**< \brief (SERCOM1) I2CS Control B */
#define REG_SERCOM1_I2CS_CTRLC (0x40003408) /**< \brief (SERCOM1) I2CS Control C */
#define REG_SERCOM1_I2CS_INTENCLR (0x40003414) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
#define REG_SERCOM1_I2CS_INTENSET (0x40003416) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
#define REG_SERCOM1_I2CS_INTFLAG (0x40003418) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CS_STATUS (0x4000341A) /**< \brief (SERCOM1) I2CS Status */
#define REG_SERCOM1_I2CS_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) I2CS Synchronization Busy */
#define REG_SERCOM1_I2CS_LENGTH (0x40003422) /**< \brief (SERCOM1) I2CS Length */
#define REG_SERCOM1_I2CS_ADDR (0x40003424) /**< \brief (SERCOM1) I2CS Address */
#define REG_SERCOM1_I2CS_DATA (0x40003428) /**< \brief (SERCOM1) I2CS Data */
#define REG_SERCOM1_SPI_CTRLA (0x40003400) /**< \brief (SERCOM1) SPI Control A */
#define REG_SERCOM1_SPI_CTRLB (0x40003404) /**< \brief (SERCOM1) SPI Control B */
#define REG_SERCOM1_SPI_CTRLC (0x40003408) /**< \brief (SERCOM1) SPI Control C */
#define REG_SERCOM1_SPI_BAUD (0x4000340C) /**< \brief (SERCOM1) SPI Baud Rate */
#define REG_SERCOM1_SPI_INTENCLR (0x40003414) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
#define REG_SERCOM1_SPI_INTENSET (0x40003416) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
#define REG_SERCOM1_SPI_INTFLAG (0x40003418) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM1_SPI_STATUS (0x4000341A) /**< \brief (SERCOM1) SPI Status */
#define REG_SERCOM1_SPI_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) SPI Synchronization Busy */
#define REG_SERCOM1_SPI_LENGTH (0x40003422) /**< \brief (SERCOM1) SPI Length */
#define REG_SERCOM1_SPI_ADDR (0x40003424) /**< \brief (SERCOM1) SPI Address */
#define REG_SERCOM1_SPI_DATA (0x40003428) /**< \brief (SERCOM1) SPI Data */
#define REG_SERCOM1_SPI_DBGCTRL (0x40003430) /**< \brief (SERCOM1) SPI Debug Control */
#define REG_SERCOM1_USART_CTRLA (0x40003400) /**< \brief (SERCOM1) USART Control A */
#define REG_SERCOM1_USART_CTRLB (0x40003404) /**< \brief (SERCOM1) USART Control B */
#define REG_SERCOM1_USART_CTRLC (0x40003408) /**< \brief (SERCOM1) USART Control C */
#define REG_SERCOM1_USART_BAUD (0x4000340C) /**< \brief (SERCOM1) USART Baud Rate */
#define REG_SERCOM1_USART_RXPL (0x4000340E) /**< \brief (SERCOM1) USART Receive Pulse Length */
#define REG_SERCOM1_USART_INTENCLR (0x40003414) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
#define REG_SERCOM1_USART_INTENSET (0x40003416) /**< \brief (SERCOM1) USART Interrupt Enable Set */
#define REG_SERCOM1_USART_INTFLAG (0x40003418) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
#define REG_SERCOM1_USART_STATUS (0x4000341A) /**< \brief (SERCOM1) USART Status */
#define REG_SERCOM1_USART_SYNCBUSY (0x4000341C) /**< \brief (SERCOM1) USART Synchronization Busy */
#define REG_SERCOM1_USART_RXERRCNT (0x40003420) /**< \brief (SERCOM1) USART Receive Error Count */
#define REG_SERCOM1_USART_LENGTH (0x40003422) /**< \brief (SERCOM1) USART Length */
#define REG_SERCOM1_USART_DATA (0x40003428) /**< \brief (SERCOM1) USART Data */
#define REG_SERCOM1_USART_DBGCTRL (0x40003430) /**< \brief (SERCOM1) USART Debug Control */
#else
#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) I2CM Control A */
#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) I2CM Control B */
#define REG_SERCOM1_I2CM_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) I2CM Control C */
#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4000340CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CM Status */
#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */
#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) I2CM Address */
#define REG_SERCOM1_I2CM_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) I2CM Data */
#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) I2CM Debug Control */
#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) I2CS Control A */
#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) I2CS Control B */
#define REG_SERCOM1_I2CS_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) I2CS Control C */
#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) I2CS Status */
#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */
#define REG_SERCOM1_I2CS_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) I2CS Length */
#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) I2CS Address */
#define REG_SERCOM1_I2CS_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) I2CS Data */
#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) SPI Control A */
#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) SPI Control B */
#define REG_SERCOM1_SPI_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) SPI Control C */
#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4000340CUL) /**< \brief (SERCOM1) SPI Baud Rate */
#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) SPI Status */
#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */
#define REG_SERCOM1_SPI_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) SPI Length */
#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x40003424UL) /**< \brief (SERCOM1) SPI Address */
#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) SPI Data */
#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) SPI Debug Control */
#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x40003400UL) /**< \brief (SERCOM1) USART Control A */
#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x40003404UL) /**< \brief (SERCOM1) USART Control B */
#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x40003408UL) /**< \brief (SERCOM1) USART Control C */
#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4000340CUL) /**< \brief (SERCOM1) USART Baud Rate */
#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4000340EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x40003414UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x40003416UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x40003418UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4000341AUL) /**< \brief (SERCOM1) USART Status */
#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4000341CUL) /**< \brief (SERCOM1) USART Synchronization Busy */
#define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x40003420UL) /**< \brief (SERCOM1) USART Receive Error Count */
#define REG_SERCOM1_USART_LENGTH (*(RwReg16*)0x40003422UL) /**< \brief (SERCOM1) USART Length */
#define REG_SERCOM1_USART_DATA (*(RwReg *)0x40003428UL) /**< \brief (SERCOM1) USART Data */
#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x40003430UL) /**< \brief (SERCOM1) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM1 peripheral ========== */
#define SERCOM1_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
#define SERCOM1_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
#define SERCOM1_DMA 1 // DMA support implemented?
#define SERCOM1_DMAC_ID_RX 6 // Index of DMA RX trigger
#define SERCOM1_DMAC_ID_TX 7 // Index of DMA TX trigger
#define SERCOM1_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
#define SERCOM1_GCLK_ID_CORE 8
#define SERCOM1_GCLK_ID_SLOW 3
#define SERCOM1_INT_MSB 6
#define SERCOM1_PMSB 3
#define SERCOM1_RETENTION_SUPPORT 0 // Retention supported?
#define SERCOM1_SE_CNT 1 // SE counter included?
#define SERCOM1_SPI 1 // SPI mode implemented?
#define SERCOM1_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
#define SERCOM1_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
#define SERCOM1_SPI_OZMO 0 // OZMO features implemented?
#define SERCOM1_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
#define SERCOM1_TTBIT_EXTENSION 1 // 32-bit extension implemented?
#define SERCOM1_TWIM 1 // TWI Master mode implemented?
#define SERCOM1_TWIS 1 // TWI Slave mode implemented?
#define SERCOM1_TWIS_AUTO_ACK 1 // TWI slave automatic acknowledge implemented?
#define SERCOM1_TWIS_GROUP_CMD 1 // TWI slave group command implemented?
#define SERCOM1_TWIS_SDASETUP_CNT_SIZE 8 // TWIS sda setup count size
#define SERCOM1_TWIS_SDASETUP_SIZE 4 // TWIS sda setup size
#define SERCOM1_TWIS_SUDAT 1 // TWI slave SDA setup implemented?
#define SERCOM1_TWI_FASTMP 1 // TWI fast mode plus implemented?
#define SERCOM1_TWI_HSMODE 1 // USART mode implemented?
#define SERCOM1_TWI_SCLSM_MODE 1 // TWI SCL clock stretch mode implemented?
#define SERCOM1_TWI_SMB_TIMEOUTS 1 // TWI SMBus timeouts implemented?
#define SERCOM1_TWI_TENBIT_ADR 1 // TWI ten bit enabled?
#define SERCOM1_USART 1 // USART mode implemented?
#define SERCOM1_USART_AUTOBAUD 1 // USART autobaud implemented?
#define SERCOM1_USART_COLDET 1 // USART collision detection implemented?
#define SERCOM1_USART_FLOW_CTRL 1 // USART flow control implemented?
#define SERCOM1_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
#define SERCOM1_USART_IRDA 1 // USART IrDA implemented?
#define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented?
#define SERCOM1_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
#define SERCOM1_USART_RS485 1 // USART RS485 mode implemented?
#define SERCOM1_USART_SAMPA_EXT 1 // USART sample adjust implemented?
#define SERCOM1_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
#endif /* _SAMD51_SERCOM1_INSTANCE_ */

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